sitara-epos/sitara-epos-kernel.git
9 years agoARM: OMAP2+: epwm: Time base clock tree node.
Philip, Avinash [Sat, 10 Mar 2012 11:29:55 +0000 (16:59 +0530)]
ARM: OMAP2+: epwm: Time base clock tree node.

pwmssctrl register (in control module) that controls time base clock
needs to be configured for proper working of ePWM. Time base module is
part of ePWM IP, and it's clock enabled through control module.

Enabling time base clock is handled by adding clock tree node and by
flagging it with ENABLE_ON_INIT.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoARM: OMAP2+: am33xx: Adds PWMSS control register
Philip, Avinash [Mon, 12 Mar 2012 07:17:22 +0000 (12:47 +0530)]
ARM: OMAP2+: am33xx: Adds PWMSS control register

Adds definitions for PWMSS control register.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoARM: OMAP2+: am33xx: Enable UBIFS support in defconfig
Philip, Avinash [Tue, 13 Mar 2012 07:29:55 +0000 (12:59 +0530)]
ARM: OMAP2+: am33xx: Enable UBIFS support in defconfig

UBIFS is the default file system for NAND MTD devices in am33xx
platforms. Hence enable the defconfig for UBIFS support.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoARM: OMAP: AM33XX: PM: Manipulate MPU voltage in suspend-resume
Vaibhav Bedia [Mon, 12 Mar 2012 18:15:27 +0000 (23:45 +0530)]
ARM: OMAP: AM33XX: PM: Manipulate MPU voltage in suspend-resume

As per the AM335x datasheet, when going to the lowest power
mode, DeepSleep0 in the docs, MPU and CORE voltages should be
scaled down to 0.95V. This is currently done via clk and regulator
APIs in the suspend-resume code.

Since the I2C driver implements aggressive RPM, we also need
to disable this during the suspend process.

Note: We are a little bit paranoid and currently scale down the
voltage to 0.965V instead of 0.95V to accomodate for some IR drop
that was earlier seen on the EVMs.

TODO:
1. Add some more error handling here
2. Check if MPU change can be moved into the cpufreq driver
3. Check if there's a better way of keeping I2C enabled very late
   in the suspend process.
4. Scale the CORE voltage also.

Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
9 years agocpufreq: OMAP: Disable cpufreq during suspend
Vaibhav Bedia [Mon, 12 Mar 2012 18:05:47 +0000 (23:35 +0530)]
cpufreq: OMAP: Disable cpufreq during suspend

On AM335x, we need to reconfigure the PLLs and voltage
during suspend. With regulator calls in the suspend code
errors were reported by the cpufreq driver in the resume
path. This is probably because cpufreq is suspended
very late in the overall suspend process.

For now, we make use of SUSPEND_PREPARE notification
to block any further OPP changes from the driver.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
9 years agoARM: OMAP: AM33XX: PM: Wait for M3 state machine reset in suspend failure
Vaibhav Bedia [Mon, 12 Mar 2012 14:10:41 +0000 (19:40 +0530)]
ARM: OMAP: AM33XX: PM: Wait for M3 state machine reset in suspend failure

In case something goes wrong in the suspend sequence, A8 sends a command
to M3 to reset its state machine. After this A8 continues with its
resume process and eventually enters idle loop. The command for reset
depends on the mailbox interrupt being generated and M3 responding it.
However, in case A8 enters the idle loop before M3 has responded to the
command for reset, M3 might cut the power to A8 thereby causing a "hang"
in the A8 world. Although the chances of the above happening is very
rare, it can and should be fixed. This is currently done by waiting for
the command posted to M3 to complete and then continuing with the resume
process.

Note: This also enforced a minor change in the M3 code and it is
recommended that the firmware binary is updated to the latest one
available on Arago.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
9 years agoinput: TSC: return with error incase of probe fail
Patil, Rachna [Mon, 12 Mar 2012 13:24:53 +0000 (18:54 +0530)]
input: TSC: return with error incase of probe fail

This patch corrects error handling in touchscreen.

Signed-off-by: Patil, Rachna <rachna@ti.com>
9 years agousb: musb: pm: update resume timeout fix
Ajay Kumar Gupta [Mon, 12 Mar 2012 06:41:21 +0000 (12:11 +0530)]
usb: musb: pm: update resume timeout fix

Further testing shows that musb controller just needs a delay of 200ms
after restoring devctl register and so removing SESSION off and on being
done is suspend and resume path.

9 years agoARM: OMAP: AM33XX: Add VDD_CORE data for the PLL
Vaibhav Bedia [Mon, 12 Mar 2012 09:44:25 +0000 (15:14 +0530)]
ARM: OMAP: AM33XX: Add VDD_CORE data for the PLL

VDD2 of TPS65910 maps to VDD_CORE of AM335x. To make
use of the regulator APIs for changing this voltage add
the data for VDD2 to the info registered with the
regulator framework.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
9 years agoARM: OMAP: AM33XX: Update defconfig with PM support
Vaibhav Bedia [Mon, 12 Mar 2012 09:31:13 +0000 (15:01 +0530)]
ARM: OMAP: AM33XX: Update defconfig with PM support

With most of the PM related code merged in enable
PM support in the defconfig.

Note: PM support depends on the CM3 firmare binary
which is compiled into the kernel image. The latest
image can be obtained from Arago and needs to be placed
in the firmware directory of the kernel.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
9 years agoARM: OMAP: AM33XX: Fix build warning in PM code
Vaibhav Bedia [Mon, 12 Mar 2012 09:22:30 +0000 (14:52 +0530)]
ARM: OMAP: AM33XX: Fix build warning in PM code

The code for disabling unused clockdomains is required
only when PM is fully enabled. To avoid a build warning
related to unused function move the code under the config
option for suspend

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
9 years agovideo: da8xx-fb: fix build warning
Patil, Rachna [Mon, 12 Mar 2012 06:04:55 +0000 (11:34 +0530)]
video: da8xx-fb: fix build warning

This patch removes the build warning related to LCD

Signed-off-by: Patil, Rachna <rachna@ti.com>
9 years agousb: musb: pm: fix resume timeout
Ajay Kumar Gupta [Sat, 10 Mar 2012 06:44:36 +0000 (12:14 +0530)]
usb: musb: pm: fix resume timeout

Fixes control transfer timeout and followed by re-enumeration of usb
devices after resume.

We need to switch off the session before DEVCTL register context save
and switch on the session before restoring POWER register context.

9 years agoPWM: ehrpwm: Replace __raw [read/write] with read/write variant
Philip, Avinash [Sat, 10 Mar 2012 06:52:28 +0000 (12:22 +0530)]
PWM: ehrpwm: Replace __raw [read/write] with read/write variant

Replaces __raw_read/__raw_write functions with read/wrte, as this
functions inserts memory barrier instructions required with ARMv6+

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoARM: OMAP: AM33XX: Restore padconf across low power state
Vaibhav Bedia [Fri, 9 Mar 2012 18:52:25 +0000 (00:22 +0530)]
ARM: OMAP: AM33XX: Restore padconf across low power state

Some specific padconf registers need to be saved and restored
in low power state. For now this is being done in the PM
code. One alternative to be explored is the usage of callbacks
functions in the various drivers to save and restore the padconf.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
9 years agoARM: OMAP: AM33XX: Rename the firmware binary
Vaibhav Bedia [Fri, 9 Mar 2012 15:47:48 +0000 (21:17 +0530)]
ARM: OMAP: AM33XX: Rename the firmware binary

Update the name of the firmware binary to be loaded
onto Cortex-M3 for low power transitions.

If the binary is not provided at the time of kernel
compilation there's a timeout of 60 seconds. To avoid
creating any confusion due to missing binary add a
message indicating that the firmware is now going
to be loaded.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
9 years agoARM: OMAP: AM33XX: Yet one more DS0 update
Vaibhav Bedia [Thu, 8 Mar 2012 14:42:15 +0000 (20:12 +0530)]
ARM: OMAP: AM33XX: Yet one more DS0 update

When suspending the PHY is programmed in mDDR mode
and the PLLs put in LP bypass mode.

While at it also cleanup the low level assembly code
and PM code. Also fixup the error message in case of
suspend failure

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
9 years agoMTD: OMAP2: elm: Fix NULL pointer dereference.
Philip, Avinash [Fri, 9 Mar 2012 16:13:03 +0000 (21:43 +0530)]
MTD: OMAP2: elm: Fix NULL pointer dereference.

NULL pointer derefence causes following crash.

[root@arago /]# echo mem > /sys/power/state
[   20.288726] PM: Syncing filesystems ... done.
[   20.300842] Freezing user space processes ... (elapsed 0.01 seconds)
done.
[   20.325897] Freezing remaining freezable tasks ... (elapsed 0.01
seconds) done.
[   20.350097] Unable to handle kernel NULL pointer dereference
at virtual address 0000009c
[   20.358581] pgd = cf97c000
[   20.361389] [0000009c] *pgd=8d176831, *pte=00000000,
*ppte=00000000
[   20.367950] Internal error: Oops: 17 [#1]
[   20.372131] Modules linked in:
[   20.375335] CPU: 0    Not tainted  (3.2.0-12326-gf5f1c1a
[   20.381439] PC is at omap_elm_suspend+0x20/0x3c
[   20.386169] LR is at platform_pm_suspend+0x58/0x64

This patch fixes the same.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoARM: OMAP2+: elm: Creates device on available profiles.
Philip, Avinash [Fri, 9 Mar 2012 16:33:22 +0000 (22:03 +0530)]
ARM: OMAP2+: elm: Creates device on available profiles.

This patch corrects creation of ELM device for profiles where NAND is
available. Previously ELM device was created from arch_initcal().

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoARM: OMAP2+: nand: check for proper return value
Philip, Avinash [Fri, 9 Mar 2012 16:08:31 +0000 (21:38 +0530)]
ARM: OMAP2+: nand: check for proper return value

Return value was not checked in evm_nand_init and because of that below
crash was generated during runtime.

[    1.004381] Unable to handle kernel NULL pointer dereference at
virtual address 00000028
[    1.012864] pgd = c0004000
[    1.015688] [00000028] *pgd=00000000
[    1.019424] Internal error: Oops: 805 [#1]
[    1.023692] Modules linked in:
[    1.026881] CPU: 0    Not tainted  (3.2.0-12213-ge873350 #365)
[    1.032992] PC is at evm_nand_init+0x34/0x5c

This patch fixes the same.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoARM: OMAP2+: nand: Fix build breakage.
Philip, Avinash [Fri, 9 Mar 2012 16:49:19 +0000 (22:19 +0530)]
ARM: OMAP2+: nand: Fix build breakage.

This patch fixes the build breakage

arch/arm/mach-omap2/board-flash.c: In function 'board_flash_init':
arch/arm/mach-omap2/board-flash.c:246:16: error:
'nand_default_timings' undeclared (first use in this function)
arch/arm/mach-omap2/board-flash.c:246:16: note: each undeclared
identifier is reported only once for each function it appears in
make[1]: *** [arch/arm/mach-omap2/board-flash.o] Error 1
make: *** [arch/arm/mach-omap2] Error 2
make: *** Waiting for unfinished jobs....

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoARM: OMAP3+: am33xx_hwmod: Fix the GPIO SYSCONFIG data
Vaibhav Bedia [Fri, 9 Mar 2012 13:48:52 +0000 (19:18 +0530)]
ARM: OMAP3+: am33xx_hwmod: Fix the GPIO SYSCONFIG data

GPIO0 can wakeup the system from low power states and this
requires the ENWAKEUP bit in the SYSCONFIG to be set.

Programming the SYSCONFIG is currently handled by the hwmod
code and hence update the SYSCONFIG register to program
this register correctly during bootup.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
9 years agoASoC: McASP: add suspend/resume support
Hebbar, Gururaja [Fri, 2 Mar 2012 03:20:33 +0000 (08:50 +0530)]
ASoC: McASP: add suspend/resume support

This patch currently adds pm_runtime_[put/get]_sync calls with context
save/restore feature.
This feature is yet to be tested. This Feature is only supported for
IP version = 3 (AM335x)

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
9 years agoASoC: McASP: use runtime PM for better clock handling
Hebbar, Gururaja [Thu, 1 Mar 2012 12:46:19 +0000 (18:16 +0530)]
ASoC: McASP: use runtime PM for better clock handling

Convert the mcasp driver to use runtime PM. This will use HWMOD data
which is preferred upon regular clk_[disable/enable]

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
9 years agoASoC: McASP: update resource request for DMA type
Hebbar, Gururaja [Tue, 28 Feb 2012 09:34:50 +0000 (15:04 +0530)]
ASoC: McASP: update resource request for DMA type

McASP device registration now uses omap_device api. This method
doesn't declare resource in order. Hence this patch replaces
platform_get_resource() with platform_get_resource_byname()

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
9 years agoARM: OMAP2+: am33xx: update mcasp platform registration
Hebbar, Gururaja [Tue, 28 Feb 2012 08:42:56 +0000 (14:12 +0530)]
ARM: OMAP2+: am33xx: update mcasp platform registration

McASP device registration now uses omap_device api. This change needs a
new argument (device id). This patch changes the call to involve device
id along with platform data.

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
9 years agoARM: OMAP2+: mcasp: use omap_device api for registration
Hebbar, Gururaja [Tue, 28 Feb 2012 08:40:27 +0000 (14:10 +0530)]
ARM: OMAP2+: mcasp: use omap_device api for registration

Convert the old-style device registration code for mcasp to use
omap_device.  This will allow the driver to be converted to use PM
runtime and to take advantage of the OMAP IP block management
infrastructure (hwmod, PM, etc.).

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
9 years agoARM: OMAP2+: mcasp: add missing HWMOD data
Hebbar, Gururaja [Tue, 28 Feb 2012 06:36:10 +0000 (12:06 +0530)]
ARM: OMAP2+: mcasp: add missing HWMOD data

HWMOD data regarding edma interrupts, sysconfig for McASP were
missing. This patch adds the same.

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
9 years agoASoC: McASP: Correct FIFOCTL register usage
Hebbar, Gururaja [Mon, 27 Feb 2012 09:47:22 +0000 (15:17 +0530)]
ASoC: McASP: Correct FIFOCTL register usage

Write FIFO register (WFIFOCTL) offset was incorrectly used in place
of Read FIFO register for McASP IP version 3. This patch corrects
the same.

TODO:
1. Differentiating the IP versions at runtime if it's possible

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
9 years agoARM: OMAP2+: ALSA : ASoC tlv320aic3x.c suspend/resume cache_sync fix
Raj, Deepu [Mon, 21 Nov 2011 06:59:20 +0000 (12:29 +0530)]
ARM: OMAP2+: ALSA : ASoC tlv320aic3x.c suspend/resume cache_sync fix

 This patch fixes audio resume failure. AIC3X codec driver is not
 generating disable regulator event due to unknown reason.
 Need to revisit the patch to find the reason and fix the same.

Signed-off-by: Raj, Deepu <deepu.raj@ti.com>
Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
9 years agoASoC: Davinci: Correct the rotation for different data-types
Vaibhav Bedia [Sat, 1 Oct 2011 11:29:00 +0000 (16:59 +0530)]
ASoC: Davinci: Correct the rotation for different data-types

During audio Rx none of the data-types need rotation in the
Receive Format Unit of the McASP

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
9 years agoARM: OMAP: AM33XX: NET: cpsw: Add suspend resume support
Mugunthan V N [Thu, 8 Mar 2012 12:21:47 +0000 (17:51 +0530)]
ARM: OMAP: AM33XX: NET: cpsw: Add suspend resume support

Need to reset all sub-components of CPGMAC to gate the clock

Moved omap_dm_timer enable and configure to cpsw_ndo_open and disabled the
timer in cpsw_ndo_close so that during suspend/resume timer will be disabled
and enabled respectively

Added timer omap_dm_timer_free in cpsw_ndo_remove to free the dm_timer while
removing the module

Added wait_for_clock_enable to ensure that CPGMAC clock is enabled before
accessing the CPGMAC registers

TODO: Currently driver doesnot support pm runtime, so hack for wait for cpgmac
clock enable is done. Once PM runtime support is done then the hack will be
removed

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
9 years agoARM: OMAP: AM33XX: NET: cpsw: fix memory lead during device open close.
Mugunthan V N [Thu, 8 Mar 2012 04:12:02 +0000 (09:42 +0530)]
ARM: OMAP: AM33XX: NET: cpsw: fix memory lead during device open close.

Rx descriptors are not freed during cpdma close in device close.

cpdma_ctlr_stop should be called after netif_carrier_off. so that
cpsw_rx_handler knows that we are shutting down the network device
and free the Rx descriptor memory

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
9 years agoARM: OMAP2+: nand: Fix build breakage
Vaibhav Bedia [Fri, 9 Mar 2012 14:30:05 +0000 (20:00 +0530)]
ARM: OMAP2+: nand: Fix build breakage

...introduced by recent NAND related changes

In file included from arch/arm/mach-omap2/board-omap3beagle.c:54:0:
arch/arm/mach-omap2/board-flash.h:50:1: error: expected identifier or '(' before '{' token
arch/arm/mach-omap2/board-flash.h:48:1: warning: 'omap_nand_init' used but never defined
make[1]: *** [arch/arm/mach-omap2/board-omap3beagle.o] Error 1
make[1]: *** Waiting for unfinished jobs....
In file included from arch/arm/mach-omap2/board-am335xevm.c:61:0:
arch/arm/mach-omap2/board-flash.h:50:1: error: expected identifier or '(' before '{' token
arch/arm/mach-omap2/board-flash.h:48:1: warning: 'omap_nand_init' used but never defined
make[1]: *** [arch/arm/mach-omap2/board-am335xevm.o] Error 1

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
9 years agovideo: da8xx-fb: correct suspend/resume sequence
Patil, Rachna [Fri, 9 Mar 2012 12:45:37 +0000 (18:15 +0530)]
video: da8xx-fb: correct suspend/resume sequence

1. correct suspend/resume sequence
for LCD.
2. add msleep in suspend/resume, to allow
LCD to finish transmitting all the frames.
3. remove enabling/disabling of clocks in
interrupt handler. This sequence was wrong.
Trying to disable clocks and write to a register
was wrong.
4. correct LCD context save sequence

Signed-off-by: Patil, Rachna <rachna@ti.com>
9 years agovideo: da8xx-fb: enable sync and underflow error interrupts
Patil, Rachna [Thu, 8 Mar 2012 11:41:49 +0000 (17:11 +0530)]
video: da8xx-fb: enable sync and underflow error interrupts

This patch enables LCD sync and underflow error interrupts.

Signed-off-by: Patil, Rachna <rachna@ti.com>
9 years agommc: omap_hsmmc: set dto to 14 for all devices
Chase Maupin [Fri, 9 Mar 2012 13:13:05 +0000 (18:43 +0530)]
mmc: omap_hsmmc: set dto to 14 for all devices

* With certain SD cards timeouts like the following have been seen
  due to an improper calculation of the dto value:
    mmcblk0: error -110 transferring data, sector 4126233, nr 8,
    card status 0xc00
* By removing the dto calculation and setting the timeout value
  to the maximum specified by the SD card specification part A2
  section 2.2.15 these timeouts can be avoided.
* This change has been used by beagleboard users as well as the
  Texas Instruments SDK without a negative impact.
* There are multiple discussion threads about this but the most
  relevant ones are:
    * http://talk.maemo.org/showthread.php?p=1000707#post1000707
    * http://www.mail-archive.com/linux-omap@vger.kernel.org/msg42213.html
* Original proposal for this fix was done by Sukumar Ghoral of
  Texas Instruments

* Tested using a Texas Instruments AM335x EVM

Signed-off-by: Chase Maupin <Chase.Maupin@ti.com>
9 years agoARM: OMAP: AM33XX: Fix build breakage when CONFIG_SUSPEND=n
Sekhar Nori [Fri, 9 Mar 2012 12:47:50 +0000 (18:17 +0530)]
ARM: OMAP: AM33XX: Fix build breakage when CONFIG_SUSPEND=n

Fix the following build error:

arch/arm/mach-omap2/pm33xx.c: In function 'am33xx_pm_init':
arch/arm/mach-omap2/pm33xx.c:462:2: error: 'cefuse_pwrdm' undeclared (first use in this function)
arch/arm/mach-omap2/pm33xx.c:462:2: note: each undeclared identifier is reported only once for each function it appears in
arch/arm/mach-omap2/pm33xx.c:468:2: error: 'gfx_pwrdm' undeclared (first use in this function)
arch/arm/mach-omap2/pm33xx.c:472:2: error: 'gfx_l3_clkdm' undeclared (first use in this function)
arch/arm/mach-omap2/pm33xx.c:476:2: error: 'gfx_l4ls_clkdm' undeclared (first use in this function)

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
9 years agoARM: OMAP2+: timer: Switch dmtimer1/clocksource to RTC32k source for am33xx
Vaibhav Hiremath [Wed, 7 Mar 2012 06:55:10 +0000 (12:25 +0530)]
ARM: OMAP2+: timer: Switch dmtimer1/clocksource to RTC32k source for am33xx

In case of AM33xx support, currently the system timer is configured
as -
- clockevent - dmtimer2 (peripheral domain)
- clocksource - dmtimer1 (wakeup domain)

Both are getting input from OSC clock, which is 24MHz input clock.
In order to keep dmtimer1/clocksource active during system
suspend/resume, we must use RTC32K clock.
This patch enables the RTC32K clock by writting RTC registers and
switches clocksource/dmtimer1 input clock to RTC32k/clk_32768_ck.

Also, during testing it has been observed that, RTC clock need couple
of seconds delay to stabilize the RTC clock; and such a huge delay is not
acceptable in kernel and will also impact quick/fast boot use-case.
So, RTC32k OSC enable code has been shifted to SPL/first-bootloader,
and in order to support older u-boot, we have adopted fallback mechanism;
where, if timer goes to bad state OR becomes idle, then we again switch
back to main/default sys_ck_in (24MHz).

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
9 years agoARM: OMAP3+: am33xx_clockdata: Fix wrong rtc parent clock
Vaibhav Hiremath [Wed, 7 Mar 2012 07:05:10 +0000 (12:35 +0530)]
ARM: OMAP3+: am33xx_clockdata: Fix wrong rtc parent clock

Fix -
- Corrected RTC32K clock defination
- Wrong parent was configured to RTC
- Wrong clock domain to USB module.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
9 years agoARM: OMAP: AM33XX: Manipulate GFX domain during suspend
Vaibhav Bedia [Wed, 7 Mar 2012 20:39:27 +0000 (02:09 +0530)]
ARM: OMAP: AM33XX: Manipulate GFX domain during suspend

In order to save as much power as possible, attempt to
put the GFX domain to OFF state during suspend.

At the same time, update the A<->M3 interaction to reduce
any chance of race conditions between A8 suspend routine
and the M3 acknowledgement interrupt.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
9 years agoARM: OMAP: AM33XX: Don't idle during suspend
Vaibhav Bedia [Tue, 6 Mar 2012 15:48:02 +0000 (21:18 +0530)]
ARM: OMAP: AM33XX: Don't idle during suspend

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
9 years agoARM: OMAP: AM335x evm: Getting rid of memory accessors with barriers
Vaibhav Bedia [Tue, 6 Mar 2012 06:42:07 +0000 (12:12 +0530)]
ARM: OMAP: AM335x evm: Getting rid of memory accessors with barriers

We should be using readl/writel since they have barriers in place

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
9 years agoARM: OMAP: PM: Skip omap3_init_voltage for AM33XX
Vaibhav Bedia [Tue, 6 Mar 2012 05:40:13 +0000 (11:10 +0530)]
ARM: OMAP: PM: Skip omap3_init_voltage for AM33XX

Right now this helps to get rid of the following warnings during
bootup

[...]
omap2_set_init_voltage: unable to get clk dpll1_ck
omap2_set_init_voltage: unable to set vdd_mpu_iva
omap2_set_init_voltage: unable to find boot up OPP for vdd_core
omap2_set_init_voltage: unable to set vdd_core
[...]

We need to explore whether an AM33XX specific init_voltage is
required or we can make do with that OMAP3/4 has to offer.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
9 years agoARM: OMAP3+: am33xx_clkdomain: Add CLKDM_NO_AUTODEPS flag
Vaibhav Bedia [Tue, 6 Mar 2012 04:53:54 +0000 (10:23 +0530)]
ARM: OMAP3+: am33xx_clkdomain: Add CLKDM_NO_AUTODEPS flag

...since it's not available in hardware.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
9 years agoARM: OMAP: am33xx: Keep the CLKDIV32K running for now
Vaibhav Bedia [Mon, 5 Mar 2012 15:24:08 +0000 (20:54 +0530)]
ARM: OMAP: am33xx: Keep the CLKDIV32K running for now

The debounce clk for GPIO is derived from CLKDIV32K.
Without enabling this module the DBCLK activity bit
of GPIO3 alone is not getting cleared even though the
clock has been disabled. For now enable the module.

TODO: Check if the clock tree dependency to have the module
enabled when the debounce feature is correct. If it is,
then GPIO3 usage needs to be looked at. Since the mainline
code of GPIO has undergone significant changes, it would
perhaps make sense to pull in those patches and then look
into this issue.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
9 years agoARM: OMAP2+: sys_timer: Add suspend/resume callback api's to sys_timer
Vaibhav Hiremath [Mon, 5 Mar 2012 05:52:39 +0000 (11:22 +0530)]
ARM: OMAP2+: sys_timer: Add suspend/resume callback api's to sys_timer

In case of AM335x, we do not 32k_counter available, which
is actually being used as source timer in OMAP family of devices.
AM335x has 8 timer modules, 2 timer modules are in wakeup/always-on
domain, and out of these 2, 1 timer is secure timer; which
leaves SW to use only 1 timer which can run in off/suspend state.
And we need 2 timers, one for clockevent and another for clocksource.

The suspend/resume callbacks are available on sys_timer and
clocksource, but due to unknown reason clocksource callbacks are
not working. TODO: WE MUST DEBUG FURTHER ON THIS.

So as of now, enable sys_timer suspend/resume callback.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
9 years agoARM: TIME: Enable sys_timer suspend/resume callback api's
Vaibhav Hiremath [Mon, 5 Mar 2012 05:23:00 +0000 (10:53 +0530)]
ARM: TIME: Enable sys_timer suspend/resume callback api's

In case of AM335x, we do not 32k_counter available, which
is actually being used as source timer in OMAP family of devices.
AM335x has 8 timer modules, 2 timer modules are in wakeup/always-on
domain, and out of these 2, 1 timer is secure timer; which leaves
SW to use only 1 timer which can run in off/suspend state. And
we need 2 timers, one for clockevent and another for clocksource.

The suspend/resume callbacks are available on sys_timer and
clocksource, but due to unknown reason clocksource callbacks are
not working. TODO: WE MUST DEBUG FURTHER ON THIS.

The sys_timer suspend/resume callback api's are supressed
under config option !defined(CONFIG_GENERIC_CLOCKEVENTS),
enable it, required for AM335x suspend/resume funtionality.
Not sure, why it is not enabled and appliable to ARM arch, will
have to follow up it with community.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
9 years agoARM: OMAP3+: am33xx_hwmod: Correct the usb clkdm_name
Vaibhav Hiremath [Mon, 5 Mar 2012 14:27:26 +0000 (19:57 +0530)]
ARM: OMAP3+: am33xx_hwmod: Correct the usb clkdm_name

Correct the usb clock domain name to "l3s_clkdm".

The USB peripheral doesn't have any seperate clock domain of its
own, it falls under "l3s_clkdm".

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
9 years agoARM: OMAP: AM33XX: Cleanup usb hwmod
Ajay Kumar Gupta [Mon, 27 Feb 2012 09:42:34 +0000 (15:12 +0530)]
ARM: OMAP: AM33XX: Cleanup usb hwmod

Updated the hwmod data for usb pm support.
Changes:
- updated the sysc type to type2
- Added the interface and functional clock and removed opt clocks

Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
9 years agoARM: OMAP: AM33XX: Update the sleep code for DS0
Vaibhav Bedia [Thu, 9 Feb 2012 17:37:26 +0000 (23:07 +0530)]
ARM: OMAP: AM33XX: Update the sleep code for DS0

Add some error handling and update the code to
make use of DeepSleep0 mode.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
9 years agoARM: OMAP: AM33XX: Update the flags in HWMOD
Vaibhav Bedia [Thu, 9 Feb 2012 17:34:02 +0000 (23:04 +0530)]
ARM: OMAP: AM33XX: Update the flags in HWMOD

For the modules which require special handling, update
the flags in the hwmod data. WIth this done, the PM
framework takes care of the special handling for the
modules.

Note: With HWMOD_SWSUP_MSTANDBY set, the module goes
to standby during boot. Unless the driver makes use
of runtime PM APIs the module will stay in standby
which is not desired. For now we disable idling
this modules during the boot. When the drivers start
making use of runtime PM this workaround must be
removed.

All this should eventually make its way into the
appropriate drivers.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
9 years agoARM: OMAP: AM33XX: Make use of DMTIMER0 for now
Vaibhav Bedia [Thu, 9 Feb 2012 17:31:12 +0000 (23:01 +0530)]
ARM: OMAP: AM33XX: Make use of DMTIMER0 for now

Need to check how to do this reliably

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
9 years agoRevert "arm:omap:gpio - Handle Clocks properly in Suspend/Resume"
Vaibhav Bedia [Thu, 9 Feb 2012 09:33:01 +0000 (15:03 +0530)]
Revert "arm:omap:gpio - Handle Clocks properly in Suspend/Resume"

This reverts commit bbfb01e1cc06c1f041060258ca93b260e0c83c41.

9 years agovideo: da8xx-fb: correct read/write API's used.
Patil, Rachna [Thu, 8 Mar 2012 11:22:28 +0000 (16:52 +0530)]
video: da8xx-fb: correct read/write API's used.

This patch replaces raw read/write with readl/writel.

Signed-off-by: Patil, Rachna <rachna@ti.com>
9 years agoMTD: OMAP2: Add support for low power sleep for NAND
Philip, Avinash [Thu, 16 Feb 2012 07:05:41 +0000 (12:35 +0530)]
MTD: OMAP2: Add support for low power sleep for NAND

Support for NAND low power done by
1. Waiting for ongoing MTD operation to finish before entering low power
mode.
2. Invokes GPMC callbacks to handle GPMC low power transitions.
3. ELM suspend activity waiting for ongoing MTD transfer to finish and
handle ELM low power transition cycle by configuring.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoARM: OMAP2+: gpmc: Add low power support
Philip, Avinash [Mon, 27 Feb 2012 06:00:40 +0000 (11:30 +0530)]
ARM: OMAP2+: gpmc: Add low power support

This patch adds Callback functions to support low power transitions by
adding
1. pm_runtime API's to handle GPMC power transitions
2. GPMC save/restore context.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoARM: OMAP2+: gpmc: Handle clock by pm_runtime API
Philip, Avinash [Mon, 5 Mar 2012 14:19:36 +0000 (19:49 +0530)]
ARM: OMAP2+: gpmc: Handle clock by pm_runtime API

This patch updates clock API to pm_runtime API for GPMC clock
activity. This will use HWMOD data which is preferred upon regular
clk_[disable/enable].

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoARM: OMAP2+: nand: Changing SPL and U-boot partition permission
Philip, Avinash [Fri, 18 Nov 2011 09:18:39 +0000 (14:48 +0530)]
ARM: OMAP2+: nand: Changing SPL and U-boot partition permission

SPL and U-boot partition provided with write permission in order to
update SPL and U-boot from kernel.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
9 years agoMTD: omap2: 14 byte ECC support for BCH8
Philip, Avinash [Thu, 17 Nov 2011 14:43:56 +0000 (20:13 +0530)]
MTD: omap2: 14 byte ECC support for BCH8

14 bytes of ECC is provided for every 512 byte even though 13 byte is the
actual requirement. This is to synchronize the ECC layout with U-boot.
Extra byte is cleared to 0.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
9 years agoARM: OMAP2+: am335x: Enables BCH8 support for NAND
Philip, Avinash [Tue, 6 Mar 2012 05:55:10 +0000 (11:25 +0530)]
ARM: OMAP2+: am335x: Enables BCH8 support for NAND

Enables BCH8 ECC support on AM335x SOC.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoMTD: omap2: Corrects BCH8 support
Philip, Avinash [Tue, 6 Mar 2012 05:54:39 +0000 (11:24 +0530)]
MTD: omap2: Corrects BCH8 support

This patch
1. Adds separate read path to handle BCH ECC scheme.
2. Adds macros to support BCH8 ECC scheme.
3. Adds ECC correction path for BCH8 ECC scheme.
4. Corrects the ECC layout for BCH8.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoARM: OMAP2+: gpmc: Corrects BCH8 support
Philip, Avinash [Tue, 6 Mar 2012 05:54:00 +0000 (11:24 +0530)]
ARM: OMAP2+: gpmc: Corrects BCH8 support

Corrects the GPMC configuration to support BCH8 ECC scheme.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoARM: OMAP2+: am335x: Enable ELM feature.
Philip, Avinash [Tue, 6 Mar 2012 05:36:53 +0000 (11:06 +0530)]
ARM: OMAP2+: am335x: Enable ELM feature.

Enable support for ELM on AM335x SOC

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoMTD: OMAP2+: elm: Initialize ELM module when needed
Philip, Avinash [Mon, 20 Feb 2012 12:11:55 +0000 (17:41 +0530)]
MTD: OMAP2+: elm: Initialize ELM module when needed

This patch configures ELM module for BCH8 ECC scheme on platforms where it is
being used.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoARM: OMAP2+: elm: Correct ELM device instance
Philip, Avinash [Thu, 16 Feb 2012 09:40:38 +0000 (15:10 +0530)]
ARM: OMAP2+: elm: Correct ELM device instance

This patch
1. Corrects the device id for ELM device to -1 as only one instance of ELM
is present, previously it was 1.
2. Adds error handling for failure cases.
3. Provides __init macros to free the memory once initialization done.
4. Corrects to make use inline function definition to remove unnecessary
calls.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoARM: OMAP2+: nand: Flag to support ELM feature on platforms.
Philip, Avinash [Wed, 22 Feb 2012 07:53:03 +0000 (13:23 +0530)]
ARM: OMAP2+: nand: Flag to support ELM feature on platforms.

This patch introduces a platform data flag to selectively enable/disable
ELM feature for NAND. On platforms where ELM support is present, this
flag needs to be set as true.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoMTD: OMAP2: elm: Add ELM module support
Philip, Avinash [Mon, 20 Feb 2012 08:19:43 +0000 (13:49 +0530)]
MTD: OMAP2: elm: Add ELM module support

This patch adds
1. ELM feature support for BCH ECC error correction.
2. Configuration API support for BCH8 ECC scheme.
3. Exports symbols to support module build.

TODO:
Updating to pm_ops
Handling multiple SYNDROME Calculation and page mode support.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoMTD: Fixes Coding style
Philip, Avinash [Wed, 29 Feb 2012 12:50:42 +0000 (18:20 +0530)]
MTD: Fixes Coding style

Fixes coding style Error in Makefile "\ No newline at end of file"

Signed-off-by: Philip, Evania's <avinashphilip@ti.com>
9 years agoARM: OMAP2+: nand: BCH8 support definitions
Philip, Avinash [Tue, 6 Mar 2012 05:28:30 +0000 (10:58 +0530)]
ARM: OMAP2+: nand: BCH8 support definitions

This patch adds
1. Enum variable for BCH type
2. Macro definitions to support BCH8 ECC scheme
3. Function declarations.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoARM: OMAP2+: nand: Updated JFFS2 clean marker offset.
Philip, Avinash [Mon, 17 Oct 2011 06:21:25 +0000 (11:51 +0530)]
ARM: OMAP2+: nand: Updated JFFS2 clean marker offset.

JFFS2 clean marker offset used by Linux in case of 8-bit NAND device was
0x1 omap2 NAND driver. But 1st 2 bytes is used to indicate bad blocks by
manufacturers. So offset for JFFS2 clean markers is fixed to 0x2 in
omap2 NAND driver irrespective of 8/16 bit device.

Introduced new macro : JFFS2_CLEAN_MARKER_OFFSET to indicate 0x2 offset
for JFFS2 clean marker.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
9 years agoARM: OMAP2+: nand: Synching HAMMING ECC layout with that of U-boot.
Vaibhav Hiremath [Sat, 26 Nov 2011 20:22:47 +0000 (01:52 +0530)]
ARM: OMAP2+: nand: Synching HAMMING ECC layout with that of U-boot.

For OOb_64, offset is fixed to 40 for kernel/fs, by changing
kernel code to calculate hw_ecc layout considering these:
1) 12 bytes in case of 512 byte access and 24 bytes in case of 256 byte
access in OOB_64 can be supported.
2) Ecc bytes lie to the end of OOB area.
Introducing a new macro : MAX_HWECC_BYTES_OOB_64 which is the maximum
number of eccbytes supported for OOB_64n Hamming ECC mode.

Signed-off-by: Hrishikesh Bhandiwad <hrishikesh.b@ti.com>
Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
9 years agoARM: OMAP2+: nand: Support for BCH
Philip, Avinash [Tue, 6 Mar 2012 04:57:03 +0000 (10:27 +0530)]
ARM: OMAP2+: nand: Support for BCH

Patch is derived from "omap3: nand: bch ecc support added"
available at:
http://arago-project.org/git/projects/?p=linux-omap3.git;a=commit;
f=arch/arm/mach-omap2/gpmc.c;hb=79f5ddc6

This patch has the following modification
1. Removes the BCH4 support as it is not tested.
2. Configures GPMC for BCH ECC support.
3. Adds BCH ECC layout definitions.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoARM: OMAP2+: am335x: Selects HAMMING ECC scheme.
Philip, Avinash [Tue, 6 Mar 2012 04:36:26 +0000 (10:06 +0530)]
ARM: OMAP2+: am335x: Selects HAMMING ECC scheme.

Selects ECC scheme to Hamming code for NAND.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoARM: OMAP2+: am335x: GPMC device registration
Philip, Avinash [Tue, 6 Mar 2012 04:06:27 +0000 (09:36 +0530)]
ARM: OMAP2+: am335x: GPMC device registration

Registers GPMC device using HWMOD API. Also provides the platform data
for the devices connected on GPMC controller, in this case NAND flash
device.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoARM: OMAP2+: hwmod: Corrects GPMC HWMOD data
Philip, Avinash [Thu, 23 Feb 2012 11:06:56 +0000 (16:36 +0530)]
ARM: OMAP2+: hwmod: Corrects GPMC HWMOD data

Corrects the GPMC HWMOD data for idle mode usage.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoARM: OMAP2+: gpmc: Adapt to HWMOD
Afzal Mohammed [Fri, 2 Mar 2012 06:07:33 +0000 (11:37 +0530)]
ARM: OMAP2+: gpmc: Adapt to HWMOD

Create API for platforms to adapt gpmc to HWMOD

Signed-off-by: Afzal Mohammed <afzal@ti.com>
9 years agoARM: OMAP2+: gpmc: nand support
Afzal Mohammed [Mon, 27 Feb 2012 13:52:54 +0000 (19:22 +0530)]
ARM: OMAP2+: gpmc: nand support

gpmc driver probe will check the capability of the
devices passed via platform data. Upon finding nand
device, gpmc nand initialization would be done. The
initialization function will internally create
platform device for nand.

Signed-off-by: Afzal Mohammed <afzal@ti.com>
9 years agoARM: OMAP2+: gpmc: initial driver support
Afzal Mohammed [Mon, 27 Feb 2012 13:52:54 +0000 (19:22 +0530)]
ARM: OMAP2+: gpmc: initial driver support

Migrate gpmc code to driver. Initially driver probe
has to initialize device connected to gpmc using
their respective initialization function (based on
the flag passed by platform data). At this stage
platform devices will be created by respective
device initialization function itself.

Later creating platfrom devices would be separated
from device initialization. Once this is done,
driver would be moved to mfd. Then in mfd probe
only device specific initialization would be done,
and would let mfd infrastruture to create platform
devices for the gpmc connected peripherals.

TODO:
1. Is BUG() required to be called on clk_get failure
2. Try not to limit GPMC use cases
3. Revisit GPMC driver conversion patch sequence

Signed-off-by: Afzal Mohammed <afzal@ti.com>
9 years agoARM: OMAP2+: nand: Unify initialization functions
Afzal Mohammed [Wed, 29 Feb 2012 12:41:56 +0000 (18:11 +0530)]
ARM: OMAP2+: nand: Unify initialization functions

Unify the two existing nand initialization functions

This makes gpmc migration to driver easier

From now on, platforms has to call omap_nand_init
to initialize platform nand structures, it's fields.
They have the liberty of directly updating platform
specific nand data also instead of calling it.

Signed-off-by: Afzal Mohammed <afzal@ti.com>
9 years agoARM: OMAP2+: nand: board_nand_init timing arguement
Afzal Mohammed [Wed, 29 Feb 2012 12:41:56 +0000 (18:11 +0530)]
ARM: OMAP2+: nand: board_nand_init timing arguement

Modify board_nand_init to take additional arguement,
timings for gpmc. Also rename the function to
omap_nand_init & let it return pointer to structure
of omap_nand_platform_data.

A prerequisite for combining different board nand
initialization functions.

Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoARM: OMAP2+: nand: Acquire CS in gpmc_nand_init
Afzal Mohammed [Wed, 29 Feb 2012 12:41:56 +0000 (18:11 +0530)]
ARM: OMAP2+: nand: Acquire CS in gpmc_nand_init

Prerequisite to merging different board nand functions to one

Signed-off-by: Afzal Mohammed <afzal@ti.com>
9 years agoARM: OMAP2+: am335x: Removes NAND device registration
Philip, Avinash [Tue, 6 Mar 2012 03:59:05 +0000 (09:29 +0530)]
ARM: OMAP2+: am335x: Removes NAND device registration

Removes NAND device registration to make the way for new NAND device
registration API.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
9 years agoRevert "arm:omap:am335x - Selects HAMMING ECC scheme."
Philip, Avinash [Tue, 6 Mar 2012 03:57:26 +0000 (09:27 +0530)]
Revert "arm:omap:am335x - Selects HAMMING ECC scheme."

This reverts commit 1abf3aa04758ab4b061f7731392f51974c327558.

9 years agoRevert "arm:omap:nand - BCH ecc support added"
Philip, Avinash [Tue, 6 Mar 2012 03:57:09 +0000 (09:27 +0530)]
Revert "arm:omap:nand - BCH ecc support added"

This reverts commit 48a09a90588b40f671447d0e8e782fc01ff7d51c.

9 years agoRevert "arm:omap:nand - Synching HAMMING ECC layout with that of U-boot."
Philip, Avinash [Tue, 6 Mar 2012 03:56:51 +0000 (09:26 +0530)]
Revert "arm:omap:nand - Synching HAMMING ECC layout with that of U-boot."

This reverts commit b60fadc071d76154972513623cf7e784a3af1d00.

9 years agoRevert "arm:omap:nand - Updated JFFS2 clean marker offset."
Philip, Avinash [Tue, 6 Mar 2012 03:56:36 +0000 (09:26 +0530)]
Revert "arm:omap:nand - Updated JFFS2 clean marker offset."

This reverts commit e536110d5dd555a2f67131a16a111505da8280e6.

9 years agoRevert "arm:omap:nand - Fix for NAND module build support"
Philip, Avinash [Tue, 6 Mar 2012 03:56:23 +0000 (09:26 +0530)]
Revert "arm:omap:nand - Fix for NAND module build support"

This reverts commit c2e6066cd2a4b5a584541c2ae16bda779d536e4b.

9 years agoRevert "arch:arm:nand - ELM Module is added"
Philip, Avinash [Tue, 6 Mar 2012 03:55:15 +0000 (09:25 +0530)]
Revert "arch:arm:nand - ELM Module is added"

This reverts commit 9b5f5456fd3b1c2b858e429e5a10fdf01abfabf3.

9 years agoRevert "arm:omap:nand - Enable BCH8 support"
Philip, Avinash [Tue, 6 Mar 2012 03:54:56 +0000 (09:24 +0530)]
Revert "arm:omap:nand - Enable BCH8 support"

This reverts commit f6c154410ab3b0169e92274b9e983091997986ff.

9 years agoRevert "arch:arm:nand - 14 byte ECC support for BCH8"
Philip, Avinash [Tue, 6 Mar 2012 03:54:39 +0000 (09:24 +0530)]
Revert "arch:arm:nand - 14 byte ECC support for BCH8"

This reverts commit 5a03f252fe0052cc5515ab1ba722c21c6f070ac3.

9 years agoRevert "arch:arm:nand - Changing SPL and U-boot partition permission"
Philip, Avinash [Tue, 6 Mar 2012 03:54:24 +0000 (09:24 +0530)]
Revert "arch:arm:nand - Changing SPL and U-boot partition permission"

This reverts commit c5fa750b5c0de616f38719e5c8f8272768a0bff5.

9 years agoRevert "arm:omap:nand - Add support for suspend/resume"
Philip, Avinash [Tue, 6 Mar 2012 03:54:12 +0000 (09:24 +0530)]
Revert "arm:omap:nand - Add support for suspend/resume"

This reverts commit 38f1ae3d786e532574ec3a21e243a72afb54458a.

9 years agoRevert "arm:omap:am33xx - GPMC timings"
Philip, Avinash [Tue, 6 Mar 2012 03:53:57 +0000 (09:23 +0530)]
Revert "arm:omap:am33xx - GPMC timings"

This reverts commit 9c1c234986af93c8478bfcbde64ee61250b9c322.

9 years agoI2C: OMAP: correct SYSC register offset for OMAP4
Alexander Aring [Thu, 8 Dec 2011 14:43:53 +0000 (15:43 +0100)]
I2C: OMAP: correct SYSC register offset for OMAP4

Correct OMAP_I2C_SYSC_REG offset in omap4 register map.
Offset 0x20 is reserved and OMAP_I2C_SYSC_REG has 0x10 as offset.

Signed-off-by: Alexander Aring <a.aring@phytec.de>
[khilman@ti.com: minor changelog edits]
Cc: stable@vger.kernel.org
Signed-off-by: Kevin Hilman <khilman@ti.com>
9 years agoARM: OMAP: AM33XX: CAN: d_can: Add suspend resume support
AnilKumar Ch [Tue, 6 Mar 2012 15:08:00 +0000 (20:38 +0530)]
ARM: OMAP: AM33XX: CAN: d_can: Add suspend resume support

This patch adds suspend resume support to DCAN module. Adds
one flag for knowing the status of DCAN module, whether it
is opened or not.

TODO: Make dcan driver as single file instead of multiple

Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
9 years agoARM: OMAP: AM33XX: CAN: d_can: fix DCAN raminit issue
AnilKumar Ch [Tue, 6 Mar 2012 13:54:35 +0000 (19:24 +0530)]
ARM: OMAP: AM33XX: CAN: d_can: fix DCAN raminit issue

This patch fixes the DCAN raminit problem

Details:
DCAN RAM initialization is not complete and clock disable
is not working as expected after doing the d_can_open().

Before this patch, implementation is like doing DCAN RAM init
first and then enabling the clocks. This was done this way
because RAM init bits are from the control module register.

Workaround:
DCAN clocks should be enable first and then DCAN ram
initialization

Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
9 years agoARM: OMAP: AM33XX: CAN: d_can: Add pm runtime support
AnilKumar Ch [Tue, 6 Mar 2012 13:51:08 +0000 (19:21 +0530)]
ARM: OMAP: AM33XX: CAN: d_can: Add pm runtime support

This patch adds the pm_runtime support to DCAN driver by
replacing clock APIs with pm_runtime APIs.

This patch also cleans up the driver by removing the un-wanted
platform data/parameters

Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
9 years agoARM: OMAP: AM33XX: CAN: d_can: Platform data clean-up
AnilKumar Ch [Tue, 6 Mar 2012 07:36:59 +0000 (13:06 +0530)]
ARM: OMAP: AM33XX: CAN: d_can: Platform data clean-up

This patch cleans up the d_can driver platform specific initilization
data after adding the am33xx hwmod data. Modifies the d_can clock table
entries, modified data includes dev_id and con_id

Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
9 years agoARM: OMAP: AM33XX: CAN: d_can: Add hwmod data for am33xx device
AnilKumar Ch [Tue, 6 Mar 2012 07:32:19 +0000 (13:02 +0530)]
ARM: OMAP: AM33XX: CAN: d_can: Add hwmod data for am33xx device

This patch adds the hwmod data needed by the driver. By adding
DCAN base addresses, interrupt numbers for two d_can instances.

Signed-off-by: AnilKumar Ch <anilkumar@ti.com>