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raw | patch | inline | side by side (parent: e17791e)
raw | patch | inline | side by side (parent: e17791e)
author | Dave Gerlach <d-gerlach@ti.com> | |
Wed, 7 Jan 2015 15:15:45 +0000 (09:15 -0600) | ||
committer | Franklin S. Cooper Jr <fcooper@ti.com> | |
Fri, 6 Feb 2015 23:51:22 +0000 (17:51 -0600) |
AM437x now supports hardware leveling for DDR3 in the EMIF which uses a
few registers not used in software leveling. These registers were not
present in the suspend and resume EMIF context save code so add them so
they are not lost after a suspend operation.
Also make sure to save and restore the EMIF Class of Service registers
as these can also be configured by u-boot if needed and will be lost
after suspend if not saved.
Tested-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
few registers not used in software leveling. These registers were not
present in the suspend and resume EMIF context save code so add them so
they are not lost after a suspend operation.
Also make sure to save and restore the EMIF Class of Service registers
as these can also be configured by u-boot if needed and will be lost
after suspend if not saved.
Tested-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
arch/arm/mach-omap2/sleep43xx.S | patch | blob | history |
index d7fbbec741e7450681c8cfd64c95266aa68c56c4..6b00982309f038294957a30aa2bab8d5ccee84d3 100644 (file)
str r1, emif_zqcfg_val
ldr r1, [r0, #EMIF_DDR_PHY_CTRL_1]
str r1, emif_ddr_phy_ctlr_1
+ ldr r1, [r0, #EMIF_READ_WRITE_LEVELING_RAMP_CONTROL]
+ str r1, emif_rd_wr_level_ramp_ctrl
+ ldr r1, [r0, #EMIF_READ_WRITE_EXECUTION_THRESHOLD]
+ str r1, emif_rd_wr_exec_thresh
+ ldr r1, [r0, #EMIF_COS_CONFIG]
+ str r1, emif_cos_config
+ ldr r1, [r0, #EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING]
+ str r1, emif_priority_to_cos_mapping
+ ldr r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING]
+ str r1, emif_connect_id_serv_1_map
+ ldr r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING]
+ str r1, emif_connect_id_serv_2_map
ldr r1, [r0, #EMIF_LPDDR2_NVM_TIMING]
str r1, emif_lpddr2_nvm_tim
ldr r1, [r0, #EMIF_LPDDR2_NVM_TIMING_SHDW]
ldr r1, emif_ddr_phy_ctlr_1
str r1, [r0, #EMIF_DDR_PHY_CTRL_1]
str r1, [r0, #EMIF_DDR_PHY_CTRL_1_SHDW]
+ ldr r1, emif_rd_wr_level_ramp_ctrl
+ str r1, [r0, #EMIF_READ_WRITE_LEVELING_RAMP_CONTROL]
+ ldr r1, emif_rd_wr_exec_thresh
+ str r1, [r0, #EMIF_READ_WRITE_EXECUTION_THRESHOLD]
+ ldr r1, emif_cos_config
+ str r1, [r0, #EMIF_COS_CONFIG]
+ ldr r1, emif_priority_to_cos_mapping
+ str r1, [r0, #EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING]
+ ldr r1, emif_connect_id_serv_1_map
+ str r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING]
+ ldr r1, emif_connect_id_serv_2_map
+ str r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING]
ldr r1, emif_pmcr_val
str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
ldr r1, emif_pmcr_shdw_val
.word 0xDEADBEEF
emif_rd_lat_val:
.word 0xDEADBEEF
+emif_rd_wr_level_ramp_ctrl:
+ .word 0xDEADBEEF
+emif_rd_wr_exec_thresh:
+ .word 0xDEADBEEF
+emif_cos_config:
+ .word 0xDEADBEEF
+emif_priority_to_cos_mapping:
+ .word 0xDEADBEEF
+emif_connect_id_serv_1_map:
+ .word 0xDEADBEEF
+emif_connect_id_serv_2_map:
+ .word 0xDEADBEEF
emif_ref_ctrl_val:
.word 0xDEADBEEF
emif_ref_ctrl_val_shdw: