arm: dts: dra7: Add syscon for smasw in VIP nodes

When using falling edge pixel clock with VIP, pclk needs to be inverted
inside SoC before it is given to the VIP block.

This is achieved by setting control module register "CTRL_CORE_SMA_SW1"
Add a syscon property for each VIP node to allow this to be set by the
driver.

Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Signed-off-by: Jyri Sarha <jsarha@ti.com>

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 99aba5bfe34822508e8a1b9b2fa1182942a8efe0..f066adf0434625e9e1a07acb0e62b740355f9bb3 100644 (file)
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1844,6 +1844,7 @@
                         ti,hwmods = "vip1";
                        interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
+                       syscon = <&dra7_ctrl_core>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                        status = "disabled";
@@ -1867,6 +1868,7 @@
                         ti,hwmods = "vip2";
                        interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
+                       syscon = <&dra7_ctrl_core>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                        status = "disabled";
@@ -1890,6 +1892,7 @@
                         ti,hwmods = "vip3";
                        interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
+                       syscon = <&dra7_ctrl_core>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                        status = "disabled";