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raw | patch | inline | side by side (parent: 43fca73)
raw | patch | inline | side by side (parent: 43fca73)
author | Vihang Parmar <a0226118@ti.com> | |
Tue, 27 Aug 2019 18:32:57 +0000 (13:32 -0500) | ||
committer | Vihang Parmar <a0226118@ti.com> | |
Tue, 27 Aug 2019 18:32:57 +0000 (13:32 -0500) |
Updated WL8 service pack to v4.4
Updated CC256xC service pack to v1.2
Updated CC256xB service pack to v1.8
Updated CC256xC service pack to v1.2
Updated CC256xB service pack to v1.8
index 0550c1d84dcdcd6f47514ffe9b44f706b3ee4516..8da4580bd622f1b90dc2edd4879322bf99675440 100644 (file)
--- a/ili/TIInit_12.10.28.ili
+++ b/ili/TIInit_12.10.28.ili
Version=1\r
\r
[FileID]\r
+-110=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\sbc\sbc.c\r
+-109=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_06.c\r
+-108=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\afh.c\r
+-107=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Utils\Utils.h\r
+-106=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\peripherals\avpr_dma.c\r
+-105=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\main\phy_fw_main.c\r
+-104=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_utils.c\r
+-103=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+-102=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcf_technology.c\r
+-101=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_trx.c\r
+-100=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Mailbox\osa_mailbox.c\r
+-99=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\patches_shared\Diamond_TI_Q1.h\r
+-98=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
+-97=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_script_timing_calibration.c\r
+-96=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_04.c\r
+-95=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\calibration_stop.c\r
+-94=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
+-93=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_stop.c\r
+-92=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+-91=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_sleep.c\r
+-90=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\filters\avpr_plc.c\r
+-89=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_generate_random_number_calibration.c\r
+-88=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_14.c\r
+-87=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\wb_report_filter.c\r
+-86=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\IPC\osa_ipc_mailbox.c\r
+-85=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
+-84=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Utils\TraceMsg.h\r
+-83=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\rate_convertor\avpr_8_16_convertor.c\r
+-82=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\util\avpr_utils.h\r
+-81=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_clock_dependent_calc.c\r
+-80=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_02.c\r
+-79=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_13.c\r
+-78=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\power_save.c\r
+-77=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_protocol_utils.c\r
+-76=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+-75=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\ble_upper_mac_interface.c\r
+-74=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_DRPB.c\r
+-73=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_BER_Meter.c\r
+-72=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
+-71=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_main.c\r
+-70=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_01.c\r
+-69=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_12.c\r
+-68=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\lps.c\r
+-67=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Include\SleepModes.h\r
+-66=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
+-65=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+-64=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_hooks.c\r
+-63=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_ifa_pole_calibration.c\r
+-62=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_11.c\r
+-61=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
+-60=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\peripherals\avpr_pcmi_drv.c\r
+-59=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations_FPGA\drpb_coarse_open_loop_calibration.c\r
+-58=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_dco_oslo_tank_tune_calibration.c\r
+-57=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_10.c\r
+-56=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
+-55=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_BT.c\r
+-54=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\patches_shared\patches_shared_rom.c\r
+-53=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_config.c\r
+-52=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\six_wires_deep_sleep.c\r
+-51=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+-50=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\fm\avpr_fm.c\r
+-49=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_dc_calibration.c\r
+-48=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\include\phy_utils.h\r
+-47=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+-46=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\utils\rf_sub_functions.c\r
+-45=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\diamond_post_patch.c\r
+-44=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\util\avpr_utils.c\r
+-43=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_temperature_change.c\r
+-42=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\tx_start.c\r
+-41=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\tx_stop.c\r
+-40=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\ANT\upper_mac\ant_upper_mac_sm.c\r
+-39=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
+-38=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+-37=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+-36=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_ldo_calibration.c\r
+-35=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_TOP.c\r
+-34=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\cvsd\avpr_cvsd.c\r
+-33=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
+-32=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations_FPGA\drpb_kdco_calibration.c\r
+-31=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_activity_core.c\r
+-30=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+-29=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\NFC_CLFdefs.h\r
+-28=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\control_path\avpr_upper_mac_interface.c\r
+-27=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations_FPGA\drpb_init.c\r
+-26=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\utils\phy_utils.c\r
+-25=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\ANT\upper_mac\ant_sleep.c\r
+-24=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_patches_ram.c\r
+-23=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
+-22=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_09.c\r
+-21=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\ANT\upper_mac\ant_connection.c\r
+-20=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+-19=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RecoveryPage.c\r
+-18=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\basic_services\top_general_2.c\r
+-17=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+-16=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_PD_extract_calibration.c\r
+-15=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_08.c\r
+-14=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\ANT\upper_mac\ant_search.c\r
+-13=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\nike_plus_activity.c\r
+-12=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+-11=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
+-10=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+-9=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Nike_plus\nike_plus_um_data_path.c\r
+-8=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Interrupts\osa_int_manager.c\r
+-7=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\timer_handler.c\r
+-6=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\basic_services\top_general_1.c\r
+-5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_07.c\r
+-4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\calibration_start.c\r
+-3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+-2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\NFC_PHYdefs.h\r
+-1=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
+1=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
+2=Palau_deep_sleep.c\r
+3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
+4=int.c\r
+5=inthndlr.c\r
+6=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Utils\Trace.c\r
+7=osa_buf_task.c\r
+8=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Buffers\osa_buf.c\r
+10=intcntrl.c\r
+11=app.c\r
+12=HCI_Transport.c\r
+14=armio.c\r
+15=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\DMA\Dma.c\r
+16=sdio.c\r
+17=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\Uart_Hci.c\r
+18=Uart_DEBUG.c\r
+19=Avpr_trace.c\r
+25=rxstop.c\r
+26=correl.c\r
+27=schedule.c\r
+29=fh.c\r
+30=BTClk.c\r
+32=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+33=Int_Drv.c\r
+34=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\drpb.c\r
+35=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
+36=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
+37=dbg.c\r
+38=Drp.c\r
+39=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Init.c\r
+40=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
+41=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LSTO.c\r
+42=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Page.c\r
+43=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
+44=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Utils.c\r
+45=BasebandScripts.c\r
+46=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Main.c\r
+47=Data_LMP.c\r
+48=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Windy.c\r
+49=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
+50=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
+51=timers_op.c\r
+52=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
+53=acl_clk_offset.c\r
+54=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_connection.c\r
+55=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_detach.c\r
+56=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_encrypt.c\r
+57=acl_features.c\r
+58=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_hold.c\r
+59=acl_key_exchange.c\r
+60=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_name.c\r
+61=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_pairing.c\r
+62=acl_pkt_types.c\r
+63=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff_Subrate.c\r
+64=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_switch.c\r
+65=acl_version.c\r
+66=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+67=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_test.c\r
+68=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
+69=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+70=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvhci.c\r
+71=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
+72=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+73=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmlc.c\r
+74=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicrcv.c\r
+75=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicsnd.c\r
+76=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcievts.c\r
+77=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
+78=e_func.c\r
+79=acl_paging.c\r
+80=acl_link_super.c\r
+81=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+82=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff.c\r
+83=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_cqddr.c\r
+84=acl_sniff_sbr.c\r
+85=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
+86=acl_park.c\r
+87=Abort.c\r
+88=RfInterface.c\r
+89=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\Cdc.c\r
+90=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Inquiry.c\r
+91=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_InquiryScan.c\r
+92=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Hold.c\r
+93=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
+94=Timers.c\r
+95=HCIPPcmd_part_1.c\r
+96=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPevt.c\r
+97=gou.c\r
+98=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\system_init.c\r
+99=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
+100=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
+101=PatchTrap.c\r
+102=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\RF_Tester.c\r
+103=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
+104=composer.c\r
+105=lsl.c\r
+106=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_qos.c\r
+107=acl_power_ctrl.c\r
+108=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
+109=acl_timing.c\r
+110=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_MS_Switch.c\r
+111=lci.c\r
+112=txacl.c\r
+113=rxacl.c\r
+114=parser.c\r
+115=encryp.c\r
+116=logger.c\r
+117=LC_Park.c\r
+118=app.c\r
+119=reg_bits_util.c\r
+120=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Buffers\osa_buf_debug.c\r
+121=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_hcicmd.c\r
+122=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_hcievt.c\r
+123=LC_LPS.c\r
+124=LC_Broadcast.c\r
+125=hci_api.c\r
+126=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SelfTest.c\r
+127=i2c_driver.c\r
+128=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
+129=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_manager.c\r
+130=IntManager.c\r
+131=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+132=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_afh.c\r
+133=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Afh.c\r
+134=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Classification.c\r
+135=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Piconizer.c\r
+136=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_tester.c\r
+137=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
+138=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ErrorStatistics.c\r
+139=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
+141=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+142=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_qos.c\r
+143=STM_Engine.c\r
+144=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Gemini.c\r
+145=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
+146=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIT\HCI_SCO_Transport.c\r
+147=Lc_Sniff_Subrate.c\r
+148=random.c\r
+149=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\protocol_utils.c\r
+150=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+151=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
+152=HCIPPcmd_part_2.c\r
+153=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\HostInterface.c\r
+154=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\spi\spi.c\r
+155=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\UART_Protocol_detection\UART_Protocol_detection.c\r
+156=acl_ptt.c\r
+157=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
+158=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\transport_detection\Transport_Detection.c\r
+159=HCIPPcmd_part_3.c\r
+160=hifcrcv.c\r
+161=hifcsnd.c\r
+162=hifd.c\r
+163=lmrcvhif.c\r
+164=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_advertise.c\r
+165=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\um2lm.c\r
+166=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lm2um.c\r
+167=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_main.c\r
+168=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+169=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connect.c\r
+170=main.c\r
+171=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
+172=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_scan.c\r
+173=lower mac advertise.c\r
+174=top mailbox.c\r
+175=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_activity.c\r
+176=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lower_mac_interface.c\r
+177=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\gps_shared_interface.c\r
+178=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection_manager.c\r
+179=gps_shared_interface.c\r
+180=arm7_a3dp.c\r
+181=connection_activity.c\r
+182=ipc_mailbox.c\r
+184=cross_platform_init_code.c\r
+185=pll_sharing.c\r
+186=top_config.c\r
+187=top_config_cross_platform.c\r
+188=top_prcm_cross_platform.c\r
+189=top_config_hcippcmd.c\r
+190=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\mailbox\internal\top_mailbox.c\r
+191=top.c\r
+192=LC_Recovery_Page.c\r
+193=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lm_auto_recovery.c\r
+194=LC_Recovery_PageScan.c\r
+195=ipc_queue.c\r
+196=avpr_lower_mac_interface.c\r
+197=top_interrupts.c\r
+198=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\basic_services\internal\top_semaphores.c\r
+199=top_pinmux.c\r
+200=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\fm_shared_interface.c\r
+220=nfc_activity.c\r
+221=HCIPPcmd_2.c\r
+222=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\Gemini_wlan_coex.c\r
+223=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_greedy_collection.c\r
+224=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_iso18092.c\r
+225=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep.c\r
+226=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
+227=nfc_nfca_technology.c\r
+228=nfc_nfcb_technology.c\r
+229=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
+230=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Collision_Avoidence\nfc_rf_collision_avoidance.c\r
+231=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_settings.c\r
+232=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+233=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+234=nfc_tag1_platform_activity.c\r
+235=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
+236=nfc_RF_FPGA.c\r
+237=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_iso15693_technology.c\r
+238=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_rw.c\r
+239=nfc_iso_dep_activity.c\r
+240=nfc_nfcf_technology.c\r
+241=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep.c\r
+242=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_activation_ce.c\r
+243=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_activation_rw.c\r
+244=nfc_dep_activity.c\r
+245=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+246=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_personality_mgmt.c\r
+247=nfc_wi_technology.c\r
+248=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_ce.c\r
+249=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
+250=nfc_stack_manager.c\r
+251=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_swp_hw.c\r
+252=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_buffer.c\r
+253=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
+254=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_utils.c\r
+255=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
+256=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_interrupt.c\r
+257=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF.c\r
+258=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_main.c\r
+259=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_admin_gate.c\r
+260=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_controller.c\r
+261=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_gate.c\r
+262=nfc_hci_id_management_gate.c\r
+263=nfc_hci_loopback_gate.c\r
+264=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_management_gate.c\r
+265=nfc_hci_pipes.c\r
+266=nfc_hci_reader_gate.c\r
+267=nfc_hci_se_gate.c\r
+268=nfc_hci_clf_control_gate.c\r
+269=nfc_hci_wi_gate.c\r
+270=nfc_hci_emulation_gate.c\r
+271=phy_if.c\r
+272=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
+273=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+274=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
+275=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_send.c\r
+276=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_vs.c\r
+277=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
+278=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+279=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
+280=LLR_General.C\r
+281=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
+282=nfc_rf_statistics.c\r
+283=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
+284=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_listen.c\r
+285=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
+286=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
+287=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_SASE_manager.c\r
+288=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_calibrations.c\r
+289=nfc_RF_NERD.c\r
+290=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_data_exchange_defs.c\r
+291=nfc_hooks.c\r
+292=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
+293=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Nike_plus\nike_plus_scan.c\r
+294=nfc_patches.c\r
\r
[MsgID]\r
1=%d message(s) was(were) dropped (UART Debug was full)\r
1448=LC_PICONIZER - freed network clock %d\r
1450=patch info lsto: handle %d, is_role_master %d, lsto %d, bd 0x%x\r
1451=patch info timing offsets: L %d.%d, N1 %d.%d\r
-1452=patch info LMP: handle %d, opcode %d, ext %d, p_data 0x%x\r
-1453=patch info LMP2: local_trans %d, state %d, peer_trans %d, state %d\r
-1454=patch info AUTH au_rand received: is_new_link_key %d, is_secure_conn %d, authentication_role %d, link_key_present %d\r
1455=patch_acl_perform_authentication patch_trans_id: %d, ROM trans_id: %d\r
-1456=patch info AUTH sres received: is_new_link_key %d, is_secure_conn %d, authentication_role %d, link_key_present %d\r
-1460=host enabled PCM clock exstension\r
1468=hook_internal_set_pcm_clock_mode 0x%x, %d\r
1477=Foundation Version of Patch Package: %d.0.%d\r
1478=Package ID: P%d.%d\r
3040=AVPR Memory Manage Fault Address=0x%.04X%.04X\r
3041=AVPR Cortex Hard Fault Execption: Program Counter=0x%.04X%.04X\r
3042=AVPR hook is working\r
-3043=AVPR New hooks system works (%u)\r
+3043=AVPR New hook system works (%u)\r
3044=AVPR Hooks attach error - NUMBER_OF_USED_HOOKS must be increased\r
3045=AVPR Foundation Version of Patch Package: %d.0.%d\r
3046=AVPR Package ID: P%d.%d\r
@@ -3322,4969 +3691,4977 @@ Version=1
\r
[MsgPos]\r
Line6=300\r
-Path6=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPevt.c\r
+Path6=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPevt.c\r
Line7=428\r
-Path7=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path7=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line8=770\r
-Path8=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path8=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line10=2029\r
-Path10=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path10=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line11=881\r
-Path11=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path11=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line12=1840\r
-Path12=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path12=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line13=1652\r
-Path13=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path13=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line14=999\r
-Path14=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path14=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line15=1010\r
-Path15=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path15=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line16=1021\r
-Path16=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path16=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line17=1032\r
-Path17=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path17=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line18=1060\r
-Path18=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path18=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line20=538\r
-Path20=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path20=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line20.2=580\r
-Path20.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
-Line20.3=1608\r
-Path20.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Path20.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Line20.3=1658\r
+Path20.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
Line21=3714\r
-Path21=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
+Path21=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
Line23=494\r
-Path23=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path23=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line24=530\r
-Path24=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path24=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line25=568\r
-Path25=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path25=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line26=673\r
-Path26=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path26=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line27=2256\r
-Path27=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
+Path27=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
Line28=2186\r
-Path28=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path28=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line28.2=1213\r
-Path28.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
+Path28.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
Line29=1005\r
-Path29=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path29=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line29.2=1016\r
-Path29.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path29.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line29.3=1027\r
-Path29.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path29.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line29.4=1038\r
-Path29.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path29.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line29.5=1217\r
-Path29.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path29.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line30=311\r
-Path30=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path30=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line31=3399\r
-Path31=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path31=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line32=370\r
-Path32=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path32=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line33=493\r
-Path33=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path33=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line34=133\r
-Path34=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Buffers\osa_buf_debug.c\r
+Path34=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Buffers\osa_buf_debug.c\r
Line35=971\r
-Path35=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path35=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line36=1004\r
-Path36=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path36=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line36.2=1015\r
-Path36.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path36.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line36.3=1026\r
-Path36.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path36.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line36.4=1037\r
-Path36.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path36.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line36.5=1216\r
-Path36.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path36.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line41=450\r
-Path41=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path41=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line42=465\r
-Path42=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path42=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line43=365\r
-Path43=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path43=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line72=529\r
-Path72=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvhci.c\r
+Path72=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvhci.c\r
Line74=340\r
-Path74=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmlc.c\r
+Path74=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmlc.c\r
Line75=425\r
-Path75=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
+Path75=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
Line76=853\r
-Path76=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path76=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line77=2661\r
-Path77=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path77=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line78=2693\r
-Path78=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path78=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line80=1972\r
-Path80=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
+Path80=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
Line81=163\r
-Path81=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_hcicmd.c\r
+Path81=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_hcicmd.c\r
Line82=335\r
-Path82=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_hcicmd.c\r
+Path82=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_hcicmd.c\r
Line82.2=441\r
-Path82.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_hcicmd.c\r
+Path82.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_hcicmd.c\r
Line83=3451\r
-Path83=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path83=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line84=753\r
-Path84=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
+Path84=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
Line85=2373\r
-Path85=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
+Path85=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
Line86=212\r
-Path86=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmlc.c\r
+Path86=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmlc.c\r
Line87=1254\r
-Path87=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+Path87=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
Line88=353\r
-Path88=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
+Path88=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
Line89=457\r
-Path89=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_qos.c\r
+Path89=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_qos.c\r
Line90=889\r
-Path90=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_qos.c\r
+Path90=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_qos.c\r
Line91=118\r
-Path91=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Piconizer.c\r
+Path91=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Piconizer.c\r
Line92=577\r
-Path92=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_qos.c\r
+Path92=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_qos.c\r
Line93=632\r
-Path93=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path93=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line96=498\r
-Path96=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path96=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line99=827\r
-Path99=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicrcv.c\r
+Path99=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicrcv.c\r
Line100=519\r
-Path100=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
+Path100=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
Line100.2=1378\r
-Path100.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
+Path100.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
Line101=1390\r
-Path101=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
+Path101=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
Line102=1469\r
-Path102=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
+Path102=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
Line103=1491\r
-Path103=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
+Path103=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
Line104=1637\r
-Path104=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
+Path104=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
Line106=434\r
-Path106=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_qos.c\r
+Path106=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_qos.c\r
Line107=431\r
-Path107=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_qos.c\r
+Path107=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_qos.c\r
Line108=393\r
-Path108=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path108=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line109=394\r
-Path109=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path109=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line110=552\r
-Path110=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path110=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line112=3410\r
-Path112=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path112=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line113=937\r
-Path113=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_qos.c\r
+Path113=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_qos.c\r
Line114=1240\r
-Path114=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_qos.c\r
+Path114=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_qos.c\r
Line115=2338\r
-Path115=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path115=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line116=320\r
-Path116=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
+Path116=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
Line126=596\r
-Path126=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Buffers\osa_buf.c\r
+Path126=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Buffers\osa_buf.c\r
Line127=392\r
-Path127=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
+Path127=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
Line131=763\r
-Path131=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path131=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line138=304\r
-Path138=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\um2lm.c\r
+Path138=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\um2lm.c\r
Line140=855\r
-Path140=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Page.c\r
+Path140=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Page.c\r
Line141=245\r
-Path141=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RecoveryPage.c\r
+Path141=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RecoveryPage.c\r
Line166=1034\r
-Path166=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path166=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line181=1100\r
-Path181=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Init.c\r
+Path181=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Init.c\r
Line182=1064\r
-Path182=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Init.c\r
+Path182=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Init.c\r
Line189=1046\r
-Path189=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Init.c\r
+Path189=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Init.c\r
Line190=1055\r
-Path190=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Init.c\r
-Line191=854\r
-Path191=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line191.2=509\r
-Path191.2=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
-Line193=853\r
-Path193=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line193.2=508\r
-Path193.2=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Path190=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Init.c\r
+Line191=509\r
+Path191=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line191.2=854\r
+Path191.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
+Line193=508\r
+Path193=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line193.2=853\r
+Path193.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
Line240=452\r
-Path240=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
+Path240=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
Line241=290\r
-Path241=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path241=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line242=267\r
-Path242=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path242=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line243=226\r
-Path243=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path243=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line244=165\r
-Path244=M:\Omri_WPAN_45nm_FW_4_SP\ti\patches_shared\patches_shared_rom.c\r
+Path244=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\patches_shared\patches_shared_rom.c\r
Line245=220\r
-Path245=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path245=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line247=230\r
-Path247=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path247=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line248=235\r
-Path248=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path248=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line249=298\r
-Path249=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path249=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line250=751\r
-Path250=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicrcv.c\r
+Path250=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicrcv.c\r
Line252=222\r
-Path252=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path252=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line253=218\r
-Path253=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path253=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line254=242\r
-Path254=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path254=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line255=247\r
-Path255=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path255=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line256=387\r
-Path256=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Gemini.c\r
+Path256=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Gemini.c\r
Line257=709\r
-Path257=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_hcievt.c\r
+Path257=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_hcievt.c\r
Line258=973\r
-Path258=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
+Path258=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
Line259=799\r
-Path259=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_hcievt.c\r
+Path259=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_hcievt.c\r
Line261=198\r
-Path261=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\Cdc.c\r
+Path261=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\Cdc.c\r
Line263=230\r
-Path263=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\Cdc.c\r
+Path263=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\Cdc.c\r
Line264=242\r
-Path264=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\Cdc.c\r
+Path264=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\Cdc.c\r
Line268=437\r
-Path268=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\Cdc.c\r
+Path268=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\Cdc.c\r
Line271=1837\r
-Path271=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+Path271=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
Line275=972\r
-Path275=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
+Path275=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
Line276=984\r
-Path276=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
+Path276=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
Line277=1017\r
-Path277=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
+Path277=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
Line278=1035\r
-Path278=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
+Path278=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
Line280=1042\r
-Path280=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
+Path280=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
Line283=139\r
-Path283=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_manager.c\r
+Path283=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_manager.c\r
Line288=2615\r
-Path288=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
+Path288=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
Line291=856\r
-Path291=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
-Line292=859\r
-Path292=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line292.2=514\r
-Path292.2=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Path291=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
+Line292=514\r
+Path292=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line292.2=859\r
+Path292.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
Line297=466\r
-Path297=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
+Path297=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
Line299=2112\r
-Path299=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
+Path299=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
Line300=345\r
-Path300=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SelfTest.c\r
+Path300=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SelfTest.c\r
Line304=364\r
-Path304=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Afh.c\r
+Path304=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Afh.c\r
Line309=471\r
-Path309=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Afh.c\r
+Path309=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Afh.c\r
Line310=493\r
-Path310=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Afh.c\r
+Path310=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Afh.c\r
Line311=610\r
-Path311=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Afh.c\r
+Path311=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Afh.c\r
Line312=629\r
-Path312=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Afh.c\r
+Path312=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Afh.c\r
Line313=1449\r
-Path313=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path313=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line317=1597\r
-Path317=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
+Path317=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
Line320=282\r
-Path320=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Hold.c\r
+Path320=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Hold.c\r
Line321=471\r
-Path321=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Hold.c\r
+Path321=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Hold.c\r
Line322=330\r
-Path322=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LSTO.c\r
+Path322=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LSTO.c\r
Line324=358\r
-Path324=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LSTO.c\r
+Path324=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LSTO.c\r
Line325=389\r
-Path325=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LSTO.c\r
+Path325=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LSTO.c\r
Line332=900\r
-Path332=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\protocol_utils.c\r
+Path332=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\protocol_utils.c\r
Line333=707\r
-Path333=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_utils.c\r
-Line335=1425\r
-Path335=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line335.2=1029\r
-Path335.2=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Path333=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_utils.c\r
+Line335=1029\r
+Path335=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line335.2=1425\r
+Path335.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
Line339=95\r
-Path339=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\fm_shared_interface.c\r
+Path339=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\fm_shared_interface.c\r
Line341=1882\r
-Path341=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
+Path341=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
Line342=132\r
-Path342=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\fm_shared_interface.c\r
+Path342=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\fm_shared_interface.c\r
Line350=240\r
-Path350=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\fm_shared_interface.c\r
+Path350=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\fm_shared_interface.c\r
Line351=219\r
-Path351=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\fm_shared_interface.c\r
+Path351=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\fm_shared_interface.c\r
Line352=229\r
-Path352=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\fm_shared_interface.c\r
+Path352=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\fm_shared_interface.c\r
Line353=233\r
-Path353=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\fm_shared_interface.c\r
+Path353=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\fm_shared_interface.c\r
Line354=95\r
-Path354=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Piconizer.c\r
+Path354=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Piconizer.c\r
Line355=398\r
-Path355=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
+Path355=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
Line356=414\r
-Path356=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
+Path356=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
Line366=724\r
-Path366=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
+Path366=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
Line367=784\r
-Path367=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
+Path367=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
Line368=321\r
-Path368=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SelfTest.c\r
-Line374=855\r
-Path374=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line374.2=510\r
-Path374.2=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Path368=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SelfTest.c\r
+Line374=510\r
+Path374=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line374.2=855\r
+Path374.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
Line378=105\r
-Path378=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Hold.c\r
+Path378=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Hold.c\r
Line379=322\r
-Path379=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Hold.c\r
+Path379=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Hold.c\r
Line380=404\r
-Path380=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Hold.c\r
+Path380=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Hold.c\r
Line382=317\r
-Path382=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
+Path382=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
Line383=1037\r
-Path383=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
+Path383=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
Line385=191\r
-Path385=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
+Path385=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
Line391=908\r
-Path391=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
+Path391=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
Line392=912\r
-Path392=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
+Path392=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
Line393=1925\r
-Path393=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
+Path393=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
Line393.2=447\r
-Path393.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_test.c\r
+Path393.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_test.c\r
Line394=512\r
-Path394=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Utils.c\r
+Path394=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Utils.c\r
Line395=3137\r
-Path395=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path395=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line396=1492\r
-Path396=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_afh.c\r
+Path396=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_afh.c\r
Line397=1545\r
-Path397=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_afh.c\r
+Path397=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_afh.c\r
Line398=311\r
-Path398=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
+Path398=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
Line398.2=648\r
-Path398.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
-Line406=1369\r
-Path406=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line406.2=976\r
-Path406.2=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Path398.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
+Line406=976\r
+Path406=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line406.2=1369\r
+Path406.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
Line407=1861\r
-Path407=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+Path407=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
Line408=1524\r
-Path408=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+Path408=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
Line409=244\r
-Path409=M:\Omri_WPAN_45nm_FW_4_SP\ti\Include\SleepModes.h\r
+Path409=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Include\SleepModes.h\r
Line411=114\r
-Path411=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
+Path411=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
Line412=150\r
-Path412=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
+Path412=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
Line414=961\r
-Path414=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
+Path414=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
Line415=57\r
-Path415=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_manager.c\r
+Path415=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_manager.c\r
Line416=166\r
-Path416=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_manager.c\r
+Path416=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_manager.c\r
Line417=350\r
-Path417=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\six_wires_deep_sleep.c\r
+Path417=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\six_wires_deep_sleep.c\r
Line419=1383\r
-Path419=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
-Line421=862\r
-Path421=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line421.2=517\r
-Path421.2=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Path419=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+Line421=517\r
+Path421=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line421.2=862\r
+Path421.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
Line422=114\r
-Path422=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Piconizer.c\r
+Path422=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Piconizer.c\r
Line423=90\r
-Path423=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Piconizer.c\r
+Path423=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Piconizer.c\r
Line424=139\r
-Path424=M:\Omri_WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
+Path424=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
Line426=3552\r
-Path426=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
+Path426=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
Line427=1032\r
-Path427=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
+Path427=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
Line429=328\r
-Path429=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_BER_Meter.c\r
+Path429=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_BER_Meter.c\r
Line430=1999\r
-Path430=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
+Path430=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
Line431=1057\r
-Path431=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
+Path431=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
Line432=899\r
-Path432=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
+Path432=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
Line433=389\r
-Path433=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\HostInterface.c\r
+Path433=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\HostInterface.c\r
Line434=903\r
-Path434=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
+Path434=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
Line435=676\r
-Path435=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
+Path435=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
Line436=677\r
-Path436=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
+Path436=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
Line437=678\r
-Path437=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
+Path437=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
Line438=233\r
-Path438=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
+Path438=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
Line439=234\r
-Path439=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
+Path439=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
Line440=235\r
-Path440=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
+Path440=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
Line441=1295\r
-Path441=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\protocol_utils.c\r
+Path441=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\protocol_utils.c\r
Line443=543\r
-Path443=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Interrupts\osa_int_manager.c\r
+Path443=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Interrupts\osa_int_manager.c\r
Line444=967\r
-Path444=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+Path444=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
Line446=275\r
-Path446=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\HostInterface.c\r
+Path446=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\HostInterface.c\r
Line446.2=282\r
-Path446.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\HostInterface.c\r
+Path446.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\HostInterface.c\r
Line447=236\r
-Path447=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff_Subrate.c\r
-Line454=852\r
-Path454=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line454.2=507\r
-Path454.2=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Path447=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff_Subrate.c\r
+Line454=507\r
+Path454=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line454.2=852\r
+Path454.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
Line456=169\r
-Path456=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\Cdc.c\r
-Line457=884\r
-Path457=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line457.2=539\r
-Path457.2=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
-Line461=889\r
-Path461=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line461.2=544\r
-Path461.2=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Path456=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\Cdc.c\r
+Line457=539\r
+Path457=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line457.2=884\r
+Path457.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
+Line461=544\r
+Path461=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line461.2=889\r
+Path461.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
Line463=468\r
-Path463=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_InquiryScan.c\r
+Path463=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_InquiryScan.c\r
Line464=116\r
-Path464=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LSTO.c\r
+Path464=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LSTO.c\r
Line467=484\r
-Path467=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LSTO.c\r
+Path467=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LSTO.c\r
Line468=1002\r
-Path468=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_MS_Switch.c\r
+Path468=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_MS_Switch.c\r
Line469=1133\r
-Path469=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_MS_Switch.c\r
+Path469=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_MS_Switch.c\r
Line470=1175\r
-Path470=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_MS_Switch.c\r
+Path470=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_MS_Switch.c\r
Line471=1262\r
-Path471=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_MS_Switch.c\r
+Path471=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_MS_Switch.c\r
Line472=1294\r
-Path472=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_MS_Switch.c\r
+Path472=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_MS_Switch.c\r
Line473=440\r
-Path473=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
+Path473=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
Line474=796\r
-Path474=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
+Path474=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
Line475=890\r
-Path475=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
-Line476=864\r
-Path476=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line476.2=519\r
-Path476.2=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Path475=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
+Line476=519\r
+Path476=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line476.2=864\r
+Path476.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
Line478=1261\r
-Path478=M:\Omri_WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
+Path478=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
Line479=580\r
-Path479=M:\Omri_WPAN_45nm_FW_4_SP\ti\Utils\Utils.h\r
+Path479=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Utils\Utils.h\r
Line481=748\r
-Path481=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
+Path481=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
Line482=824\r
-Path482=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
+Path482=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
Line485=371\r
-Path485=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
+Path485=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
Line486=391\r
-Path486=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
+Path486=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
Line487=1115\r
-Path487=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
+Path487=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
Line488=156\r
-Path488=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SelfTest.c\r
+Path488=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SelfTest.c\r
Line491=164\r
-Path491=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SelfTest.c\r
+Path491=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SelfTest.c\r
Line493=1168\r
-Path493=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
+Path493=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
Line493.2=446\r
-Path493.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_test.c\r
+Path493.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_test.c\r
Line494=518\r
-Path494=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Utils.c\r
+Path494=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Utils.c\r
Line495=288\r
-Path495=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Windy.c\r
+Path495=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Windy.c\r
Line497=2726\r
-Path497=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvhci.c\r
+Path497=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvhci.c\r
Line498=3144\r
-Path498=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path498=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line499=3157\r
-Path499=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path499=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line500=165\r
-Path500=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_afh.c\r
+Path500=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_afh.c\r
Line501=1316\r
-Path501=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_afh.c\r
+Path501=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_afh.c\r
Line502=3987\r
-Path502=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path502=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line504=691\r
-Path504=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
-Line505=883\r
-Path505=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line505.2=538\r
-Path505.2=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
-Line506=874\r
-Path506=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line506.2=529\r
-Path506.2=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
-Line507=882\r
-Path507=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line507.2=537\r
-Path507.2=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
-Line508=872\r
-Path508=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line508.2=879\r
-Path508.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line508.3=527\r
-Path508.3=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
-Line508.4=534\r
-Path508.4=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
-Line509=873\r
-Path509=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line509.2=528\r
-Path509.2=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Path504=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
+Line505=538\r
+Path505=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line505.2=883\r
+Path505.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
+Line506=529\r
+Path506=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line506.2=874\r
+Path506.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
+Line507=537\r
+Path507=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line507.2=882\r
+Path507.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
+Line508=527\r
+Path508=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line508.2=534\r
+Path508.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line508.3=872\r
+Path508.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
+Line508.4=879\r
+Path508.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
+Line509=528\r
+Path509=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line509.2=873\r
+Path509.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
Line510=503\r
-Path510=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+Path510=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
Line512=1879\r
-Path512=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+Path512=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
Line513=1272\r
-Path513=M:\Omri_WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
+Path513=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
Line514=581\r
-Path514=M:\Omri_WPAN_45nm_FW_4_SP\ti\Utils\Utils.h\r
+Path514=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Utils\Utils.h\r
Line514.2=584\r
-Path514.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\Utils\Utils.h\r
+Path514.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Utils\Utils.h\r
Line515=2434\r
-Path515=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\system_init.c\r
+Path515=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\system_init.c\r
Line516=338\r
-Path516=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Afh.c\r
+Path516=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Afh.c\r
Line517=1354\r
-Path517=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
+Path517=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
Line518=1464\r
-Path518=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
+Path518=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
Line519=197\r
-Path519=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Hold.c\r
+Path519=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Hold.c\r
Line520=520\r
-Path520=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
+Path520=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
Line520.2=528\r
-Path520.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
+Path520.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
Line521=1119\r
-Path521=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Inquiry.c\r
+Path521=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Inquiry.c\r
Line522=669\r
-Path522=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_MS_Switch.c\r
+Path522=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_MS_Switch.c\r
Line523=934\r
-Path523=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_MS_Switch.c\r
+Path523=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_MS_Switch.c\r
Line524=961\r
-Path524=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_MS_Switch.c\r
+Path524=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_MS_Switch.c\r
Line525=111\r
-Path525=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_manager.c\r
+Path525=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_manager.c\r
Line526=986\r
-Path526=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_MS_Switch.c\r
+Path526=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_MS_Switch.c\r
Line527=1001\r
-Path527=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RecoveryPage.c\r
-Line528=1348\r
-Path528=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line528.2=1360\r
-Path528.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line528.3=955\r
-Path528.3=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
-Line528.4=967\r
-Path528.4=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
-Line529=878\r
-Path529=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line529.2=533\r
-Path529.2=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
-Line530=894\r
-Path530=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line530.2=549\r
-Path530.2=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Path527=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RecoveryPage.c\r
+Line528=955\r
+Path528=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line528.2=967\r
+Path528.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line528.3=1348\r
+Path528.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
+Line528.4=1360\r
+Path528.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
+Line529=533\r
+Path529=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line529.2=878\r
+Path529.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
+Line530=549\r
+Path530=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line530.2=894\r
+Path530.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
Line531=2924\r
-Path531=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
+Path531=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
Line535=375\r
-Path535=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
+Path535=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
Line536=395\r
-Path536=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
+Path536=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
Line537=416\r
-Path537=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
+Path537=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
Line538=389\r
-Path538=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
+Path538=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
Line539=418\r
-Path539=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
+Path539=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
Line540=423\r
-Path540=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
+Path540=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
Line541=425\r
-Path541=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
+Path541=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
Line545=448\r
-Path545=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
+Path545=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
Line546=432\r
-Path546=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
+Path546=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
Line548=2677\r
-Path548=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
+Path548=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
Line550=2965\r
-Path550=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
+Path550=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
Line551=3377\r
-Path551=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
+Path551=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
Line552=1991\r
-Path552=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
+Path552=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
Line552.2=448\r
-Path552.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_test.c\r
+Path552.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_test.c\r
Line553=1992\r
-Path553=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
+Path553=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
Line553.2=449\r
-Path553.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_test.c\r
+Path553.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_test.c\r
Line554=1993\r
-Path554=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
+Path554=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
Line554.2=450\r
-Path554.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_test.c\r
+Path554.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_test.c\r
Line555=1994\r
-Path555=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
+Path555=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
Line555.2=451\r
-Path555.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_test.c\r
+Path555.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_test.c\r
Line557=518\r
-Path557=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff.c\r
+Path557=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff.c\r
Line559=162\r
-Path559=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
+Path559=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
Line567=148\r
-Path567=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
+Path567=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
Line569=594\r
-Path569=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Afh.c\r
+Path569=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Afh.c\r
Line572=601\r
-Path572=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
+Path572=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
Line572.2=640\r
-Path572.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
+Path572.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
Line575=1038\r
-Path575=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
+Path575=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
Line576=1176\r
-Path576=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
+Path576=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
Line576.2=1199\r
-Path576.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
+Path576.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
Line576.3=1225\r
-Path576.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
+Path576.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
Line577=1756\r
-Path577=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
+Path577=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
Line578=1887\r
-Path578=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
+Path578=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
Line587=363\r
-Path587=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff_Subrate.c\r
+Path587=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff_Subrate.c\r
Line589=739\r
-Path589=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Inquiry.c\r
+Path589=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Inquiry.c\r
Line590=244\r
-Path590=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_InquiryScan.c\r
+Path590=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_InquiryScan.c\r
Line593=420\r
-Path593=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
+Path593=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
Line594=233\r
-Path594=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_InquiryScan.c\r
+Path594=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_InquiryScan.c\r
Line594.2=236\r
-Path594.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
+Path594.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
Line600=1567\r
-Path600=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
+Path600=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
Line602=497\r
-Path602=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Inquiry.c\r
+Path602=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Inquiry.c\r
Line614=378\r
-Path614=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIT\HCI_SCO_Transport.c\r
+Path614=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIT\HCI_SCO_Transport.c\r
Line634=452\r
-Path634=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_BER_Meter.c\r
+Path634=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_BER_Meter.c\r
Line635=456\r
-Path635=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_BER_Meter.c\r
+Path635=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_BER_Meter.c\r
Line636=460\r
-Path636=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_BER_Meter.c\r
+Path636=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_BER_Meter.c\r
Line639=1291\r
-Path639=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
+Path639=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
Line642=1965\r
-Path642=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+Path642=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
Line645=1235\r
-Path645=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
+Path645=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
Line647=3799\r
-Path647=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
+Path647=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
Line650=1237\r
-Path650=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
+Path650=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
Line653=259\r
-Path653=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ErrorStatistics.c\r
+Path653=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ErrorStatistics.c\r
Line654=987\r
-Path654=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
+Path654=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
Line655=1007\r
-Path655=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
+Path655=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_SCO_Data.c\r
Line656=2428\r
-Path656=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
+Path656=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
Line659=3138\r
-Path659=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path659=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line660=1125\r
-Path660=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
+Path660=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
Line661=1043\r
-Path661=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+Path661=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
Line662=1529\r
-Path662=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
+Path662=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
Line663=1143\r
-Path663=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Init.c\r
+Path663=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Init.c\r
Line665=1183\r
-Path665=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
+Path665=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
Line667=1189\r
-Path667=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
+Path667=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
Line670=515\r
-Path670=M:\Omri_WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
+Path670=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
Line673=1174\r
-Path673=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
+Path673=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
Line676=797\r
-Path676=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\mailbox\internal\top_mailbox.c\r
+Path676=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\mailbox\internal\top_mailbox.c\r
Line677=992\r
-Path677=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
+Path677=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
Line677.2=999\r
-Path677.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
+Path677.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
Line677.3=1000\r
-Path677.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
+Path677.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
Line677.4=1001\r
-Path677.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
+Path677.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
Line679=4204\r
-Path679=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
+Path679=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
Line681=398\r
-Path681=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Classification.c\r
+Path681=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Classification.c\r
Line681.2=421\r
-Path681.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Classification.c\r
+Path681.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Classification.c\r
Line682=275\r
-Path682=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
+Path682=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
Line683=939\r
-Path683=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path683=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line684=3922\r
-Path684=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
+Path684=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
Line684.2=3928\r
-Path684.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
+Path684.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
Line685=3933\r
-Path685=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
+Path685=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
Line685.2=3938\r
-Path685.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
+Path685.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
Line687=3007\r
-Path687=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
+Path687=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
Line689=3085\r
-Path689=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path689=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line691=375\r
-Path691=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\Uart_Hci.c\r
+Path691=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\Uart_Hci.c\r
Line692=1524\r
-Path692=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
+Path692=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
Line693=1427\r
-Path693=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
+Path693=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
Line694=807\r
-Path694=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Classification.c\r
+Path694=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Classification.c\r
Line695=798\r
-Path695=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\mailbox\internal\top_mailbox.c\r
+Path695=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\mailbox\internal\top_mailbox.c\r
Line697=2591\r
-Path697=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
+Path697=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
Line698=136\r
-Path698=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
+Path698=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
Line698.2=1563\r
-Path698.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\system_init.c\r
+Path698.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\system_init.c\r
Line698.3=1649\r
-Path698.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\system_init.c\r
+Path698.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\system_init.c\r
Line699=2765\r
-Path699=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
+Path699=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
Line700=83\r
-Path700=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LSTO.c\r
+Path700=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LSTO.c\r
Line701=3518\r
-Path701=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
+Path701=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
Line702=3569\r
-Path702=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
+Path702=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
Line703=3531\r
-Path703=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
+Path703=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
Line704=3537\r
-Path704=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
+Path704=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
Line705=1062\r
-Path705=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
+Path705=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
Line706=2350\r
-Path706=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
+Path706=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
Line706.2=2351\r
-Path706.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
+Path706.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
Line706.3=2368\r
-Path706.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
+Path706.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
Line706.4=2373\r
-Path706.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
+Path706.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
Line707=2415\r
-Path707=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
-Line708=2025\r
-Path708=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
-Line709=1506\r
-Path709=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Path707=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
+Line708=2147\r
+Path708=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Line709=1556\r
+Path709=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
Line710=224\r
-Path710=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
+Path710=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
Line711=1274\r
-Path711=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path711=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line712=1260\r
-Path712=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path712=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line713=1283\r
-Path713=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path713=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line714=1590\r
-Path714=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path714=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line718=433\r
-Path718=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LSTO.c\r
+Path718=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LSTO.c\r
Line721=1298\r
-Path721=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path721=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line722=780\r
-Path722=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path722=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line723=1551\r
-Path723=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
+Path723=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
Line724=1750\r
-Path724=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\system_init.c\r
+Path724=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\system_init.c\r
Line725=697\r
-Path725=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+Path725=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
Line726=744\r
-Path726=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+Path726=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
Line727=1044\r
-Path727=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
-Line741=721\r
-Path741=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Utils.c\r
-Line741.2=1581\r
-Path741.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line741.3=1182\r
-Path741.3=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Path727=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Line741=1182\r
+Path741=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line741.2=721\r
+Path741.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Utils.c\r
+Line741.3=1581\r
+Path741.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
Line743=1179\r
-Path743=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
+Path743=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
Line744=806\r
-Path744=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\RF_Tester.c\r
+Path744=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\RF_Tester.c\r
Line744.2=813\r
-Path744.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\RF_Tester.c\r
+Path744.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\RF_Tester.c\r
Line744.3=820\r
-Path744.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\RF_Tester.c\r
+Path744.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\RF_Tester.c\r
Line744.4=833\r
-Path744.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\RF_Tester.c\r
+Path744.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\RF_Tester.c\r
Line744.5=839\r
-Path744.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\RF_Tester.c\r
+Path744.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\RF_Tester.c\r
Line744.6=871\r
-Path744.6=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\RF_Tester.c\r
+Path744.6=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\RF_Tester.c\r
Line745=371\r
-Path745=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
+Path745=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
Line749=420\r
-Path749=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
+Path749=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
Line750=634\r
-Path750=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
+Path750=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
Line751=928\r
-Path751=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
+Path751=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
Line752=931\r
-Path752=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
+Path752=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
Line755=252\r
-Path755=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
+Path755=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
Line756=578\r
-Path756=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
+Path756=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
Line757=685\r
-Path757=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
+Path757=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
Line758=688\r
-Path758=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
+Path758=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
Line759=893\r
-Path759=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
+Path759=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
Line760=967\r
-Path760=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
+Path760=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
Line761=1076\r
-Path761=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
+Path761=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
Line763=731\r
-Path763=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
+Path763=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
Line764=461\r
-Path764=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
+Path764=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
Line765=1164\r
-Path765=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
+Path765=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
Line766=1269\r
-Path766=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
+Path766=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
Line767=462\r
-Path767=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
+Path767=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\MAM\Memory_Allocation_Manager.c\r
Line769=1819\r
-Path769=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
+Path769=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
Line770=894\r
-Path770=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+Path770=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
Line773=633\r
-Path773=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
+Path773=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
Line774=395\r
-Path774=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
+Path774=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
Line778=2989\r
-Path778=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path778=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line780=514\r
-Path780=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
+Path780=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
Line781=3554\r
-Path781=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path781=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line786=204\r
-Path786=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
+Path786=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
Line789=2831\r
-Path789=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path789=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line790=808\r
-Path790=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
+Path790=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
Line791=255\r
-Path791=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_connection.c\r
+Path791=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_connection.c\r
Line796=3696\r
-Path796=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path796=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line798=210\r
-Path798=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_switch.c\r
+Path798=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_switch.c\r
Line799=3622\r
-Path799=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path799=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line801=5209\r
-Path801=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path801=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line803=2352\r
-Path803=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path803=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line804=2358\r
-Path804=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path804=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line805=1156\r
-Path805=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
+Path805=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
Line806=1475\r
-Path806=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
+Path806=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
Line808=1356\r
-Path808=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path808=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line808.2=645\r
-Path808.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+Path808.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
Line809=545\r
-Path809=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path809=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line810=738\r
-Path810=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path810=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line813=3450\r
-Path813=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path813=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line814=3724\r
-Path814=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path814=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line817=1054\r
-Path817=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
+Path817=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
Line819=3075\r
-Path819=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path819=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line821=291\r
-Path821=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
+Path821=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
Line825=3528\r
-Path825=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path825=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line825.2=3675\r
-Path825.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path825.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line827=2690\r
-Path827=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
+Path827=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
Line829=884\r
-Path829=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path829=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line830=2262\r
-Path830=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
+Path830=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
Line831=350\r
-Path831=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
+Path831=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\FM\fm.c\r
Line832=3380\r
-Path832=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path832=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line833=394\r
-Path833=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
+Path833=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
Line834=3751\r
-Path834=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path834=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line834.2=3753\r
-Path834.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path834.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line834.3=3755\r
-Path834.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path834.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line837=321\r
-Path837=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
+Path837=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
Line838=3453\r
-Path838=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path838=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line839=3004\r
-Path839=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path839=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line840=2997\r
-Path840=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path840=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line841=264\r
-Path841=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_qos.c\r
+Path841=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_qos.c\r
Line842=663\r
-Path842=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_qos.c\r
+Path842=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_qos.c\r
Line843=701\r
-Path843=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_qos.c\r
+Path843=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_qos.c\r
Line844=2675\r
-Path844=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
+Path844=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
Line845=4709\r
-Path845=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path845=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line845.2=4728\r
-Path845.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path845.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line845.3=4743\r
-Path845.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path845.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line845.4=4850\r
-Path845.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path845.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line847=5507\r
-Path847=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path847=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line848=2462\r
-Path848=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path848=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line849=2515\r
-Path849=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path849=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line850=2051\r
-Path850=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path850=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line851=2057\r
-Path851=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
-Line851.2=1186\r
-Path851.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Path851=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Line851.2=1216\r
+Path851.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
Line852=5573\r
-Path852=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path852=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line853=2563\r
-Path853=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path853=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line854=5564\r
-Path854=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path854=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line857=1588\r
-Path857=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path857=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line858=270\r
-Path858=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Afh.c\r
+Path858=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Afh.c\r
Line859=5171\r
-Path859=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path859=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line860=5264\r
-Path860=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path860=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line861=4999\r
-Path861=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path861=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line862=4844\r
-Path862=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path862=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line862.2=4859\r
-Path862.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path862.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line863=1129\r
-Path863=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RecoveryPage.c\r
+Path863=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RecoveryPage.c\r
Line863.2=417\r
-Path863.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lm_auto_recovery.c\r
+Path863.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lm_auto_recovery.c\r
Line864=3925\r
-Path864=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path864=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line865=4126\r
-Path865=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path865=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line866=2378\r
-Path866=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path866=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line867=3855\r
-Path867=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path867=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line868=3910\r
-Path868=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path868=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line869=4168\r
-Path869=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path869=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line870=4173\r
-Path870=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path870=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line873=5137\r
-Path873=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path873=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line874=5632\r
-Path874=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path874=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line875=5386\r
-Path875=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path875=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line876=3845\r
-Path876=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path876=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line877=1940\r
-Path877=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path877=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line879=5019\r
-Path879=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path879=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line879.2=5131\r
-Path879.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path879.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line881=5333\r
-Path881=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path881=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line882=2453\r
-Path882=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path882=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line883=5556\r
-Path883=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path883=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line883.2=5586\r
-Path883.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path883.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line884=5288\r
-Path884=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path884=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line885=351\r
-Path885=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
+Path885=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
Line885.2=768\r
-Path885.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
+Path885.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
Line887=416\r
-Path887=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Gemini.c\r
+Path887=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Gemini.c\r
Line888=430\r
-Path888=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Gemini.c\r
-Line888.2=1755\r
-Path888.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Path888=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Gemini.c\r
+Line888.2=1817\r
+Path888.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
Line889=4150\r
-Path889=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path889=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line889.2=4156\r
-Path889.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path889.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line891=4153\r
-Path891=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path891=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line892=455\r
-Path892=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection_manager.c\r
+Path892=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection_manager.c\r
Line892.2=459\r
-Path892.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection_manager.c\r
+Path892.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection_manager.c\r
Line893=5408\r
-Path893=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path893=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line894=659\r
-Path894=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection_manager.c\r
+Path894=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection_manager.c\r
Line895=548\r
-Path895=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection_manager.c\r
+Path895=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection_manager.c\r
Line896=751\r
-Path896=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection_manager.c\r
+Path896=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection_manager.c\r
Line897=1857\r
-Path897=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path897=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line898=436\r
-Path898=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_DRPB.c\r
+Path898=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_DRPB.c\r
Line899=950\r
-Path899=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_afh.c\r
+Path899=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_afh.c\r
Line900=258\r
-Path900=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_switch.c\r
+Path900=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_switch.c\r
Line900.2=333\r
-Path900.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_switch.c\r
-Line904=1268\r
-Path904=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
+Path900.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_switch.c\r
+Line902=1429\r
+Path902=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
+Line904=1485\r
+Path904=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
Line905=4053\r
-Path905=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path905=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line907=2325\r
-Path907=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
+Path907=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
Line908=2317\r
-Path908=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
+Path908=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
Line909=2307\r
-Path909=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
+Path909=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
Line910=2387\r
-Path910=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
+Path910=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
Line915=1614\r
-Path915=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
-Line916=1514\r
-Path916=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
-Line917=1596\r
-Path917=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
-Line918=1346\r
-Path918=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
-Line919=1200\r
-Path919=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
+Path915=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
+Line916=1731\r
+Path916=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
+Line917=1815\r
+Path917=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
+Line918=1396\r
+Path918=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Line919=1346\r
+Path919=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
Line920=572\r
-Path920=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
+Path920=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
Line921=585\r
-Path921=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line922=1194\r
-Path922=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
-Line924=511\r
-Path924=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Path921=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
+Line922=1340\r
+Path922=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
+Line924=533\r
+Path924=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
Line925=611\r
-Path925=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
-Line926=2039\r
-Path926=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Path925=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
+Line925.2=2515\r
+Path925.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Line926=2161\r
+Path926=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
Line927=2479\r
-Path927=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+Path927=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
Line927.2=2489\r
-Path927.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+Path927.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
Line928=2480\r
-Path928=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+Path928=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
Line928.2=2490\r
-Path928.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
-Line929=2032\r
-Path929=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Path928.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+Line929=2154\r
+Path929=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
Line930=2227\r
-Path930=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
+Path930=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
Line931=2231\r
-Path931=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
+Path931=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
Line932=2247\r
-Path932=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
+Path932=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
Line933=2251\r
-Path933=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
+Path933=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
Line934=2376\r
-Path934=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
+Path934=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
Line935=413\r
-Path935=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_switch.c\r
+Path935=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_switch.c\r
Line936=2449\r
-Path936=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
-Line937=519\r
-Path937=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
-Line940=1382\r
-Path940=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
-Line942=699\r
-Path942=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Path936=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
+Line937=541\r
+Path937=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Line940=1432\r
+Path940=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Line942=721\r
+Path942=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
Line956=5087\r
-Path956=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
+Path956=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
Line976=1824\r
-Path976=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
+Path976=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
Line977=1792\r
-Path977=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
-Line980=670\r
-Path980=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
-Line990=1386\r
-Path990=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
+Path977=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
+Line980=692\r
+Path980=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Line990=1603\r
+Path990=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
Line999=1071\r
-Path999=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Hold.c\r
+Path999=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Hold.c\r
Line1010=205\r
-Path1010=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lm2um.c\r
+Path1010=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lm2um.c\r
Line1025=2069\r
-Path1025=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicsnd.c\r
+Path1025=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicsnd.c\r
Line1038=557\r
-Path1038=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_tester.c\r
+Path1038=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_tester.c\r
Line1046=1104\r
-Path1046=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_utils.c\r
+Path1046=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_utils.c\r
Line1048=2190\r
-Path1048=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path1048=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line1048.2=1217\r
-Path1048.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
+Path1048.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
Line1049=2254\r
-Path1049=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path1049=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line1050=625\r
-Path1050=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+Path1050=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
Line1051=640\r
-Path1051=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+Path1051=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
Line1052=724\r
-Path1052=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1052=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1053=472\r
-Path1053=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_gate.c\r
+Path1053=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_gate.c\r
Line1053.2=530\r
-Path1053.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_gate.c\r
+Path1053.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_gate.c\r
Line1054=1143\r
-Path1054=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1054=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1056=108\r
-Path1056=M:\Omri_WPAN_45nm_FW_4_SP\ti\ANT\upper_mac\ant_upper_mac_sm.c\r
+Path1056=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\ANT\upper_mac\ant_upper_mac_sm.c\r
Line1057=63\r
-Path1057=M:\Omri_WPAN_45nm_FW_4_SP\ti\ANT\upper_mac\ant_connection.c\r
+Path1057=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\ANT\upper_mac\ant_connection.c\r
Line1057.2=63\r
-Path1057.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\ANT\upper_mac\ant_search.c\r
+Path1057.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\ANT\upper_mac\ant_search.c\r
Line1057.3=109\r
-Path1057.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\ANT\upper_mac\ant_upper_mac_sm.c\r
+Path1057.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\ANT\upper_mac\ant_upper_mac_sm.c\r
Line1058=1435\r
-Path1058=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1058=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1059=1911\r
-Path1059=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1059=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1060=875\r
-Path1060=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicsnd.c\r
+Path1060=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicsnd.c\r
Line1061=1512\r
-Path1061=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcievts.c\r
+Path1061=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcievts.c\r
Line1063=851\r
-Path1063=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_hcicmd.c\r
+Path1063=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_hcicmd.c\r
Line1073=392\r
-Path1073=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_tester.c\r
+Path1073=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_tester.c\r
Line1074=609\r
-Path1074=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_tester.c\r
+Path1074=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_tester.c\r
Line1078=1405\r
-Path1078=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_BT.c\r
+Path1078=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_BT.c\r
Line1080=2291\r
-Path1080=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
+Path1080=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
Line1081=1073\r
-Path1081=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1081=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1082=1486\r
-Path1082=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1082=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1083=246\r
-Path1083=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1083=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1086=1406\r
-Path1086=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_BT.c\r
+Path1086=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_BT.c\r
Line1087=1480\r
-Path1087=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
+Path1087=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
Line1087.2=1567\r
-Path1087.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
+Path1087.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
Line1087.3=1575\r
-Path1087.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
+Path1087.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
Line1087.4=1616\r
-Path1087.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
+Path1087.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
Line1087.5=1630\r
-Path1087.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
+Path1087.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
Line1087.6=1636\r
-Path1087.6=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
+Path1087.6=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
Line1088=1135\r
-Path1088=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1088=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1089=1144\r
-Path1089=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1089=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1089.2=1177\r
-Path1089.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1089.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1089.3=1211\r
-Path1089.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1089.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1089.4=1247\r
-Path1089.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1089.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1089.5=1261\r
-Path1089.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1089.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1089.6=1344\r
-Path1089.6=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1089.6=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1089.7=1410\r
-Path1089.7=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1089.7=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1089.8=1466\r
-Path1089.8=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1089.8=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1092=4263\r
-Path1092=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicrcv.c\r
+Path1092=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicrcv.c\r
Line1093=1134\r
-Path1093=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicsnd.c\r
+Path1093=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicsnd.c\r
Line1093.2=2318\r
-Path1093.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicsnd.c\r
+Path1093.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicsnd.c\r
Line1101=157\r
-Path1101=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_tester.c\r
+Path1101=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_tester.c\r
Line1102=170\r
-Path1102=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_tester.c\r
+Path1102=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_tester.c\r
Line1103=798\r
-Path1103=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_tester.c\r
+Path1103=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_tester.c\r
Line1107=1365\r
-Path1107=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_BT.c\r
+Path1107=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_BT.c\r
Line1108=1381\r
-Path1108=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_BT.c\r
+Path1108=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_BT.c\r
Line1109=306\r
-Path1109=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPevt.c\r
+Path1109=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPevt.c\r
Line1110=5232\r
-Path1110=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path1110=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line1111=351\r
-Path1111=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1111=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1112=233\r
-Path1112=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\six_wires_deep_sleep.c\r
+Path1112=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\six_wires_deep_sleep.c\r
Line1113=373\r
-Path1113=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\Uart_Hci.c\r
+Path1113=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\Uart_Hci.c\r
Line1115=1111\r
-Path1115=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
+Path1115=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
Line1115.2=1154\r
-Path1115.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
+Path1115.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
Line1116=1116\r
-Path1116=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
+Path1116=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
Line1116.2=1159\r
-Path1116.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
+Path1116.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
Line1118=290\r
-Path1118=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path1118=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line1118.2=302\r
-Path1118.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path1118.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line1118.3=1387\r
-Path1118.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path1118.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line1118.4=1461\r
-Path1118.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path1118.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line1120=652\r
-Path1120=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1120=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1122=1145\r
-Path1122=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
+Path1122=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
Line1123=779\r
-Path1123=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1123=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1124=842\r
-Path1124=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path1124=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line1128=657\r
-Path1128=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1128=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1130=573\r
-Path1130=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_main.c\r
+Path1130=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_main.c\r
Line1131=847\r
-Path1131=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1131=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1132=896\r
-Path1132=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1132=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1133=816\r
-Path1133=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1133=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1134=702\r
-Path1134=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+Path1134=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
Line1136=1979\r
-Path1136=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicsnd.c\r
+Path1136=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicsnd.c\r
Line1137=4151\r
-Path1137=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path1137=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line1140=4119\r
-Path1140=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path1140=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line1143=4169\r
-Path1143=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path1143=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line1143.2=4208\r
-Path1143.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path1143.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line1144=4200\r
-Path1144=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path1144=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line1150=78\r
-Path1150=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\transport_detection\Transport_Detection.c\r
+Path1150=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\transport_detection\Transport_Detection.c\r
Line1152=567\r
-Path1152=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\spi\spi.c\r
+Path1152=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\spi\spi.c\r
Line1153=753\r
-Path1153=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\spi\spi.c\r
+Path1153=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\spi\spi.c\r
Line1155=122\r
-Path1155=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\transport_detection\Transport_Detection.c\r
+Path1155=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\transport_detection\Transport_Detection.c\r
Line1158=3360\r
-Path1158=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path1158=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line1159=3361\r
-Path1159=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path1159=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line1161=2974\r
-Path1161=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path1161=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line1162=1235\r
-Path1162=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcievts.c\r
+Path1162=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcievts.c\r
Line1164=225\r
-Path1164=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\spi\spi.c\r
+Path1164=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\spi\spi.c\r
Line1167=245\r
-Path1167=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\spi\spi.c\r
+Path1167=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\spi\spi.c\r
Line1170=2230\r
-Path1170=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path1170=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line1174=2443\r
-Path1174=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
+Path1174=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
Line1174.2=883\r
-Path1174.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_InquiryScan.c\r
+Path1174.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_InquiryScan.c\r
Line1178=1014\r
-Path1178=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path1178=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line1179=767\r
-Path1179=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path1179=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line1180=1021\r
-Path1180=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path1180=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line1181=562\r
-Path1181=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path1181=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line1182=875\r
-Path1182=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path1182=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line1185=4516\r
-Path1185=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path1185=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line1188=439\r
-Path1188=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path1188=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line1193=471\r
-Path1193=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path1193=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line1194=524\r
-Path1194=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
+Path1194=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
Line1195=4506\r
-Path1195=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path1195=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line1197=335\r
-Path1197=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path1197=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line1198=626\r
-Path1198=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path1198=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line1199=1828\r
-Path1199=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
+Path1199=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
Line1208=144\r
-Path1208=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\UART_Protocol_detection\UART_Protocol_detection.c\r
+Path1208=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\UART_Protocol_detection\UART_Protocol_detection.c\r
Line1210=1209\r
-Path1210=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\spi\spi.c\r
+Path1210=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\spi\spi.c\r
Line1221=1000\r
-Path1221=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+Path1221=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
Line1223=416\r
-Path1223=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1223=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1224=254\r
-Path1224=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1224=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1224.2=259\r
-Path1224.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1224.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1224.3=1726\r
-Path1224.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1224.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1224.4=1820\r
-Path1224.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1224.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1224.5=1829\r
-Path1224.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1224.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1224.6=1836\r
-Path1224.6=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1224.6=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1224.7=1847\r
-Path1224.7=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1224.7=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1224.8=1852\r
-Path1224.8=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1224.8=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1224.9=1861\r
-Path1224.9=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1224.9=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1224.10=1869\r
-Path1224.10=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1224.10=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1224.11=1879\r
-Path1224.11=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1224.11=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1225=1633\r
-Path1225=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1225=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1233=104\r
-Path1233=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
+Path1233=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
Line1235=322\r
-Path1235=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
+Path1235=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
Line1236=325\r
-Path1236=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
+Path1236=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
Line1240=339\r
-Path1240=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
+Path1240=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
Line1241=181\r
-Path1241=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_send.c\r
+Path1241=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_send.c\r
Line1247=1205\r
-Path1247=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1247=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1248=1233\r
-Path1248=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_hcicmd.c\r
+Path1248=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_hcicmd.c\r
Line1251=137\r
-Path1251=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\UART_Protocol_detection\UART_Protocol_detection.c\r
+Path1251=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\UART_Protocol_detection\UART_Protocol_detection.c\r
Line1252=138\r
-Path1252=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+Path1252=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
Line1254=1314\r
-Path1254=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\spi\spi.c\r
+Path1254=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\spi\spi.c\r
Line1258=261\r
-Path1258=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\transport_detection\Transport_Detection.c\r
+Path1258=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\transport_detection\Transport_Detection.c\r
Line1259=285\r
-Path1259=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\transport_detection\Transport_Detection.c\r
+Path1259=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\transport_detection\Transport_Detection.c\r
Line1260=421\r
-Path1260=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
+Path1260=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
Line1261=231\r
-Path1261=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_send.c\r
+Path1261=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_send.c\r
Line1262=1370\r
-Path1262=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\spi\spi.c\r
+Path1262=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\spi\spi.c\r
Line1263=363\r
-Path1263=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
+Path1263=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
Line1264=2173\r
-Path1264=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1264=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1266=250\r
-Path1266=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_gate.c\r
+Path1266=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_gate.c\r
Line1267=150\r
-Path1267=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
+Path1267=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
Line1268=350\r
-Path1268=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_send.c\r
+Path1268=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_send.c\r
Line1269=311\r
-Path1269=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\HostInterface.c\r
+Path1269=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\HostInterface.c\r
Line1270=2213\r
-Path1270=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1270=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1272=1366\r
-Path1272=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1272=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1273=468\r
-Path1273=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\protocol_utils.c\r
+Path1273=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\protocol_utils.c\r
Line1275=1278\r
-Path1275=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_TOP.c\r
+Path1275=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_TOP.c\r
Line1276=1165\r
-Path1276=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_TOP.c\r
+Path1276=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_TOP.c\r
Line1277=495\r
-Path1277=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+Path1277=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
Line1277.2=1373\r
-Path1277.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\spi\spi.c\r
+Path1277.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\spi\spi.c\r
Line1289=1491\r
-Path1289=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1289=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1289.2=1571\r
-Path1289.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1289.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1292=406\r
-Path1292=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\system_init.c\r
+Path1292=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\system_init.c\r
Line1293=167\r
-Path1293=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1293=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1295=348\r
-Path1295=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1295=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1296=177\r
-Path1296=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1296=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1296.2=2172\r
-Path1296.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1296.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1300=265\r
-Path1300=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\basic_services\top_general_1.c\r
+Path1300=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\basic_services\top_general_1.c\r
Line1302=4366\r
-Path1302=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path1302=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line1304=402\r
-Path1304=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
+Path1304=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
Line1305=197\r
-Path1305=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmlc.c\r
+Path1305=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmlc.c\r
Line1308=823\r
-Path1308=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+Path1308=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
Line1309=841\r
-Path1309=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+Path1309=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
Line1310=851\r
-Path1310=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+Path1310=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
Line1311=1279\r
-Path1311=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+Path1311=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
Line1313=1206\r
-Path1313=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
+Path1313=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
Line1314=1268\r
-Path1314=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
+Path1314=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
Line1316=2053\r
-Path1316=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path1316=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line1317=2063\r
-Path1317=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path1317=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line1318=2069\r
-Path1318=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path1318=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line1319=2638\r
-Path1319=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path1319=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line1322=1553\r
-Path1322=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1322=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1323=1595\r
-Path1323=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1323=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1325=1891\r
-Path1325=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1325=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1327=1583\r
-Path1327=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path1327=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line1329=1851\r
-Path1329=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path1329=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line1331=1742\r
-Path1331=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path1331=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line1332=1771\r
-Path1332=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path1332=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line1333=2197\r
-Path1333=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1333=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1334=1462\r
-Path1334=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path1334=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line1334.2=1795\r
-Path1334.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path1334.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line1335=1231\r
-Path1335=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path1335=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line1337=2275\r
-Path1337=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1337=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1338=1172\r
-Path1338=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
+Path1338=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
Line1338.2=1183\r
-Path1338.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
+Path1338.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
Line1339=1427\r
-Path1339=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
+Path1339=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
Line1340=3185\r
-Path1340=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1340=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1341=1417\r
-Path1341=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
+Path1341=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
Line1342=1345\r
-Path1342=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
+Path1342=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
Line1343=1360\r
-Path1343=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
+Path1343=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
Line1344=149\r
-Path1344=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_connection.c\r
+Path1344=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_connection.c\r
Line1345=273\r
-Path1345=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_connection.c\r
+Path1345=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_connection.c\r
Line1347=484\r
-Path1347=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_connection.c\r
+Path1347=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_connection.c\r
Line1348=500\r
-Path1348=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_connection.c\r
+Path1348=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_connection.c\r
Line1349=528\r
-Path1349=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_connection.c\r
+Path1349=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_connection.c\r
Line1350=83\r
-Path1350=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_detach.c\r
+Path1350=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_detach.c\r
Line1351=608\r
-Path1351=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_encrypt.c\r
+Path1351=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_encrypt.c\r
Line1351.2=1712\r
-Path1351.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_encrypt.c\r
+Path1351.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_encrypt.c\r
Line1352=1080\r
-Path1352=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_encrypt.c\r
+Path1352=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_encrypt.c\r
Line1353=429\r
-Path1353=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_hold.c\r
+Path1353=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_hold.c\r
Line1353.2=434\r
-Path1353.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_hold.c\r
+Path1353.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_hold.c\r
Line1354=218\r
-Path1354=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_name.c\r
+Path1354=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_name.c\r
Line1355=338\r
-Path1355=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_pairing.c\r
+Path1355=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_pairing.c\r
Line1355.2=506\r
-Path1355.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_pairing.c\r
+Path1355.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_pairing.c\r
Line1356=169\r
-Path1356=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Nike_plus\nike_plus_um_data_path.c\r
-Line1358=2238\r
-Path1358=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
-Line1358.2=1332\r
-Path1358.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
-Line1358.3=1337\r
-Path1358.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+Path1356=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Nike_plus\nike_plus_um_data_path.c\r
+Line1358=1332\r
+Path1358=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+Line1358.2=1337\r
+Path1358.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+Line1358.3=2238\r
+Path1358.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
Line1361=2257\r
-Path1361=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path1361=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line1362=2249\r
-Path1362=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path1362=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line1363=2240\r
-Path1363=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path1363=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line1364=124\r
-Path1364=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_switch.c\r
+Path1364=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_switch.c\r
Line1365=645\r
-Path1365=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_switch.c\r
+Path1365=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_switch.c\r
Line1366=607\r
-Path1366=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path1366=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line1367=2215\r
-Path1367=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path1367=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line1367.2=2232\r
-Path1367.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path1367.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line1368=2756\r
-Path1368=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path1368=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line1369=2109\r
-Path1369=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path1369=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line1370=825\r
-Path1370=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
+Path1370=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
Line1371=831\r
-Path1371=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
+Path1371=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
Line1372=1375\r
-Path1372=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
+Path1372=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
Line1375=1185\r
-Path1375=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path1375=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line1376=1402\r
-Path1376=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+Path1376=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
Line1377=1231\r
-Path1377=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path1377=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line1378=2128\r
-Path1378=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path1378=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line1379=2079\r
-Path1379=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path1379=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line1380=1085\r
-Path1380=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff.c\r
+Path1380=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff.c\r
Line1381=361\r
-Path1381=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_name.c\r
+Path1381=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_name.c\r
Line1383=2736\r
-Path1383=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1383=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1384=426\r
-Path1384=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+Path1384=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
Line1385=460\r
-Path1385=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
+Path1385=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
Line1386=558\r
-Path1386=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
+Path1386=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
Line1387=546\r
-Path1387=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
+Path1387=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
Line1393=2600\r
-Path1393=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1393=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1403=572\r
-Path1403=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
+Path1403=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
Line1409=4460\r
-Path1409=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path1409=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line1410=4503\r
-Path1410=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path1410=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line1414=4684\r
-Path1414=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
-Line1414.2=949\r
-Path1414.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Path1414=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Line1414.2=978\r
+Path1414.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
Line1417=4705\r
-Path1417=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
-Line1417.2=970\r
-Path1417.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
-Line1418=1019\r
-Path1418=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
-Line1419=1030\r
-Path1419=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
-Line1420=1056\r
-Path1420=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
-Line1421=1067\r
-Path1421=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Path1417=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Line1417.2=999\r
+Path1417.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Line1418=1048\r
+Path1418=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Line1419=1059\r
+Path1419=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Line1420=1085\r
+Path1420=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Line1421=1096\r
+Path1421=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
Line1425=4747\r
-Path1425=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
-Line1425.2=1005\r
-Path1425.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Path1425=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Line1425.2=1034\r
+Path1425.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
Line1430=2140\r
-Path1430=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1430=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1432=2277\r
-Path1432=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1432=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1433=2324\r
-Path1433=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1433=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1434=2332\r
-Path1434=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1434=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1435=2512\r
-Path1435=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1435=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1441=2293\r
-Path1441=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
-Line1450=543\r
-Path1450=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
-Line1451=562\r
-Path1451=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
-Line1455=1124\r
-Path1455=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
-Line1468=2174\r
-Path1468=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
-Line1477=250\r
-Path1477=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
-Line1478=1361\r
-Path1478=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
-Line1478.2=4267\r
-Path1478.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicrcv.c\r
-Line1478.3=254\r
-Path1478.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
-Line1479=259\r
-Path1479=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
+Path1441=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Line1450=565\r
+Path1450=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Line1451=584\r
+Path1451=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Line1455=1270\r
+Path1455=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
+Line1468=2295\r
+Path1468=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Line1477=269\r
+Path1477=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
+Line1477.2=1910\r
+Path1477.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
+Line1477.3=1914\r
+Path1477.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
+Line1477.4=1920\r
+Path1477.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
+Line1478=4267\r
+Path1478=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicrcv.c\r
+Line1478.2=1361\r
+Path1478.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Line1478.3=273\r
+Path1478.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
+Line1479=278\r
+Path1479=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
Line1510=1764\r
-Path1510=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path1510=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line1536=130\r
-Path1536=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmlc.c\r
+Path1536=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmlc.c\r
Line1537=277\r
-Path1537=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmlc.c\r
+Path1537=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmlc.c\r
Line1538=304\r
-Path1538=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmlc.c\r
+Path1538=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmlc.c\r
Line1539=936\r
-Path1539=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+Path1539=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
Line1542=1617\r
-Path1542=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1542=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1544=516\r
-Path1544=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1544=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1545=2582\r
-Path1545=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1545=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1547=676\r
-Path1547=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+Path1547=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
Line1548=298\r
-Path1548=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\um2lm.c\r
-Line1549=943\r
-Path1549=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Path1548=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\um2lm.c\r
+Line1549=972\r
+Path1549=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
Line1551=1038\r
-Path1551=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1551=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1552=1018\r
-Path1552=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1552=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1554=429\r
-Path1554=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
+Path1554=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
Line1555=4336\r
-Path1555=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path1555=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line1556=375\r
-Path1556=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1556=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1557=3036\r
-Path1557=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1557=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1559=3269\r
-Path1559=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1559=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1560=982\r
-Path1560=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
+Path1560=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
Line1560.2=987\r
-Path1560.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
+Path1560.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
Line1562=192\r
-Path1562=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_cqddr.c\r
+Path1562=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_cqddr.c\r
Line1563=752\r
-Path1563=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_encrypt.c\r
+Path1563=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_encrypt.c\r
Line1564=1618\r
-Path1564=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_encrypt.c\r
+Path1564=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_encrypt.c\r
Line1565=363\r
-Path1565=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_pairing.c\r
+Path1565=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_pairing.c\r
Line1566=1116\r
-Path1566=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1566=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1568=687\r
-Path1568=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path1568=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line1569=498\r
-Path1569=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1569=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1569.2=564\r
-Path1569.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1569.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1569.3=621\r
-Path1569.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1569.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1569.4=2002\r
-Path1569.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1569.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1569.5=2050\r
-Path1569.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1569.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1571=1366\r
-Path1571=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
+Path1571=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
Line1571.2=1428\r
-Path1571.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
+Path1571.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
Line1571.3=1485\r
-Path1571.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
+Path1571.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
Line1571.4=3016\r
-Path1571.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1571.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1571.5=3164\r
-Path1571.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1571.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1573=1020\r
-Path1573=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
+Path1573=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
Line1574=560\r
-Path1574=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_switch.c\r
+Path1574=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_switch.c\r
Line1576=3847\r
-Path1576=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path1576=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line1577=118\r
-Path1577=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lm2um.c\r
+Path1577=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lm2um.c\r
Line1578=292\r
-Path1578=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path1578=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line1579=316\r
-Path1579=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path1579=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line1580=541\r
-Path1580=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path1580=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line1583=545\r
-Path1583=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path1583=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line1585=1386\r
-Path1585=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path1585=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line1586=826\r
-Path1586=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1586=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1587=2636\r
-Path1587=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1587=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1587.2=2666\r
-Path1587.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1587.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1587.3=2724\r
-Path1587.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1587.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1587.4=2821\r
-Path1587.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1587.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1587.5=2895\r
-Path1587.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1587.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1587.6=2974\r
-Path1587.6=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1587.6=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1587.7=3119\r
-Path1587.7=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1587.7=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1588=3284\r
-Path1588=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_settings.c\r
+Path1588=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_settings.c\r
Line1588.2=3294\r
-Path1588.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_settings.c\r
+Path1588.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_settings.c\r
Line1589=796\r
-Path1589=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path1589=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line1590=809\r
-Path1590=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path1590=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line1591=1014\r
-Path1591=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path1591=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line1592=1017\r
-Path1592=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path1592=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line1594=1364\r
-Path1594=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path1594=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line1594.2=1582\r
-Path1594.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path1594.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line1596=1465\r
-Path1596=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path1596=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line1597=2281\r
-Path1597=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path1597=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line1599=132\r
-Path1599=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Buffers\osa_buf_debug.c\r
+Path1599=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Buffers\osa_buf_debug.c\r
Line1600=1022\r
-Path1600=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path1600=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line1601=2276\r
-Path1601=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path1601=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line1604=149\r
-Path1604=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Buffers\osa_buf_debug.c\r
+Path1604=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Buffers\osa_buf_debug.c\r
Line1608=4114\r
-Path1608=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path1608=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line1615=3928\r
-Path1615=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path1615=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line1616=3950\r
-Path1616=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path1616=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line1618=62\r
-Path1618=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\UART_Protocol_detection\UART_Protocol_detection.c\r
+Path1618=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\UART_Protocol_detection\UART_Protocol_detection.c\r
Line1621=2236\r
-Path1621=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1621=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1622=1291\r
-Path1622=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+Path1622=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
Line1624=1303\r
-Path1624=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+Path1624=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
Line1625=1884\r
-Path1625=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1625=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1627=1346\r
-Path1627=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
+Path1627=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
Line1627.2=1348\r
-Path1627.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
+Path1627.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
Line1627.3=1360\r
-Path1627.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
+Path1627.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
Line1627.4=1408\r
-Path1627.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
+Path1627.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
Line1627.5=1410\r
-Path1627.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
+Path1627.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
Line1627.6=1422\r
-Path1627.6=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
+Path1627.6=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
Line1627.7=1465\r
-Path1627.7=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
+Path1627.7=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
Line1627.8=1467\r
-Path1627.8=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
+Path1627.8=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
Line1627.9=1479\r
-Path1627.9=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
+Path1627.9=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
Line1627.10=2836\r
-Path1627.10=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1627.10=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1627.11=2838\r
-Path1627.11=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1627.11=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1627.12=2850\r
-Path1627.12=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1627.12=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1627.13=2921\r
-Path1627.13=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1627.13=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1627.14=2923\r
-Path1627.14=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1627.14=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1627.15=2993\r
-Path1627.15=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1627.15=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1627.16=2995\r
-Path1627.16=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1627.16=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1627.17=3007\r
-Path1627.17=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1627.17=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1627.18=3144\r
-Path1627.18=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1627.18=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1627.19=3146\r
-Path1627.19=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1627.19=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1627.20=3156\r
-Path1627.20=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
-Line1628=923\r
-Path1628=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
+Path1627.20=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Line1628=966\r
+Path1628=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_patches_ram.c\r
Line1629=2089\r
-Path1629=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1629=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1629.2=2104\r
-Path1629.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1629.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1629.3=2117\r
-Path1629.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1629.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1629.4=2131\r
-Path1629.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1629.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1629.5=2144\r
-Path1629.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1629.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1629.6=2158\r
-Path1629.6=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1629.6=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1629.7=4304\r
-Path1629.7=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1629.7=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1629.8=4317\r
-Path1629.8=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1629.8=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1629.9=4330\r
-Path1629.9=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1629.9=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1629.10=4341\r
-Path1629.10=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path1629.10=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line1630=1051\r
-Path1630=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RecoveryPage.c\r
+Path1630=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RecoveryPage.c\r
Line1631=490\r
-Path1631=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lm_auto_recovery.c\r
+Path1631=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lm_auto_recovery.c\r
Line1632=1347\r
-Path1632=M:\Omri_WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
+Path1632=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
Line1632.2=1357\r
-Path1632.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
+Path1632.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
Line1633=1339\r
-Path1633=M:\Omri_WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
+Path1633=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
Line1634=1330\r
-Path1634=M:\Omri_WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
+Path1634=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
Line1635=1320\r
-Path1635=M:\Omri_WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
+Path1635=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
Line1636=1314\r
-Path1636=M:\Omri_WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
+Path1636=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
Line1640=2335\r
-Path1640=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path1640=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line1641=2375\r
-Path1641=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path1641=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line1642=129\r
-Path1642=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
+Path1642=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
Line1644=1818\r
-Path1644=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
+Path1644=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
Line1645=2686\r
-Path1645=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1645=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1647=2708\r
-Path1647=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1647=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1649=205\r
-Path1649=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
+Path1649=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
Line1652=2572\r
-Path1652=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1652=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1656=214\r
-Path1656=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
+Path1656=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
Line1656.2=239\r
-Path1656.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
+Path1656.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
Line1656.3=260\r
-Path1656.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
+Path1656.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
Line1656.4=281\r
-Path1656.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
+Path1656.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
Line1658=221\r
-Path1658=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
+Path1658=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
Line1659=1991\r
-Path1659=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1659=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1660=1985\r
-Path1660=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1660=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1662=2018\r
-Path1662=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1662=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1663=231\r
-Path1663=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
+Path1663=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
Line1663.2=252\r
-Path1663.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
+Path1663.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
Line1663.3=272\r
-Path1663.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
+Path1663.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
Line1664=217\r
-Path1664=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
+Path1664=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
Line1664.2=242\r
-Path1664.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
+Path1664.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
Line1664.3=262\r
-Path1664.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
+Path1664.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
Line1664.4=284\r
-Path1664.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
+Path1664.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
Line1665=219\r
-Path1665=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
+Path1665=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
Line1665.2=244\r
-Path1665.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
+Path1665.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
Line1665.3=264\r
-Path1665.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
+Path1665.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
Line1665.4=286\r
-Path1665.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
+Path1665.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
Line1666=3151\r
-Path1666=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_settings.c\r
+Path1666=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_settings.c\r
Line1666.2=3246\r
-Path1666.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_settings.c\r
+Path1666.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_settings.c\r
Line1667=2933\r
-Path1667=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Path1667=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
Line1668=260\r
-Path1668=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
+Path1668=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
Line1669=261\r
-Path1669=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
+Path1669=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
Line1670=631\r
-Path1670=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
+Path1670=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
Line1670.2=693\r
-Path1670.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
+Path1670.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
Line1671=1014\r
-Path1671=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_main.c\r
+Path1671=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_main.c\r
Line1672=1522\r
-Path1672=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
+Path1672=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
Line1673=1189\r
-Path1673=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
+Path1673=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
Line1674=1305\r
-Path1674=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
+Path1674=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
Line1675=93\r
-Path1675=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Collision_Avoidence\nfc_rf_collision_avoidance.c\r
+Path1675=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Collision_Avoidence\nfc_rf_collision_avoidance.c\r
Line1676=129\r
-Path1676=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Collision_Avoidence\nfc_rf_collision_avoidance.c\r
+Path1676=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Collision_Avoidence\nfc_rf_collision_avoidance.c\r
Line1677=119\r
-Path1677=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Collision_Avoidence\nfc_rf_collision_avoidance.c\r
+Path1677=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Collision_Avoidence\nfc_rf_collision_avoidance.c\r
Line1680=217\r
-Path1680=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_iso18092.c\r
+Path1680=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_iso18092.c\r
Line1681=1016\r
-Path1681=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_main.c\r
+Path1681=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_main.c\r
Line1682=386\r
-Path1682=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_data_exchange_defs.c\r
+Path1682=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_data_exchange_defs.c\r
Line1683=1450\r
-Path1683=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
+Path1683=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
Line1684=1554\r
-Path1684=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1684=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1684.2=1563\r
-Path1684.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1684.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1684.3=1572\r
-Path1684.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1684.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1684.4=1581\r
-Path1684.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1684.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1684.5=1590\r
-Path1684.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1684.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1684.6=1599\r
-Path1684.6=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1684.6=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1684.7=1608\r
-Path1684.7=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1684.7=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1684.8=1617\r
-Path1684.8=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1684.8=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1684.9=1626\r
-Path1684.9=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1684.9=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1684.10=1635\r
-Path1684.10=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1684.10=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1684.11=1644\r
-Path1684.11=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1684.11=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1685=1432\r
-Path1685=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
+Path1685=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
Line1686=1707\r
-Path1686=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_vs.c\r
+Path1686=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_vs.c\r
Line1687=731\r
-Path1687=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
+Path1687=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
Line1688=496\r
-Path1688=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
+Path1688=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
Line1689=504\r
-Path1689=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
+Path1689=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
Line1689.2=507\r
-Path1689.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
+Path1689.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
Line1690=85\r
-Path1690=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_trx.c\r
+Path1690=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_trx.c\r
Line1690.2=111\r
-Path1690.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_trx.c\r
+Path1690.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_trx.c\r
Line1691=309\r
-Path1691=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
+Path1691=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
Line1691.2=341\r
-Path1691.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
+Path1691.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
Line1691.3=364\r
-Path1691.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
+Path1691.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
Line1692=457\r
-Path1692=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
+Path1692=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
Line1693=481\r
-Path1693=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
+Path1693=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
Line1694=507\r
-Path1694=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
+Path1694=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
Line1695=1311\r
-Path1695=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
+Path1695=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
Line1697=1390\r
-Path1697=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
+Path1697=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
Line1698=566\r
-Path1698=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
+Path1698=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
Line1699=1312\r
-Path1699=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
+Path1699=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
Line1700=732\r
-Path1700=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
+Path1700=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
Line1701=770\r
-Path1701=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
+Path1701=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
Line1702=784\r
-Path1702=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
+Path1702=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
Line1704=1555\r
-Path1704=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
+Path1704=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
Line1706=459\r
-Path1706=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_personality_mgmt.c\r
+Path1706=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_personality_mgmt.c\r
Line1707=663\r
-Path1707=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_calibrations.c\r
+Path1707=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_calibrations.c\r
Line1707.2=2214\r
-Path1707.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF.c\r
+Path1707.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF.c\r
Line1708=786\r
-Path1708=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
+Path1708=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
Line1709=333\r
-Path1709=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
+Path1709=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
Line1709.2=372\r
-Path1709.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
+Path1709.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
Line1709.3=385\r
-Path1709.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
+Path1709.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
Line1710=430\r
-Path1710=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
+Path1710=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
Line1711=499\r
-Path1711=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
+Path1711=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
Line1712=532\r
-Path1712=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
+Path1712=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
Line1713=910\r
-Path1713=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
+Path1713=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
Line1714=940\r
-Path1714=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
+Path1714=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
Line1715=335\r
-Path1715=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
+Path1715=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
Line1719=727\r
-Path1719=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
+Path1719=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
Line1722=891\r
-Path1722=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
+Path1722=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
Line1722.2=906\r
-Path1722.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
+Path1722.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
Line1722.3=913\r
-Path1722.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
+Path1722.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
Line1722.4=933\r
-Path1722.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
+Path1722.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
Line1722.5=980\r
-Path1722.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
+Path1722.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
Line1723=952\r
-Path1723=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
+Path1723=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
Line1723.2=1051\r
-Path1723.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
+Path1723.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
Line1723.3=1139\r
-Path1723.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
+Path1723.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
Line1723.4=1211\r
-Path1723.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
+Path1723.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
Line1724=30\r
-Path1724=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\NFC_CLFdefs.h\r
+Path1724=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\NFC_CLFdefs.h\r
Line1724.2=40\r
-Path1724.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\NFC_CLFdefs.h\r
+Path1724.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\NFC_CLFdefs.h\r
Line1724.3=41\r
-Path1724.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\NFC_CLFdefs.h\r
+Path1724.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\NFC_CLFdefs.h\r
Line1724.4=25\r
-Path1724.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\NFC_PHYdefs.h\r
+Path1724.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\NFC_PHYdefs.h\r
Line1724.5=32\r
-Path1724.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\NFC_PHYdefs.h\r
+Path1724.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\NFC_PHYdefs.h\r
Line1724.6=33\r
-Path1724.6=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\NFC_PHYdefs.h\r
+Path1724.6=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\NFC_PHYdefs.h\r
Line1724.7=46\r
-Path1724.7=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\NFC_PHYdefs.h\r
+Path1724.7=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\NFC_PHYdefs.h\r
Line1724.8=92\r
-Path1724.8=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\NFC_PHYdefs.h\r
+Path1724.8=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\NFC_PHYdefs.h\r
Line1724.9=93\r
-Path1724.9=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\NFC_PHYdefs.h\r
+Path1724.9=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\NFC_PHYdefs.h\r
Line1725=32\r
-Path1725=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\NFC_CLFdefs.h\r
+Path1725=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\NFC_CLFdefs.h\r
Line1727=393\r
-Path1727=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep.c\r
+Path1727=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep.c\r
Line1728=277\r
-Path1728=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_iso15693_technology.c\r
+Path1728=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_iso15693_technology.c\r
Line1729=307\r
-Path1729=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_iso15693_technology.c\r
+Path1729=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_iso15693_technology.c\r
Line1730=341\r
-Path1730=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_iso15693_technology.c\r
+Path1730=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_iso15693_technology.c\r
Line1731=360\r
-Path1731=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_iso15693_technology.c\r
+Path1731=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_iso15693_technology.c\r
Line1732=400\r
-Path1732=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_iso15693_technology.c\r
+Path1732=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_iso15693_technology.c\r
Line1733=416\r
-Path1733=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_iso15693_technology.c\r
+Path1733=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_iso15693_technology.c\r
Line1734=438\r
-Path1734=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_iso15693_technology.c\r
+Path1734=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_iso15693_technology.c\r
Line1735=734\r
-Path1735=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
+Path1735=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
Line1738=307\r
-Path1738=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_calibrations.c\r
+Path1738=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_calibrations.c\r
Line1739=350\r
-Path1739=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_calibrations.c\r
+Path1739=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_calibrations.c\r
Line1740=377\r
-Path1740=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_calibrations.c\r
+Path1740=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_calibrations.c\r
Line1741=408\r
-Path1741=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_calibrations.c\r
+Path1741=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_calibrations.c\r
Line1742=480\r
-Path1742=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_calibrations.c\r
+Path1742=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_calibrations.c\r
Line1743=546\r
-Path1743=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_calibrations.c\r
+Path1743=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_calibrations.c\r
Line1744=621\r
-Path1744=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_calibrations.c\r
+Path1744=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_calibrations.c\r
Line1745=1210\r
-Path1745=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
+Path1745=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
Line1745.2=1248\r
-Path1745.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
+Path1745.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
Line1745.3=535\r
-Path1745.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_SASE_manager.c\r
+Path1745.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_SASE_manager.c\r
Line1745.4=404\r
-Path1745.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
+Path1745.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
Line1745.5=536\r
-Path1745.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
+Path1745.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
Line1746=1234\r
-Path1746=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
+Path1746=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
Line1746.2=1249\r
-Path1746.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
+Path1746.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
Line1746.3=1283\r
-Path1746.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
+Path1746.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
Line1746.4=1306\r
-Path1746.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
+Path1746.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
Line1746.5=1327\r
-Path1746.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
+Path1746.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
Line1746.6=1333\r
-Path1746.6=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
+Path1746.6=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
Line1746.7=1362\r
-Path1746.7=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
+Path1746.7=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
Line1746.8=1372\r
-Path1746.8=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
+Path1746.8=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
Line1746.9=1381\r
-Path1746.9=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
+Path1746.9=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
Line1746.10=1396\r
-Path1746.10=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
+Path1746.10=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
Line1774=931\r
-Path1774=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path1774=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line1775=437\r
-Path1775=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path1775=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line1775.2=937\r
-Path1775.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path1775.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line1777=683\r
-Path1777=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path1777=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line1778=737\r
-Path1778=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path1778=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line1779=671\r
-Path1779=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path1779=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line1780=1410\r
-Path1780=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path1780=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line1783=464\r
-Path1783=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path1783=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line1784=456\r
-Path1784=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path1784=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line1785=472\r
-Path1785=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path1785=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line1786=414\r
-Path1786=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path1786=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line1787=408\r
-Path1787=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path1787=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line1788=392\r
-Path1788=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path1788=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line1789=1057\r
-Path1789=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path1789=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line1790=386\r
-Path1790=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path1790=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line1791=180\r
-Path1791=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path1791=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line1792=468\r
-Path1792=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_gate.c\r
+Path1792=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_gate.c\r
Line1792.2=525\r
-Path1792.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_gate.c\r
+Path1792.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_gate.c\r
Line1793=426\r
-Path1793=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
+Path1793=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
Line1794=692\r
-Path1794=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
+Path1794=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
Line1795=311\r
-Path1795=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path1795=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line1796=454\r
-Path1796=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
+Path1796=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
Line1796.2=1295\r
-Path1796.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
+Path1796.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
Line1798=3173\r
-Path1798=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_settings.c\r
+Path1798=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_settings.c\r
Line1798.2=3268\r
-Path1798.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_settings.c\r
+Path1798.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_settings.c\r
Line1799=3162\r
-Path1799=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_settings.c\r
+Path1799=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_settings.c\r
Line1799.2=3256\r
-Path1799.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_settings.c\r
+Path1799.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_settings.c\r
Line1800=420\r
-Path1800=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path1800=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line1801=995\r
-Path1801=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
+Path1801=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
Line1802=3182\r
-Path1802=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_settings.c\r
+Path1802=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_settings.c\r
Line1806=410\r
-Path1806=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff.c\r
+Path1806=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff.c\r
Line1807=430\r
-Path1807=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff.c\r
+Path1807=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff.c\r
Line1808=463\r
-Path1808=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff.c\r
+Path1808=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff.c\r
Line1809=3210\r
-Path1809=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_settings.c\r
+Path1809=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_settings.c\r
Line1810=752\r
-Path1810=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
+Path1810=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
Line1811=820\r
-Path1811=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
+Path1811=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
Line1812=926\r
-Path1812=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
+Path1812=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
Line1813=1080\r
-Path1813=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
+Path1813=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
Line1814=854\r
-Path1814=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
+Path1814=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
Line1816=234\r
-Path1816=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_admin_gate.c\r
+Path1816=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_admin_gate.c\r
Line1818=1936\r
-Path1818=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1818=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1819=552\r
-Path1819=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_gate.c\r
+Path1819=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_gate.c\r
Line1820=562\r
-Path1820=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_gate.c\r
+Path1820=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_gate.c\r
Line1821=556\r
-Path1821=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_gate.c\r
+Path1821=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_gate.c\r
Line1822=566\r
-Path1822=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_gate.c\r
+Path1822=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_gate.c\r
Line1823=423\r
-Path1823=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
+Path1823=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
Line1824=1884\r
-Path1824=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF.c\r
+Path1824=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF.c\r
Line1824.2=140\r
-Path1824.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_utils.c\r
+Path1824.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_utils.c\r
Line1824.3=217\r
-Path1824.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_utils.c\r
+Path1824.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_utils.c\r
Line1825=224\r
-Path1825=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
+Path1825=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
Line1825.2=258\r
-Path1825.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
+Path1825.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
Line1825.3=268\r
-Path1825.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
+Path1825.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
Line1825.4=311\r
-Path1825.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
+Path1825.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
Line1825.5=365\r
-Path1825.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
+Path1825.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
Line1825.6=387\r
-Path1825.6=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
+Path1825.6=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
Line1825.7=449\r
-Path1825.7=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
+Path1825.7=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
Line1825.8=466\r
-Path1825.8=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
+Path1825.8=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
Line1825.9=659\r
-Path1825.9=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
+Path1825.9=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
Line1825.10=688\r
-Path1825.10=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
+Path1825.10=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
Line1825.11=778\r
-Path1825.11=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
+Path1825.11=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
Line1825.12=818\r
-Path1825.12=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
+Path1825.12=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
Line1826=428\r
-Path1826=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_SASE_manager.c\r
+Path1826=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_SASE_manager.c\r
Line1826.2=447\r
-Path1826.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_SASE_manager.c\r
+Path1826.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_SASE_manager.c\r
Line1827=741\r
-Path1827=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
+Path1827=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
Line1828=1605\r
-Path1828=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1828=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1829=762\r
-Path1829=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_SASE_manager.c\r
+Path1829=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_SASE_manager.c\r
Line1830=226\r
-Path1830=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1830=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1831=200\r
-Path1831=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1831=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1832=2334\r
-Path1832=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1832=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1833=1918\r
-Path1833=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF.c\r
+Path1833=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF.c\r
Line1834=828\r
-Path1834=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_SASE_manager.c\r
+Path1834=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_SASE_manager.c\r
Line1834.2=836\r
-Path1834.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_SASE_manager.c\r
+Path1834.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_SASE_manager.c\r
Line1835=1736\r
-Path1835=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1835=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1835.2=1768\r
-Path1835.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path1835.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line1836=863\r
-Path1836=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_buffer.c\r
+Path1836=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_buffer.c\r
Line1837=859\r
-Path1837=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_buffer.c\r
+Path1837=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_buffer.c\r
Line1838=855\r
-Path1838=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_buffer.c\r
+Path1838=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_buffer.c\r
Line1839=464\r
-Path1839=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
+Path1839=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
Line1839.2=467\r
-Path1839.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
+Path1839.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
Line1839.3=852\r
-Path1839.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_buffer.c\r
+Path1839.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_buffer.c\r
Line1840=216\r
-Path1840=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
+Path1840=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
Line1841=1360\r
-Path1841=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
+Path1841=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
Line1842=1834\r
-Path1842=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
+Path1842=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
Line1843=842\r
-Path1843=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_buffer.c\r
+Path1843=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_buffer.c\r
Line1844=1765\r
-Path1844=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_send.c\r
+Path1844=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_send.c\r
Line1845=1804\r
-Path1845=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_send.c\r
+Path1845=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_send.c\r
Line1846=431\r
-Path1846=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
+Path1846=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
Line1847=1275\r
-Path1847=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
+Path1847=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
Line1848=442\r
-Path1848=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
+Path1848=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
Line1848.2=549\r
-Path1848.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
+Path1848.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
Line1848.3=666\r
-Path1848.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
+Path1848.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
Line1848.4=759\r
-Path1848.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
+Path1848.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
Line1848.5=899\r
-Path1848.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
+Path1848.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
Line1850=589\r
-Path1850=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_main.c\r
+Path1850=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_main.c\r
Line1851=196\r
-Path1851=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
+Path1851=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
Line1851.2=349\r
-Path1851.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
+Path1851.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
Line1851.3=481\r
-Path1851.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
+Path1851.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
Line1851.4=606\r
-Path1851.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
+Path1851.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
Line1851.5=725\r
-Path1851.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
+Path1851.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
Line1851.6=1011\r
-Path1851.6=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
+Path1851.6=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
Line1852=906\r
-Path1852=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
+Path1852=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
Line1854=1828\r
-Path1854=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1854=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1854.2=657\r
-Path1854.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
+Path1854.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
Line1855=1247\r
-Path1855=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
+Path1855=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
Line1856=1439\r
-Path1856=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
+Path1856=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
Line1857=379\r
-Path1857=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
+Path1857=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
Line1858=1293\r
-Path1858=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
+Path1858=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
Line1861=173\r
-Path1861=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
+Path1861=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
Line1862=201\r
-Path1862=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
+Path1862=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
Line1863=99\r
-Path1863=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_management_gate.c\r
+Path1863=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_management_gate.c\r
Line1865=998\r
-Path1865=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_greedy_collection.c\r
+Path1865=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_greedy_collection.c\r
Line1866=293\r
-Path1866=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_admin_gate.c\r
+Path1866=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_admin_gate.c\r
Line1867=902\r
-Path1867=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_greedy_collection.c\r
+Path1867=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_greedy_collection.c\r
Line1868=958\r
-Path1868=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path1868=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line1869=1142\r
-Path1869=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_vs.c\r
+Path1869=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_vs.c\r
Line1870=437\r
-Path1870=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path1870=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line1871=353\r
-Path1871=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_gate.c\r
+Path1871=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_gate.c\r
Line1872=580\r
-Path1872=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
+Path1872=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
Line1873=195\r
-Path1873=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcf_technology.c\r
+Path1873=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcf_technology.c\r
Line1873.2=204\r
-Path1873.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcf_technology.c\r
+Path1873.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcf_technology.c\r
Line1873.3=224\r
-Path1873.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcf_technology.c\r
+Path1873.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcf_technology.c\r
Line1873.4=273\r
-Path1873.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcf_technology.c\r
+Path1873.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcf_technology.c\r
Line1873.5=292\r
-Path1873.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcf_technology.c\r
+Path1873.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcf_technology.c\r
Line1877=1172\r
-Path1877=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
+Path1877=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
Line1878=1123\r
-Path1878=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
+Path1878=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
Line1879=346\r
-Path1879=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
+Path1879=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
Line1880=1190\r
-Path1880=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
+Path1880=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_main_state_machine.c\r
Line1883=665\r
-Path1883=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
+Path1883=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
Line1884=185\r
-Path1884=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
+Path1884=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
Line1884.2=222\r
-Path1884.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
+Path1884.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
Line1885=1837\r
-Path1885=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
+Path1885=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_main.c\r
Line1886=1095\r
-Path1886=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
+Path1886=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
Line1887=1251\r
-Path1887=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
+Path1887=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfca_technology.c\r
Line1888=451\r
-Path1888=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
+Path1888=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\nci\nfc_nci_recv.c\r
Line1889=1145\r
-Path1889=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_utils.c\r
+Path1889=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_utils.c\r
Line1891=346\r
-Path1891=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_personality_mgmt.c\r
+Path1891=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_personality_mgmt.c\r
Line1892=812\r
-Path1892=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
+Path1892=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\nfc_reader_sm.c\r
Line1893=420\r
-Path1893=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_personality_mgmt.c\r
+Path1893=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_personality_mgmt.c\r
Line1894=559\r
-Path1894=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_personality_mgmt.c\r
+Path1894=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_personality_mgmt.c\r
Line1895=920\r
-Path1895=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_personality_mgmt.c\r
+Path1895=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_personality_mgmt.c\r
Line1896=1033\r
-Path1896=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_personality_mgmt.c\r
+Path1896=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_personality_mgmt.c\r
Line1897=558\r
-Path1897=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
+Path1897=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
Line1898=164\r
-Path1898=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
+Path1898=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
Line1898.2=205\r
-Path1898.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
+Path1898.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
Line1898.3=218\r
-Path1898.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
+Path1898.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
Line1898.4=245\r
-Path1898.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
+Path1898.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
Line1898.5=269\r
-Path1898.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
+Path1898.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
Line1898.6=294\r
-Path1898.6=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
+Path1898.6=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
Line1898.7=337\r
-Path1898.7=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
+Path1898.7=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
Line1898.8=438\r
-Path1898.8=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
+Path1898.8=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
Line1898.9=477\r
-Path1898.9=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
+Path1898.9=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_WI.c\r
Line1899=1060\r
-Path1899=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
+Path1899=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfcb_technology.c\r
Line1947=1233\r
-Path1947=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
+Path1947=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
Line2045=138\r
-Path2045=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff_Subrate.c\r
+Path2045=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff_Subrate.c\r
Line2047=937\r
-Path2047=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
+Path2047=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
Line2048=582\r
-Path2048=M:\Omri_WPAN_45nm_FW_4_SP\ti\Utils\Trace.c\r
+Path2048=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Utils\Trace.c\r
Line2049=757\r
-Path2049=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicrcv.c\r
+Path2049=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicrcv.c\r
Line2049.2=4711\r
-Path2049.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicrcv.c\r
+Path2049.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicrcv.c\r
Line2050=1358\r
-Path2050=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicsnd.c\r
+Path2050=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicsnd.c\r
Line2051=242\r
-Path2051=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
+Path2051=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
Line2052=1206\r
-Path2052=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
+Path2052=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
Line2053=1684\r
-Path2053=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
+Path2053=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
Line2054=1819\r
-Path2054=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
+Path2054=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
Line2055=1936\r
-Path2055=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
+Path2055=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
Line2056=2046\r
-Path2056=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
+Path2056=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
Line2057=863\r
-Path2057=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_hcicmd.c\r
+Path2057=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_hcicmd.c\r
Line2058=698\r
-Path2058=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_hcievt.c\r
+Path2058=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\Customers\palau_hcievt.c\r
Line2060=238\r
-Path2060=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIT\HCI_SCO_Transport.c\r
+Path2060=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIT\HCI_SCO_Transport.c\r
Line2062=693\r
-Path2062=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Utils.c\r
+Path2062=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Utils.c\r
Line2065=663\r
-Path2065=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_BT.c\r
+Path2065=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_BT.c\r
Line2070=575\r
-Path2070=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
+Path2070=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
Line2072=298\r
-Path2072=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\Cdc.c\r
+Path2072=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\Cdc.c\r
Line2074=640\r
-Path2074=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\Cdc.c\r
+Path2074=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\Cdc.c\r
Line2075=1065\r
-Path2075=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path2075=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line2076=968\r
-Path2076=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
+Path2076=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
Line2077=661\r
-Path2077=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_afh.c\r
+Path2077=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_afh.c\r
Line2078=2472\r
-Path2078=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
+Path2078=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
Line2079=2546\r
-Path2079=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
+Path2079=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
Line2081=2763\r
-Path2081=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
+Path2081=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
Line2088=3238\r
-Path2088=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
+Path2088=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
Line2089=3262\r
-Path2089=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
+Path2089=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
Line2090=3271\r
-Path2090=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
+Path2090=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
Line2091=256\r
-Path2091=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Classification.c\r
+Path2091=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Classification.c\r
Line2092=215\r
-Path2092=M:\Omri_WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
+Path2092=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
Line2094=93\r
-Path2094=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
+Path2094=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
Line2095=131\r
-Path2095=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
+Path2095=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
Line2095.2=406\r
-Path2095.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
+Path2095.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
Line2096=428\r
-Path2096=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
+Path2096=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
Line2097=442\r
-Path2097=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
+Path2097=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
Line2099=493\r
-Path2099=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
+Path2099=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
Line2100=501\r
-Path2100=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
+Path2100=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
Line2103=1129\r
-Path2103=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
+Path2103=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
Line2107=927\r
-Path2107=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Hold.c\r
+Path2107=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Hold.c\r
Line2110=731\r
-Path2110=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Inquiry.c\r
+Path2110=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Inquiry.c\r
Line2111=886\r
-Path2111=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Inquiry.c\r
+Path2111=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Inquiry.c\r
Line2112=527\r
-Path2112=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_InquiryScan.c\r
+Path2112=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_InquiryScan.c\r
Line2113=604\r
-Path2113=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_InquiryScan.c\r
+Path2113=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_InquiryScan.c\r
Line2114=684\r
-Path2114=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_InquiryScan.c\r
+Path2114=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_InquiryScan.c\r
Line2115=753\r
-Path2115=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_InquiryScan.c\r
+Path2115=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_InquiryScan.c\r
Line2116=261\r
-Path2116=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LSTO.c\r
+Path2116=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LSTO.c\r
Line2117=990\r
-Path2117=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_MS_Switch.c\r
-Line2118=394\r
-Path2118=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Main.c\r
-Line2118.2=1721\r
-Path2118.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
-Line2118.3=81\r
-Path2118.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\ANT\upper_mac\ant_sleep.c\r
+Path2117=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_MS_Switch.c\r
+Line2118=81\r
+Path2118=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\ANT\upper_mac\ant_sleep.c\r
+Line2118.2=394\r
+Path2118.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Main.c\r
+Line2118.3=1721\r
+Path2118.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
Line2119=637\r
-Path2119=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Page.c\r
+Path2119=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Page.c\r
Line2120=1401\r
-Path2120=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path2120=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line2121=1503\r
-Path2121=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\system_init.c\r
+Path2121=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\system_init.c\r
Line2122=2298\r
-Path2122=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path2122=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line2125=502\r
-Path2125=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
+Path2125=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
Line2126=584\r
-Path2126=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
+Path2126=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
Line2127=645\r
-Path2127=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
+Path2127=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
Line2128=744\r
-Path2128=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
+Path2128=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
Line2129=807\r
-Path2129=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
+Path2129=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
Line2130=848\r
-Path2130=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
+Path2130=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PageScan.c\r
Line2132=301\r
-Path2132=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_encrypt.c\r
+Path2132=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_encrypt.c\r
Line2132.2=349\r
-Path2132.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_encrypt.c\r
+Path2132.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_encrypt.c\r
Line2132.3=410\r
-Path2132.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_encrypt.c\r
+Path2132.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_encrypt.c\r
Line2132.4=431\r
-Path2132.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_encrypt.c\r
+Path2132.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_encrypt.c\r
Line2135=274\r
-Path2135=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
+Path2135=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
Line2136=350\r
-Path2136=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
+Path2136=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
Line2147=261\r
-Path2147=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
+Path2147=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
Line2148=647\r
-Path2148=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
+Path2148=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
Line2149=270\r
-Path2149=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
+Path2149=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
Line2150=2640\r
-Path2150=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
+Path2150=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
Line2151=2728\r
-Path2151=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
+Path2151=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
Line2152=3003\r
-Path2152=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
+Path2152=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
Line2153=3094\r
-Path2153=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
+Path2153=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
Line2155=340\r
-Path2155=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path2155=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line2156=426\r
-Path2156=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path2156=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line2157=431\r
-Path2157=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path2157=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line2158=717\r
-Path2158=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path2158=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line2160=940\r
-Path2160=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path2160=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line2161=982\r
-Path2161=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path2161=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line2163=652\r
-Path2163=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
+Path2163=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
Line2167=2072\r
-Path2167=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
+Path2167=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
Line2168=2205\r
-Path2168=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
+Path2168=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
Line2169=2234\r
-Path2169=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
+Path2169=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
Line2170=2281\r
-Path2170=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
+Path2170=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
Line2171=2342\r
-Path2171=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
+Path2171=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
Line2172=2530\r
-Path2172=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
+Path2172=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
Line2173=2738\r
-Path2173=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
+Path2173=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
Line2174=2788\r
-Path2174=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
+Path2174=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
Line2175=2917\r
-Path2175=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
+Path2175=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
Line2176=2926\r
-Path2176=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
+Path2176=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_TestMode.c\r
Line2177=322\r
-Path2177=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
+Path2177=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
Line2178=769\r
-Path2178=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
+Path2178=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
Line2179=996\r
-Path2179=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
+Path2179=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
Line2180=145\r
-Path2180=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Windy.c\r
+Path2180=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Windy.c\r
Line2181=2412\r
-Path2181=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
+Path2181=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
Line2182=1432\r
-Path2182=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+Path2182=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
Line2183=1569\r
-Path2183=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+Path2183=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
Line2184=3032\r
-Path2184=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvhci.c\r
+Path2184=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvhci.c\r
Line2185=647\r
-Path2185=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
+Path2185=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
Line2186=739\r
-Path2186=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
+Path2186=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
Line2187=767\r
-Path2187=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
+Path2187=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
Line2188=1199\r
-Path2188=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
+Path2188=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
Line2188.2=1230\r
-Path2188.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
+Path2188.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
Line2189=1262\r
-Path2189=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
+Path2189=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmrcvlc.c\r
Line2190=1939\r
-Path2190=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path2190=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line2192=349\r
-Path2192=M:\Omri_WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
+Path2192=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Utils\utils.c\r
Line2198=640\r
-Path2198=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Afh.c\r
+Path2198=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Afh.c\r
Line2200=2359\r
-Path2200=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\system_init.c\r
+Path2200=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\system_init.c\r
Line2201=1517\r
-Path2201=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_afh.c\r
+Path2201=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_afh.c\r
Line2202=844\r
-Path2202=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
+Path2202=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_authentication.c\r
Line2203=622\r
-Path2203=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_encrypt.c\r
+Path2203=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_encrypt.c\r
Line2204=372\r
-Path2204=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_hold.c\r
+Path2204=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_hold.c\r
Line2205=474\r
-Path2205=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_hold.c\r
+Path2205=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_hold.c\r
Line2206=647\r
-Path2206=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_pairing.c\r
+Path2206=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_pairing.c\r
Line2207=360\r
-Path2207=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Mailbox\osa_mailbox.c\r
+Path2207=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Mailbox\osa_mailbox.c\r
Line2218=425\r
-Path2218=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Mailbox\osa_mailbox.c\r
+Path2218=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Mailbox\osa_mailbox.c\r
Line2220=663\r
-Path2220=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff.c\r
+Path2220=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff.c\r
Line2222=1476\r
-Path2222=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
+Path2222=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
Line2223=2606\r
-Path2223=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
+Path2223=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
Line2224=335\r
-Path2224=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path2224=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line2225=427\r
-Path2225=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path2225=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line2226=327\r
-Path2226=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
+Path2226=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
Line2227=692\r
-Path2227=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path2227=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line2228=1166\r
-Path2228=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path2228=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line2229=1497\r
-Path2229=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path2229=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line2230=1587\r
-Path2230=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path2230=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line2231=1927\r
-Path2231=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path2231=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line2232=2104\r
-Path2232=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path2232=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line2234=393\r
-Path2234=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicsnd.c\r
+Path2234=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicsnd.c\r
Line2235=2754\r
-Path2235=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path2235=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line2236=2828\r
-Path2236=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path2236=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line2237=206\r
-Path2237=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Piconizer.c\r
+Path2237=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Piconizer.c\r
Line2238=2092\r
-Path2238=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
+Path2238=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
Line2239=3224\r
-Path2239=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path2239=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line2240=845\r
-Path2240=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
+Path2240=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
Line2241=3281\r
-Path2241=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path2241=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line2242=3308\r
-Path2242=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
+Path2242=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_voice.c\r
Line2243=1549\r
-Path2243=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
+Path2243=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
Line2245=2412\r
-Path2245=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
+Path2245=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
Line2246=2442\r
-Path2246=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
+Path2246=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
Line2247=1107\r
-Path2247=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\RF_Tester.c\r
+Path2247=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\RF_Tester.c\r
Line2249=169\r
-Path2249=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
+Path2249=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
Line2249.2=939\r
-Path2249.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
+Path2249.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
Line2250=226\r
-Path2250=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
+Path2250=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
Line2251=289\r
-Path2251=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
+Path2251=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
Line2252=469\r
-Path2252=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
+Path2252=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
Line2254=363\r
-Path2254=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\timer_handler.c\r
+Path2254=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\timer_handler.c\r
Line2256=1417\r
-Path2256=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
+Path2256=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
Line2256.2=1492\r
-Path2256.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
+Path2256.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
Line2256.3=1558\r
-Path2256.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
+Path2256.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
Line2266=357\r
-Path2266=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+Path2266=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
Line2267=1526\r
-Path2267=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+Path2267=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
Line2268=1617\r
-Path2268=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+Path2268=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
Line2278=331\r
-Path2278=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPevt.c\r
+Path2278=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPevt.c\r
Line2278.2=194\r
-Path2278.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
+Path2278.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
Line2279=235\r
-Path2279=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
+Path2279=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
Line2280=811\r
-Path2280=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
+Path2280=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
Line2281=865\r
-Path2281=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
+Path2281=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
Line2282=916\r
-Path2282=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
+Path2282=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
Line2283=935\r
-Path2283=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
+Path2283=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
Line2284=1116\r
-Path2284=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
+Path2284=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
Line2285=1208\r
-Path2285=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
+Path2285=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_e2prom.c\r
Line2286=234\r
-Path2286=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_manager.c\r
+Path2286=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\I2C\i2c_manager.c\r
Line2291=611\r
-Path2291=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path2291=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line2292=1572\r
-Path2292=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path2292=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line2293=1929\r
-Path2293=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path2293=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line2294=2092\r
-Path2294=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
+Path2294=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H5\H5_Protocol.c\r
Line2298=891\r
-Path2298=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path2298=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line2299=2153\r
-Path2299=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
+Path2299=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
Line2299.2=2182\r
-Path2299.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
+Path2299.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
Line2300=110\r
-Path2300=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
+Path2300=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
Line2301=155\r
-Path2301=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
+Path2301=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
Line2302=1316\r
-Path2302=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
+Path2302=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
Line2303=204\r
-Path2303=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\Uart_Hci.c\r
+Path2303=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\Uart_Hci.c\r
Line2303.2=278\r
-Path2303.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\Uart_Hci.c\r
+Path2303.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\Uart_Hci.c\r
Line2304=518\r
-Path2304=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\Uart_Hci.c\r
+Path2304=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\Uart_Hci.c\r
Line2305=523\r
-Path2305=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Buffers\osa_buf.c\r
+Path2305=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Buffers\osa_buf.c\r
Line2306=483\r
-Path2306=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\spi\spi.c\r
+Path2306=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\spi\spi.c\r
Line2307=526\r
-Path2307=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Buffers\osa_buf.c\r
+Path2307=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Buffers\osa_buf.c\r
Line2308=2672\r
-Path2308=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
+Path2308=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_voice.c\r
Line2311=3292\r
-Path2311=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path2311=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line2313=2979\r
-Path2313=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
+Path2313=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acltm.c\r
Line2314=723\r
-Path2314=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
+Path2314=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
Line2315=767\r
-Path2315=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
+Path2315=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
Line2316=684\r
-Path2316=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
+Path2316=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
Line2317=777\r
-Path2317=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
+Path2317=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
Line2318=724\r
-Path2318=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
+Path2318=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Link_Manager.c\r
Line2321=1572\r
-Path2321=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\spi\spi.c\r
+Path2321=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\spi\spi.c\r
Line2322=404\r
-Path2322=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\protocol_utils.c\r
+Path2322=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\protocol_utils.c\r
Line2324=322\r
-Path2324=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\DMA\Dma.c\r
+Path2324=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\DMA\Dma.c\r
Line2325=861\r
-Path2325=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Buffers\osa_buf.c\r
+Path2325=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Buffers\osa_buf.c\r
Line2330=339\r
-Path2330=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
+Path2330=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\Palau_Transport_Utils\Palau_Transport_Utils.c\r
Line2331=2144\r
-Path2331=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
+Path2331=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
Line2335=187\r
-Path2335=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
+Path2335=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
Line2336=353\r
-Path2336=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
+Path2336=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
Line2337=400\r
-Path2337=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
+Path2337=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
Line2338=491\r
-Path2338=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
+Path2338=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
Line2339=294\r
-Path2339=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
+Path2339=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
Line2341=728\r
-Path2341=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
+Path2341=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
Line2342=3332\r
-Path2342=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
+Path2342=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
Line2343=642\r
-Path2343=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
+Path2343=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
Line2344=2281\r
-Path2344=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
+Path2344=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
Line2346=163\r
-Path2346=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicsnd.c\r
+Path2346=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicsnd.c\r
Line2347=200\r
-Path2347=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPevt.c\r
+Path2347=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPevt.c\r
Line2350=169\r
-Path2350=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
+Path2350=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
Line2351=3199\r
-Path2351=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
+Path2351=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
Line2352=1348\r
-Path2352=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path2352=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line2353=1360\r
-Path2353=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path2353=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line2354=1366\r
-Path2354=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path2354=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line2355=1354\r
-Path2355=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path2355=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line2356=4146\r
-Path2356=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicrcv.c\r
+Path2356=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicrcv.c\r
Line2357=861\r
-Path2357=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\protocol_utils.c\r
+Path2357=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\protocol_utils.c\r
Line2363=313\r
-Path2363=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
+Path2363=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
Line2365=269\r
-Path2365=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
+Path2365=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
Line2367=767\r
-Path2367=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Buffers\osa_buf.c\r
+Path2367=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Buffers\osa_buf.c\r
Line2368=68\r
-Path2368=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\basic_services\internal\top_semaphores.c\r
+Path2368=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\basic_services\internal\top_semaphores.c\r
Line2369=2534\r
-Path2369=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
+Path2369=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_VoiceManager.c\r
Line2370=154\r
-Path2370=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff_Subrate.c\r
+Path2370=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff_Subrate.c\r
Line2371=215\r
-Path2371=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff_Subrate.c\r
+Path2371=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff_Subrate.c\r
Line2373=438\r
-Path2373=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
+Path2373=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
Line2374=3944\r
-Path2374=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path2374=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line2374.2=4108\r
-Path2374.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path2374.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line2374.3=4171\r
-Path2374.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path2374.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line2374.4=4212\r
-Path2374.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
+Path2374.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acllmp.c\r
Line2375=498\r
-Path2375=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
+Path2375=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_sniff_subrate.c\r
Line2376=353\r
-Path2376=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
+Path2376=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
Line2377=146\r
-Path2377=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
+Path2377=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\ECDH\ECDHCalculator.c\r
Line2379=183\r
-Path2379=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
+Path2379=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
Line2383=407\r
-Path2383=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
-Line2384=870\r
-Path2384=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line2384.2=525\r
-Path2384.2=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Path2383=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\acl\acl_simple_pair.c\r
+Line2384=525\r
+Path2384=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line2384.2=870\r
+Path2384.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
Line2388=796\r
-Path2388=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
+Path2388=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Synchronizer.c\r
Line2389=765\r
-Path2389=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path2389=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line2390=572\r
-Path2390=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path2390=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line2394=655\r
-Path2394=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
+Path2394=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
Line2395=1879\r
-Path2395=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
+Path2395=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_CmdIF.c\r
Line2396=227\r
-Path2396=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\diamond_post_patch.c\r
+Path2396=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\diamond_post_patch.c\r
Line2400=5059\r
-Path2400=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2400=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2401=669\r
-Path2401=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\basic_services\top_general_1.c\r
+Path2401=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\basic_services\top_general_1.c\r
Line2403=1466\r
-Path2403=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path2403=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line2404=1118\r
-Path2404=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_TOP.c\r
+Path2404=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_TOP.c\r
Line2404.2=1235\r
-Path2404.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_TOP.c\r
+Path2404.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_TOP.c\r
Line2404.3=376\r
-Path2404.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\basic_services\top_general_1.c\r
+Path2404.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\basic_services\top_general_1.c\r
Line2404.4=396\r
-Path2404.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\basic_services\top_general_2.c\r
+Path2404.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\basic_services\top_general_2.c\r
Line2405=1299\r
-Path2405=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path2405=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line2409=285\r
-Path2409=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Mailbox\osa_mailbox.c\r
+Path2409=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Mailbox\osa_mailbox.c\r
Line2413=207\r
-Path2413=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\HostInterface.c\r
+Path2413=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\HostInterface.c\r
Line2414=324\r
-Path2414=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Mailbox\osa_mailbox.c\r
+Path2414=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Mailbox\osa_mailbox.c\r
Line2415=385\r
-Path2415=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Mailbox\osa_mailbox.c\r
+Path2415=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Mailbox\osa_mailbox.c\r
Line2416=1278\r
-Path2416=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
+Path2416=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
Line2417=1919\r
-Path2417=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
+Path2417=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
Line2418=757\r
-Path2418=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_main.c\r
+Path2418=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_main.c\r
Line2419=1600\r
-Path2419=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lower_mac_interface.c\r
+Path2419=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lower_mac_interface.c\r
Line2420=1066\r
-Path2420=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lower_mac_interface.c\r
+Path2420=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lower_mac_interface.c\r
Line2421=802\r
-Path2421=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2421=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2422=982\r
-Path2422=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lower_mac_interface.c\r
+Path2422=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lower_mac_interface.c\r
Line2423=1100\r
-Path2423=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+Path2423=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
Line2424=986\r
-Path2424=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lower_mac_interface.c\r
+Path2424=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lower_mac_interface.c\r
Line2425=1081\r
-Path2425=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\basic_services\top_general_1.c\r
+Path2425=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\basic_services\top_general_1.c\r
Line2425.2=1228\r
-Path2425.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\basic_services\top_general_1.c\r
+Path2425.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\basic_services\top_general_1.c\r
Line2426=1849\r
-Path2426=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path2426=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line2427=616\r
-Path2427=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path2427=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line2428=790\r
-Path2428=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
+Path2428=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
Line2428.2=1276\r
-Path2428.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
+Path2428.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_avpr.c\r
Line2429=880\r
-Path2429=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
+Path2429=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
Line2430=149\r
-Path2430=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\transport_detection\Transport_Detection.c\r
+Path2430=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\transport_detection\Transport_Detection.c\r
Line2431=198\r
-Path2431=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_buffer.c\r
+Path2431=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_buffer.c\r
Line2432=150\r
-Path2432=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_buffer.c\r
+Path2432=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_buffer.c\r
Line2433=1474\r
-Path2433=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
+Path2433=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
Line2434=128\r
-Path2434=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicsnd.c\r
+Path2434=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcic\hcicsnd.c\r
Line2435=1072\r
-Path2435=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lower_mac_interface.c\r
+Path2435=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lower_mac_interface.c\r
Line2436=445\r
-Path2436=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connect.c\r
+Path2436=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connect.c\r
Line2437=5014\r
-Path2437=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path2437=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line2438=4996\r
-Path2438=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path2438=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line2439=5020\r
-Path2439=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path2439=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line2440=1908\r
-Path2440=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\drpb.c\r
+Path2440=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\drpb.c\r
Line2441=2170\r
-Path2441=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
+Path2441=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
Line2442=5005\r
-Path2442=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path2442=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line2443=2239\r
-Path2443=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
+Path2443=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
Line2543=1789\r
-Path2543=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2543=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2544=1359\r
-Path2544=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2544=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2545=1361\r
-Path2545=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2545=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2546=1366\r
-Path2546=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2546=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2547=1370\r
-Path2547=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2547=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2548=961\r
-Path2548=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2548=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2549=778\r
-Path2549=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2549=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2549.2=914\r
-Path2549.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2549.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2549.3=979\r
-Path2549.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2549.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2549.4=1034\r
-Path2549.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2549.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2551=364\r
-Path2551=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2551=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2552=3871\r
-Path2552=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path2552=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line2553=227\r
-Path2553=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2553=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2553.2=247\r
-Path2553.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2553.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2553.3=267\r
-Path2553.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2553.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2553.4=285\r
-Path2553.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2553.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2555=1484\r
-Path2555=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+Path2555=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
Line2556=230\r
-Path2556=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
+Path2556=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
Line2557=1256\r
-Path2557=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2557=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2558=842\r
-Path2558=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lower_mac_interface.c\r
+Path2558=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lower_mac_interface.c\r
Line2559=1406\r
-Path2559=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connect.c\r
+Path2559=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connect.c\r
Line2561=651\r
-Path2561=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connect.c\r
+Path2561=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connect.c\r
Line2562=1046\r
-Path2562=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+Path2562=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
Line2564=1075\r
-Path2564=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path2564=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line2565=95\r
-Path2565=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_activity.c\r
+Path2565=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_activity.c\r
Line2565.2=148\r
-Path2565.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_activity.c\r
+Path2565.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_activity.c\r
Line2567=1884\r
-Path2567=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path2567=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line2568=2140\r
-Path2568=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path2568=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line2569=2092\r
-Path2569=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path2569=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line2570=126\r
-Path2570=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+Path2570=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
Line2571=995\r
-Path2571=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path2571=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line2572=148\r
-Path2572=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+Path2572=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
Line2573=980\r
-Path2573=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+Path2573=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
Line2575=1272\r
-Path2575=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+Path2575=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
Line2576=1277\r
-Path2576=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+Path2576=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
Line2577=687\r
-Path2577=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+Path2577=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
Line2578=712\r
-Path2578=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+Path2578=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
Line2580=877\r
-Path2580=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
+Path2580=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
Line2580.2=907\r
-Path2580.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
+Path2580.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
Line2581=1485\r
-Path2581=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connect.c\r
+Path2581=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connect.c\r
Line2582=1943\r
-Path2582=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path2582=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line2602=507\r
-Path2602=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+Path2602=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
Line2603=6048\r
-Path2603=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2603=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2604=2189\r
-Path2604=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2604=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2606=1983\r
-Path2606=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2606=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2614=1729\r
-Path2614=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2614=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2615=1993\r
-Path2615=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2615=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2616=497\r
-Path2616=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
+Path2616=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
Line2617=5878\r
-Path2617=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2617=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2618=1969\r
-Path2618=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2618=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2619=429\r
-Path2619=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
+Path2619=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
Line2620=463\r
-Path2620=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
+Path2620=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
Line2624=3570\r
-Path2624=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2624=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2625=3589\r
-Path2625=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2625=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2626=3689\r
-Path2626=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2626=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2627=567\r
-Path2627=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_main.c\r
+Path2627=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_main.c\r
Line2628=3355\r
-Path2628=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2628=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2628.2=4481\r
-Path2628.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2628.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2633=3382\r
-Path2633=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2633=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2633.2=4507\r
-Path2633.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2633.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2634=229\r
-Path2634=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
+Path2634=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
Line2641=5724\r
-Path2641=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2641=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2643=604\r
-Path2643=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
+Path2643=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
Line2645=1124\r
-Path2645=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
+Path2645=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
Line2648=1001\r
-Path2648=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
+Path2648=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
Line2649=1097\r
-Path2649=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
+Path2649=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
Line2651=5705\r
-Path2651=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2651=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2656=1915\r
-Path2656=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2656=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2665=1572\r
-Path2665=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path2665=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line2666=1681\r
-Path2666=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path2666=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line2669=2015\r
-Path2669=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_BT.c\r
+Path2669=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_BT.c\r
Line2670=2022\r
-Path2670=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_BT.c\r
+Path2670=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_BT.c\r
Line2671=2031\r
-Path2671=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_BT.c\r
+Path2671=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd_BT.c\r
Line2672=1348\r
-Path2672=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path2672=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line2682=802\r
-Path2682=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_activity_core.c\r
+Path2682=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_activity_core.c\r
Line2682.2=1385\r
-Path2682.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_activity_core.c\r
+Path2682.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_activity_core.c\r
Line2682.3=1024\r
-Path2682.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
+Path2682.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
Line2682.4=1814\r
-Path2682.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path2682.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line2682.5=1924\r
-Path2682.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path2682.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line2682.6=1162\r
-Path2682.6=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+Path2682.6=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
Line2686=313\r
-Path2686=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
+Path2686=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
Line2687=169\r
-Path2687=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_protocol_utils.c\r
+Path2687=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_protocol_utils.c\r
Line2689=1273\r
-Path2689=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_activity_core.c\r
+Path2689=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_activity_core.c\r
Line2690=1341\r
-Path2690=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2690=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2690.2=1938\r
-Path2690.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2690.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2692=4076\r
-Path2692=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2692=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2696=666\r
-Path2696=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
+Path2696=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
Line2697=440\r
-Path2697=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path2697=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line2698=784\r
-Path2698=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_advertise.c\r
+Path2698=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_advertise.c\r
Line2699=617\r
-Path2699=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
+Path2699=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
Line2699.2=631\r
-Path2699.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
+Path2699.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
Line2701=4103\r
-Path2701=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2701=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2701.2=4243\r
-Path2701.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2701.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2710=565\r
-Path2710=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2710=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2711=794\r
-Path2711=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2711=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2712=732\r
-Path2712=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2712=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2713=790\r
-Path2713=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2713=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2714=4131\r
-Path2714=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2714=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2717=208\r
-Path2717=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection_manager.c\r
+Path2717=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection_manager.c\r
Line2718=226\r
-Path2718=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection_manager.c\r
+Path2718=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection_manager.c\r
Line2720=4168\r
-Path2720=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2720=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2721=4208\r
-Path2721=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2721=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2722=2526\r
-Path2722=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2722=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2726=178\r
-Path2726=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path2726=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line2737=3829\r
-Path2737=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2737=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2738=2753\r
-Path2738=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2738=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2739=4277\r
-Path2739=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2739=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2740=3204\r
-Path2740=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2740=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2741=2920\r
-Path2741=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2741=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2741.2=3977\r
-Path2741.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2741.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2742=4303\r
-Path2742=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2742=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2743=3834\r
-Path2743=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2743=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2743.2=3840\r
-Path2743.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2743.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2744=1486\r
-Path2744=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_advertise.c\r
+Path2744=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_advertise.c\r
Line2745=1196\r
-Path2745=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2745=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2748=2052\r
-Path2748=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2748=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2749=4359\r
-Path2749=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2749=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2750=5650\r
-Path2750=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2750=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2751=2897\r
-Path2751=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2751=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2751.2=3909\r
-Path2751.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2751.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2752=2721\r
-Path2752=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2752=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2753=3794\r
-Path2753=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2753=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2754=3210\r
-Path2754=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2754=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2756=3021\r
-Path2756=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2756=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2757=2974\r
-Path2757=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2757=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2757.2=3991\r
-Path2757.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2757.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2758=2981\r
-Path2758=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2758=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2758.2=4010\r
-Path2758.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2758.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2759=4028\r
-Path2759=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2759=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2761=578\r
-Path2761=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_main.c\r
+Path2761=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_main.c\r
Line2762=585\r
-Path2762=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_main.c\r
+Path2762=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_main.c\r
Line2765=1406\r
-Path2765=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2765=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2766=3115\r
-Path2766=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2766=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2768=3090\r
-Path2768=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2768=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2769=3155\r
-Path2769=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2769=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2771=2825\r
-Path2771=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2771=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2772=4143\r
-Path2772=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2772=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2773=3867\r
-Path2773=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2773=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2777=3873\r
-Path2777=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2777=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2779=1561\r
-Path2779=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lower_mac_interface.c\r
+Path2779=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lower_mac_interface.c\r
Line2780=1151\r
-Path2780=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lower_mac_interface.c\r
+Path2780=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lower_mac_interface.c\r
Line2781=1387\r
-Path2781=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lower_mac_interface.c\r
+Path2781=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lower_mac_interface.c\r
Line2783=2848\r
-Path2783=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2783=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2784=3944\r
-Path2784=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2784=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2785=397\r
-Path2785=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2785=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2785.2=433\r
-Path2785.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path2785.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line2786=1893\r
-Path2786=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path2786=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line2787=1886\r
-Path2787=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
+Path2787=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\HCIPP\HCIPPcmd.c\r
Line2788=2537\r
-Path2788=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2788=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2789=1987\r
-Path2789=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path2789=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line2800=167\r
-Path2800=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_init.c\r
+Path2800=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_init.c\r
Line2800.2=178\r
-Path2800.2=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations_FPGA\drpb_init.c\r
+Path2800.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations_FPGA\drpb_init.c\r
Line2801=63\r
-Path2801=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\calibration_start.c\r
+Path2801=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\calibration_start.c\r
Line2802=155\r
-Path2802=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations_FPGA\drpb_coarse_open_loop_calibration.c\r
+Path2802=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations_FPGA\drpb_coarse_open_loop_calibration.c\r
Line2803=159\r
-Path2803=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations_FPGA\drpb_coarse_open_loop_calibration.c\r
+Path2803=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations_FPGA\drpb_coarse_open_loop_calibration.c\r
Line2804=186\r
-Path2804=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations_FPGA\drpb_kdco_calibration.c\r
+Path2804=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations_FPGA\drpb_kdco_calibration.c\r
Line2806=108\r
-Path2806=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_coarse_open_loop_calibration.c\r
+Path2806=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_coarse_open_loop_calibration.c\r
Line2807=160\r
-Path2807=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_coarse_open_loop_calibration.c\r
+Path2807=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_coarse_open_loop_calibration.c\r
Line2813=396\r
-Path2813=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_dc_calibration.c\r
+Path2813=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_dc_calibration.c\r
Line2814=326\r
-Path2814=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_ifa_pole_calibration.c\r
+Path2814=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_ifa_pole_calibration.c\r
Line2815=194\r
-Path2815=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_coarse_open_loop_calibration.c\r
+Path2815=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_coarse_open_loop_calibration.c\r
Line2816=198\r
-Path2816=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_coarse_open_loop_calibration.c\r
+Path2816=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_coarse_open_loop_calibration.c\r
Line2820=85\r
-Path2820=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_generate_random_number_calibration.c\r
+Path2820=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_generate_random_number_calibration.c\r
Line2820.2=715\r
-Path2820.2=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations_FPGA\drpb_init.c\r
+Path2820.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations_FPGA\drpb_init.c\r
Line2821=141\r
-Path2821=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_kdco_calibration.c\r
+Path2821=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_kdco_calibration.c\r
Line2822=142\r
-Path2822=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_kdco_calibration.c\r
+Path2822=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_kdco_calibration.c\r
Line2825=239\r
-Path2825=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_dc_calibration.c\r
+Path2825=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_dc_calibration.c\r
Line2828=64\r
-Path2828=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_PD_extract_calibration.c\r
+Path2828=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_PD_extract_calibration.c\r
Line2829=432\r
-Path2829=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_ifa_pole_calibration.c\r
+Path2829=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_ifa_pole_calibration.c\r
Line2831=379\r
-Path2831=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_temperature_change.c\r
+Path2831=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_temperature_change.c\r
Line2832=86\r
-Path2832=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_ldo_calibration.c\r
+Path2832=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_ldo_calibration.c\r
Line2833=448\r
-Path2833=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\utils\phy_utils.c\r
+Path2833=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\utils\phy_utils.c\r
Line2834=94\r
-Path2834=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_script_timing_calibration.c\r
+Path2834=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_script_timing_calibration.c\r
Line2835=138\r
-Path2835=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_script_timing_calibration.c\r
+Path2835=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_script_timing_calibration.c\r
Line2837=577\r
-Path2837=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\main\phy_fw_main.c\r
+Path2837=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\main\phy_fw_main.c\r
Line2838=605\r
-Path2838=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\main\phy_fw_main.c\r
+Path2838=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\main\phy_fw_main.c\r
Line2841=778\r
-Path2841=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\tx_start.c\r
+Path2841=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\tx_start.c\r
Line2842=1192\r
-Path2842=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
+Path2842=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
Line2843=545\r
-Path2843=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\main\phy_fw_main.c\r
+Path2843=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\main\phy_fw_main.c\r
Line2844=647\r
-Path2844=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\main\phy_fw_main.c\r
+Path2844=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\main\phy_fw_main.c\r
Line2845=1901\r
-Path2845=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
+Path2845=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
Line2846=2053\r
-Path2846=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
+Path2846=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
Line2847=710\r
-Path2847=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\main\phy_fw_main.c\r
+Path2847=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\main\phy_fw_main.c\r
Line2848=719\r
-Path2848=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\main\phy_fw_main.c\r
+Path2848=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\main\phy_fw_main.c\r
Line2849=728\r
-Path2849=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\main\phy_fw_main.c\r
+Path2849=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\main\phy_fw_main.c\r
Line2850=742\r
-Path2850=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\main\phy_fw_main.c\r
+Path2850=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\main\phy_fw_main.c\r
Line2851=756\r
-Path2851=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\main\phy_fw_main.c\r
+Path2851=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\main\phy_fw_main.c\r
Line2852=97\r
-Path2852=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\power_save.c\r
+Path2852=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\power_save.c\r
Line2853=139\r
-Path2853=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\power_save.c\r
+Path2853=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\power_save.c\r
Line2854=111\r
-Path2854=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\power_save.c\r
+Path2854=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\power_save.c\r
Line2855=153\r
-Path2855=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\power_save.c\r
+Path2855=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\power_save.c\r
Line2856=172\r
-Path2856=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_clock_dependent_calc.c\r
+Path2856=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_clock_dependent_calc.c\r
Line2857=1239\r
-Path2857=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
+Path2857=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
Line2858=1250\r
-Path2858=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
+Path2858=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
Line2859=171\r
-Path2859=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_kdco_calibration.c\r
+Path2859=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_kdco_calibration.c\r
Line2860=401\r
-Path2860=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_dc_calibration.c\r
+Path2860=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_dc_calibration.c\r
Line2861=406\r
-Path2861=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_dc_calibration.c\r
+Path2861=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_dc_calibration.c\r
Line2862=1894\r
-Path2862=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\utils\rf_sub_functions.c\r
+Path2862=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\utils\rf_sub_functions.c\r
Line2863=166\r
-Path2863=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_ldo_calibration.c\r
+Path2863=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_ldo_calibration.c\r
Line2863.2=170\r
-Path2863.2=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_ldo_calibration.c\r
+Path2863.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_ldo_calibration.c\r
Line2864=135\r
-Path2864=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_ldo_calibration.c\r
+Path2864=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_ldo_calibration.c\r
Line2865=50\r
-Path2865=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\calibration_start.c\r
+Path2865=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\calibration_start.c\r
Line2866=206\r
-Path2866=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_init.c\r
+Path2866=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_init.c\r
Line2867=307\r
-Path2867=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\afh.c\r
+Path2867=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\afh.c\r
Line2868=34\r
-Path2868=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\calibration_stop.c\r
+Path2868=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\calibration_stop.c\r
Line2869=23\r
-Path2869=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\calibration_stop.c\r
+Path2869=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\calibration_stop.c\r
Line2870=44\r
-Path2870=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\calibration_stop.c\r
+Path2870=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\calibration_stop.c\r
Line2871=39\r
-Path2871=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\calibration_stop.c\r
+Path2871=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\calibration_stop.c\r
Line2872=825\r
-Path2872=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\main\phy_fw_main.c\r
+Path2872=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\main\phy_fw_main.c\r
Line2873=371\r
-Path2873=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
+Path2873=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
Line2874=155\r
-Path2874=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\tx_start.c\r
+Path2874=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\tx_start.c\r
Line2875=77\r
-Path2875=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\lps.c\r
+Path2875=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\lps.c\r
Line2876=287\r
-Path2876=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\afh.c\r
+Path2876=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\afh.c\r
Line2877=34\r
-Path2877=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\power_save.c\r
+Path2877=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\power_save.c\r
Line2878=806\r
-Path2878=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\afh.c\r
+Path2878=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\afh.c\r
Line2879=34\r
-Path2879=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\tx_stop.c\r
+Path2879=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\tx_stop.c\r
Line2881=96\r
-Path2881=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_stop.c\r
+Path2881=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_stop.c\r
Line2882=486\r
-Path2882=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\lps.c\r
+Path2882=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\lps.c\r
Line2883=318\r
-Path2883=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\afh.c\r
+Path2883=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\afh.c\r
Line2884=216\r
-Path2884=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\power_save.c\r
+Path2884=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\power_save.c\r
Line2885=896\r
-Path2885=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\afh.c\r
+Path2885=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\afh.c\r
Line2886=154\r
-Path2886=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_script_timing_calibration.c\r
+Path2886=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_script_timing_calibration.c\r
Line2887=1285\r
-Path2887=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
+Path2887=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
Line2887.2=821\r
-Path2887.2=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\tx_start.c\r
+Path2887.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\tx_start.c\r
Line2888=1577\r
-Path2888=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
+Path2888=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
Line2888.2=1027\r
-Path2888.2=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\tx_start.c\r
+Path2888.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\tx_start.c\r
Line2889=1346\r
-Path2889=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
+Path2889=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
Line2889.2=906\r
-Path2889.2=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\tx_start.c\r
+Path2889.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\tx_start.c\r
Line2890=106\r
-Path2890=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_dco_oslo_tank_tune_calibration.c\r
+Path2890=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_dco_oslo_tank_tune_calibration.c\r
Line2891=134\r
-Path2891=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_dco_oslo_tank_tune_calibration.c\r
+Path2891=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_dco_oslo_tank_tune_calibration.c\r
Line2892=204\r
-Path2892=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_ldo_calibration.c\r
+Path2892=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\calibrations\drpb_ldo_calibration.c\r
Line2893=860\r
-Path2893=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\afh.c\r
+Path2893=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\afh.c\r
Line2894=859\r
-Path2894=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\afh.c\r
+Path2894=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\afh.c\r
Line2895=2202\r
-Path2895=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
+Path2895=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
Line2896=857\r
-Path2896=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\afh.c\r
+Path2896=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\afh.c\r
Line2897=309\r
-Path2897=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
+Path2897=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
Line2898=263\r
-Path2898=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
+Path2898=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
Line2899=267\r
-Path2899=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
+Path2899=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\scripts\rx_start.c\r
Line2901=173\r
-Path2901=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_01.c\r
+Path2901=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_01.c\r
Line2901.2=192\r
-Path2901.2=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_01.c\r
+Path2901.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_01.c\r
Line2901.3=1250\r
-Path2901.3=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2901.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2901.4=1269\r
-Path2901.4=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2901.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2902=134\r
-Path2902=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2902=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2903=133\r
-Path2903=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_04.c\r
+Path2903=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_04.c\r
Line2903.2=1656\r
-Path2903.2=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2903.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2904=143\r
-Path2904=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_13.c\r
+Path2904=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_13.c\r
Line2904.2=182\r
-Path2904.2=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_13.c\r
+Path2904.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_13.c\r
Line2904.3=230\r
-Path2904.3=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_13.c\r
+Path2904.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_13.c\r
Line2904.4=274\r
-Path2904.4=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_13.c\r
+Path2904.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_13.c\r
Line2904.5=2310\r
-Path2904.5=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2904.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2904.6=2349\r
-Path2904.6=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2904.6=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2904.7=2397\r
-Path2904.7=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2904.7=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2904.8=2441\r
-Path2904.8=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2904.8=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2905=200\r
-Path2905=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_01.c\r
+Path2905=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_01.c\r
Line2905.2=1277\r
-Path2905.2=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2905.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2907=156\r
-Path2907=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_10.c\r
+Path2907=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_10.c\r
Line2908=507\r
-Path2908=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2908=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2908.2=553\r
-Path2908.2=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2908.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2908.3=582\r
-Path2908.3=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2908.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2908.4=632\r
-Path2908.4=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2908.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2908.5=689\r
-Path2908.5=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2908.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2909=89\r
-Path2909=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_14.c\r
+Path2909=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_14.c\r
Line2910=79\r
-Path2910=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_10.c\r
+Path2910=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_10.c\r
Line2911=129\r
-Path2911=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_11.c\r
+Path2911=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_11.c\r
Line2911.2=2057\r
-Path2911.2=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2911.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2912=135\r
-Path2912=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_12.c\r
+Path2912=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_12.c\r
Line2912.2=2197\r
-Path2912.2=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2912.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2913=429\r
-Path2913=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_13.c\r
+Path2913=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_13.c\r
Line2913.2=435\r
-Path2913.2=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_13.c\r
+Path2913.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_13.c\r
Line2913.3=2596\r
-Path2913.3=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2913.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2913.4=2602\r
-Path2913.4=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2913.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2914=140\r
-Path2914=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_14.c\r
+Path2914=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_14.c\r
Line2915=220\r
-Path2915=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_02.c\r
+Path2915=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_02.c\r
Line2915.2=1512\r
-Path2915.2=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2915.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2916=149\r
-Path2916=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_04.c\r
+Path2916=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_04.c\r
Line2916.2=1672\r
-Path2916.2=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2916.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2917=88\r
-Path2917=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_09.c\r
+Path2917=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_09.c\r
Line2917.2=1941\r
-Path2917.2=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2917.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2918=1022\r
-Path2918=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2918=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2919=243\r
-Path2919=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_08.c\r
+Path2919=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_08.c\r
Line2919.2=2818\r
-Path2919.2=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2919.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2920=141\r
-Path2920=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_11.c\r
+Path2920=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_11.c\r
Line2920.2=2069\r
-Path2920.2=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2920.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2921=130\r
-Path2921=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_14.c\r
+Path2921=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_14.c\r
Line2925=165\r
-Path2925=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_07.c\r
+Path2925=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_07.c\r
Line2925.2=1833\r
-Path2925.2=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2925.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2926=187\r
-Path2926=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_07.c\r
+Path2926=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_07.c\r
Line2926.2=1855\r
-Path2926.2=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
+Path2926.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit_utils\Orbit_main_and_sub_function.c\r
Line2927=239\r
-Path2927=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_06.c\r
+Path2927=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_06.c\r
Line2928=240\r
-Path2928=M:\Omri_WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_06.c\r
+Path2928=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\PHY_FW\orbit\orbit_06.c\r
Line3001=504\r
-Path3001=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3001=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3002=572\r
-Path3002=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3002=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3003=639\r
-Path3003=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3003=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3004=775\r
-Path3004=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3004=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3005=846\r
-Path3005=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3005=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3006=1000\r
-Path3006=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3006=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3008=590\r
-Path3008=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3008=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3009=776\r
-Path3009=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3009=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3010=772\r
-Path3010=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3010=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3012=774\r
-Path3012=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3012=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3013=973\r
-Path3013=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3013=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3014=812\r
-Path3014=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3014=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3016=773\r
-Path3016=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3016=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3020=1142\r
-Path3020=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3020=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3021=815\r
-Path3021=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3021=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3022=1759\r
-Path3022=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3022=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3023=1058\r
-Path3023=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3023=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3026=1412\r
-Path3026=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3026=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3027=1780\r
-Path3027=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3027=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3028=1812\r
-Path3028=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3028=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3029=1813\r
-Path3029=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3029=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3030=1814\r
-Path3030=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3030=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3031=1815\r
-Path3031=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3031=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3032=1816\r
-Path3032=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3032=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3035=145\r
-Path3035=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
+Path3035=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
Line3036=147\r
-Path3036=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
+Path3036=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
Line3037=151\r
-Path3037=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
+Path3037=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
Line3038=156\r
-Path3038=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
+Path3038=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
Line3039=161\r
-Path3039=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
-Line3043=165\r
-Path3043=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_hooks.c\r
-Line3043.2=172\r
-Path3043.2=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_hooks.c\r
+Path3039=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
+Line3043=155\r
+Path3043=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_hooks.c\r
Line3045=126\r
-Path3045=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_patches_ram.c\r
+Path3045=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_patches_ram.c\r
Line3046=130\r
-Path3046=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_patches_ram.c\r
+Path3046=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_patches_ram.c\r
Line3047=134\r
-Path3047=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_patches_ram.c\r
+Path3047=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_patches_ram.c\r
Line3048=209\r
-Path3048=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_patches_ram.c\r
+Path3048=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_patches_ram.c\r
Line3048.2=251\r
-Path3048.2=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_patches_ram.c\r
+Path3048.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_patches_ram.c\r
Line3051=162\r
-Path3051=M:\Omri_WPAN_45nm_FW_4_SP\ti\patches_shared\patches_shared_rom.c\r
+Path3051=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\patches_shared\patches_shared_rom.c\r
Line3100=70\r
-Path3100=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\control_path\avpr_upper_mac_interface.c\r
+Path3100=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\control_path\avpr_upper_mac_interface.c\r
Line3101=168\r
-Path3101=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\control_path\avpr_upper_mac_interface.c\r
+Path3101=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\control_path\avpr_upper_mac_interface.c\r
Line3102=82\r
-Path3102=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\peripherals\avpr_dma.c\r
+Path3102=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\peripherals\avpr_dma.c\r
Line3114=628\r
-Path3114=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
+Path3114=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
Line3114.2=940\r
-Path3114.2=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
+Path3114.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
Line3115=478\r
-Path3115=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
+Path3115=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
Line3117=168\r
-Path3117=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_main.c\r
+Path3117=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_main.c\r
Line3118=164\r
-Path3118=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\control_path\avpr_upper_mac_interface.c\r
+Path3118=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\control_path\avpr_upper_mac_interface.c\r
Line3119=555\r
-Path3119=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
+Path3119=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
Line3120=122\r
-Path3120=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\peripherals\avpr_pcmi_drv.c\r
+Path3120=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\peripherals\avpr_pcmi_drv.c\r
Line3139=49\r
-Path3139=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\peripherals\avpr_dma.c\r
+Path3139=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\peripherals\avpr_dma.c\r
Line3140=338\r
-Path3140=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_patches_ram.c\r
+Path3140=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_patches_ram.c\r
Line3140.2=354\r
-Path3140.2=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_patches_ram.c\r
+Path3140.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_patches_ram.c\r
Line3143=716\r
-Path3143=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
+Path3143=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
Line3144=826\r
-Path3144=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
+Path3144=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
Line3145=655\r
-Path3145=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
+Path3145=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
Line3146=948\r
-Path3146=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
+Path3146=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
Line3159=650\r
-Path3159=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
+Path3159=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
Line3190=2062\r
-Path3190=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\sbc\sbc.c\r
+Path3190=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\sbc\sbc.c\r
Line3191=2075\r
-Path3191=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\sbc\sbc.c\r
+Path3191=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\sbc\sbc.c\r
Line3192=2097\r
-Path3192=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\sbc\sbc.c\r
+Path3192=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\sbc\sbc.c\r
Line3200=124\r
-Path3200=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\fm\avpr_fm.c\r
+Path3200=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\fm\avpr_fm.c\r
Line3201=216\r
-Path3201=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\fm\avpr_fm.c\r
+Path3201=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\fm\avpr_fm.c\r
Line3202=203\r
-Path3202=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\fm\avpr_fm.c\r
+Path3202=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\fm\avpr_fm.c\r
Line3204=76\r
-Path3204=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\fm\avpr_fm.c\r
+Path3204=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\fm\avpr_fm.c\r
Line3205=168\r
-Path3205=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\filters\avpr_plc.c\r
+Path3205=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\filters\avpr_plc.c\r
Line3206=445\r
-Path3206=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_patches_ram.c\r
+Path3206=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_patches_ram.c\r
Line3228=390\r
-Path3228=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
+Path3228=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
Line3230=492\r
-Path3230=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
+Path3230=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
Line3231=143\r
-Path3231=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
+Path3231=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
Line3232=158\r
-Path3232=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\util\avpr_utils.h\r
+Path3232=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\util\avpr_utils.h\r
Line3233=184\r
-Path3233=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
+Path3233=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
Line3234=113\r
-Path3234=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\cvsd\avpr_cvsd.c\r
+Path3234=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\cvsd\avpr_cvsd.c\r
Line3235=200\r
-Path3235=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\cvsd\avpr_cvsd.c\r
+Path3235=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\cvsd\avpr_cvsd.c\r
Line3236=272\r
-Path3236=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\cvsd\avpr_cvsd.c\r
+Path3236=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\cvsd\avpr_cvsd.c\r
Line3237=331\r
-Path3237=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\cvsd\avpr_cvsd.c\r
+Path3237=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\cvsd\avpr_cvsd.c\r
Line3238=497\r
-Path3238=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\cvsd\avpr_cvsd.c\r
+Path3238=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\cvsd\avpr_cvsd.c\r
Line3253=141\r
-Path3253=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
+Path3253=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
Line3254=105\r
-Path3254=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\rate_convertor\avpr_8_16_convertor.c\r
-Line3255=566\r
-Path3255=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
-Line3255.2=516\r
-Path3255.2=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\rate_convertor\avpr_8_16_convertor.c\r
+Path3254=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\rate_convertor\avpr_8_16_convertor.c\r
+Line3255=516\r
+Path3255=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\rate_convertor\avpr_8_16_convertor.c\r
+Line3255.2=566\r
+Path3255.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
Line3256=369\r
-Path3256=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
+Path3256=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
Line3257=401\r
-Path3257=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
+Path3257=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\wbs\wbs.c\r
Line3300=267\r
-Path3300=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3300=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3301=159\r
-Path3301=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\util\avpr_utils.h\r
+Path3301=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\util\avpr_utils.h\r
Line3301.2=162\r
-Path3301.2=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\util\avpr_utils.h\r
+Path3301.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\util\avpr_utils.h\r
Line3302=408\r
-Path3302=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3302=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3302.2=574\r
-Path3302.2=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3302.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3303=409\r
-Path3303=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3303=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3303.2=575\r
-Path3303.2=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3303.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3304=410\r
-Path3304=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3304=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3304.2=576\r
-Path3304.2=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3304.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3305=411\r
-Path3305=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3305=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3305.2=577\r
-Path3305.2=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3305.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3308=320\r
-Path3308=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3308=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3309=439\r
-Path3309=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_patches_ram.c\r
+Path3309=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_patches\avpr_patches_ram.c\r
Line3310=641\r
-Path3310=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3310=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3311=375\r
-Path3311=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3311=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3313=1792\r
-Path3313=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path3313=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line3314=1793\r
-Path3314=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path3314=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line3315=353\r
-Path3315=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\util\avpr_utils.c\r
+Path3315=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\util\avpr_utils.c\r
Line3316=759\r
-Path3316=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3316=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3318=750\r
-Path3318=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3318=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3320=1414\r
-Path3320=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path3320=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line3321=783\r
-Path3321=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3321=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3322=1794\r
-Path3322=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path3322=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line3323=1732\r
-Path3323=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
+Path3323=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\AVPR\main_mcu_a3dp.c\r
Line3324=362\r
-Path3324=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\util\avpr_utils.c\r
+Path3324=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\util\avpr_utils.c\r
Line3325=194\r
-Path3325=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\rate_convertor\avpr_8_16_convertor.c\r
+Path3325=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\rate_convertor\avpr_8_16_convertor.c\r
Line3327=275\r
-Path3327=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\rate_convertor\avpr_8_16_convertor.c\r
+Path3327=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\rate_convertor\avpr_8_16_convertor.c\r
Line3328=333\r
-Path3328=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\rate_convertor\avpr_8_16_convertor.c\r
+Path3328=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\rate_convertor\avpr_8_16_convertor.c\r
Line3329=169\r
-Path3329=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
+Path3329=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
Line3330=543\r
-Path3330=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3330=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3331=544\r
-Path3331=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3331=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3332=545\r
-Path3332=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3332=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3333=546\r
-Path3333=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3333=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3334=547\r
-Path3334=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3334=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3400=447\r
-Path3400=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\peripherals\avpr_pcmi_drv.c\r
+Path3400=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\peripherals\avpr_pcmi_drv.c\r
Line3401=482\r
-Path3401=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\peripherals\avpr_pcmi_drv.c\r
+Path3401=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\peripherals\avpr_pcmi_drv.c\r
Line3402=1111\r
-Path3402=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3402=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3403=1114\r
-Path3403=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
+Path3403=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp.c\r
Line3404=961\r
-Path3404=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3404=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3405=965\r
-Path3405=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3405=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3406=745\r
-Path3406=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3406=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3407=880\r
-Path3407=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3407=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3408=1025\r
-Path3408=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3408=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3409=1028\r
-Path3409=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3409=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3410=323\r
-Path3410=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
+Path3410=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
Line3411=856\r
-Path3411=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3411=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3412=477\r
-Path3412=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
+Path3412=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\a3dp\avpr_a3dp_snk.c\r
Line3413=365\r
-Path3413=M:\Omri_WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
+Path3413=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\AVPR_FW\proj\avpr_interrupt_handler.c\r
Line3501=335\r
-Path3501=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\gps_shared_interface.c\r
+Path3501=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\gps_shared_interface.c\r
Line3503=203\r
-Path3503=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\gps_shared_interface.c\r
+Path3503=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\gps_shared_interface.c\r
Line3512=400\r
-Path3512=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\gps_shared_interface.c\r
-Line3584=422\r
-Path3584=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
-Line3584.2=366\r
-Path3584.2=M:\Omri_WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Path3512=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\gps_shared_interface.c\r
+Line3584=366\r
+Path3584=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\sw_compiler\make\ti_make-3.81_view\main.c\r
+Line3584.2=422\r
+Path3584.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\Main.c\r
Line3585=1131\r
-Path3585=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+Path3585=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
Line3586=3147\r
-Path3586=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
+Path3586=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
Line3588=1972\r
-Path3588=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lower_mac_interface.c\r
+Path3588=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lower_mac_interface.c\r
Line3596=4344\r
-Path3596=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
+Path3596=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\control\lm_afh.c\r
Line3597=412\r
-Path3597=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\gps_shared_interface.c\r
+Path3597=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\gps_shared_interface.c\r
Line3597.2=413\r
-Path3597.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\gps_shared_interface.c\r
+Path3597.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\gps_shared_interface.c\r
Line3597.3=414\r
-Path3597.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\gps_shared_interface.c\r
+Path3597.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\gps_shared_interface.c\r
Line3597.4=415\r
-Path3597.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\gps_shared_interface.c\r
+Path3597.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\gps_shared_interface.c\r
Line3597.5=893\r
-Path3597.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\protocol_utils.c\r
+Path3597.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\protocol_utils.c\r
Line3598=411\r
-Path3598=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\gps_shared_interface.c\r
+Path3598=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\shared_interfaces\gps_shared_interface.c\r
Line3599=892\r
-Path3599=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\protocol_utils.c\r
+Path3599=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\protocol_utils.c\r
Line3600=434\r
-Path3600=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_scan.c\r
+Path3600=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_scan.c\r
Line3601=460\r
-Path3601=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_scan.c\r
+Path3601=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_scan.c\r
Line3602=773\r
-Path3602=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connect.c\r
+Path3602=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connect.c\r
Line3603=799\r
-Path3603=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connect.c\r
+Path3603=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connect.c\r
Line3604=834\r
-Path3604=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_scan.c\r
+Path3604=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_scan.c\r
Line3605=1221\r
-Path3605=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connect.c\r
+Path3605=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connect.c\r
Line3607=189\r
-Path3607=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\IPC\osa_ipc_mailbox.c\r
+Path3607=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\IPC\osa_ipc_mailbox.c\r
Line3608=586\r
-Path3608=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_scan.c\r
+Path3608=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_scan.c\r
Line3609=382\r
-Path3609=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_scan.c\r
+Path3609=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_scan.c\r
Line3610=1328\r
-Path3610=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_scan.c\r
+Path3610=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_scan.c\r
Line3611=1288\r
-Path3611=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_scan.c\r
+Path3611=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_scan.c\r
Line3612=1122\r
-Path3612=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connect.c\r
+Path3612=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connect.c\r
Line3616=4927\r
-Path3616=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path3616=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line3617=1720\r
-Path3617=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path3617=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line3618=1762\r
-Path3618=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path3618=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line3619=1525\r
-Path3619=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path3619=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line3621=1717\r
-Path3621=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path3621=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line3622=985\r
-Path3622=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path3622=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line3623=1033\r
-Path3623=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path3623=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line3624=1817\r
-Path3624=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path3624=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line3625=1617\r
-Path3625=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path3625=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line3626=1300\r
-Path3626=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path3626=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line3627=2341\r
-Path3627=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path3627=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line3628=2287\r
-Path3628=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path3628=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line3629=4886\r
-Path3629=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path3629=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line3630=1319\r
-Path3630=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path3630=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line3631=5799\r
-Path3631=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path3631=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line3632=428\r
-Path3632=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_main.c\r
+Path3632=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_main.c\r
Line3633=152\r
-Path3633=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lm2um.c\r
+Path3633=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\lm2um.c\r
Line3634=97\r
-Path3634=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\um2lm.c\r
+Path3634=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\um2lm.c\r
Line3635=469\r
-Path3635=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_main.c\r
+Path3635=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_main.c\r
Line3636=2208\r
-Path3636=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path3636=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line3637=1979\r
-Path3637=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path3637=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line3638=2063\r
-Path3638=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
+Path3638=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
Line3639=2056\r
-Path3639=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path3639=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line3639.2=2306\r
-Path3639.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path3639.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line3640=1422\r
-Path3640=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path3640=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line3641=1497\r
-Path3641=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path3641=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line3643=777\r
-Path3643=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
+Path3643=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
Line3644=786\r
-Path3644=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
+Path3644=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
Line3645=1244\r
-Path3645=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
+Path3645=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_RF_Calibration.c\r
Line3646=1580\r
-Path3646=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
+Path3646=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
Line3648=966\r
-Path3648=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_advertise.c\r
+Path3648=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_advertise.c\r
Line3649=1616\r
-Path3649=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_advertise.c\r
+Path3649=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_advertise.c\r
Line3650=1205\r
-Path3650=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_advertise.c\r
+Path3650=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_advertise.c\r
Line3651=929\r
-Path3651=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_advertise.c\r
+Path3651=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_advertise.c\r
Line3652=1015\r
-Path3652=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_advertise.c\r
+Path3652=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_advertise.c\r
Line3653=743\r
-Path3653=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_advertise.c\r
+Path3653=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_advertise.c\r
Line3654=888\r
-Path3654=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_advertise.c\r
+Path3654=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_advertise.c\r
Line3664=1373\r
-Path3664=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path3664=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line3666=1269\r
-Path3666=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+Path3666=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
Line3667=795\r
-Path3667=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+Path3667=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
Line3668=978\r
-Path3668=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
+Path3668=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
Line3669=943\r
-Path3669=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
+Path3669=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
Line3670=1139\r
-Path3670=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Classification.c\r
+Path3670=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Classification.c\r
Line3671=1221\r
-Path3671=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Classification.c\r
+Path3671=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Classification.c\r
Line3672=5674\r
-Path3672=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
+Path3672=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\UM\wb_connection.c\r
Line3675=1538\r
-Path3675=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path3675=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line3676=393\r
-Path3676=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Gemini.c\r
+Path3676=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Gemini.c\r
Line3677=1202\r
-Path3677=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path3677=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line3678=1322\r
-Path3678=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path3678=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line3679=545\r
-Path3679=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Gemini.c\r
+Path3679=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Gemini.c\r
Line3680=915\r
-Path3680=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
-Line3680.2=1238\r
-Path3680.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
+Path3680=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmmain.c\r
+Line3680.2=1268\r
+Path3680.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\mcu_patches\mcu_hooks.c\r
Line3681=670\r
-Path3681=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
+Path3681=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
Line3684=4617\r
-Path3684=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
+Path3684=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LM\lmutil.c\r
Line3686=218\r
-Path3686=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\Gemini_wlan_coex.c\r
+Path3686=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\Gemini_wlan_coex.c\r
Line3686.2=234\r
-Path3686.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\Gemini_wlan_coex.c\r
+Path3686.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\Gemini_wlan_coex.c\r
Line3686.3=245\r
-Path3686.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\Gemini_wlan_coex.c\r
+Path3686.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\Gemini_wlan_coex.c\r
Line3688=2043\r
-Path3688=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
+Path3688=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Hci\hcid\hcid.c\r
Line3689=285\r
-Path3689=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
+Path3689=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
Line3690=456\r
-Path3690=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
+Path3690=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
Line3691=237\r
-Path3691=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
+Path3691=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
Line3692=423\r
-Path3692=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
+Path3692=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
Line3693=1427\r
-Path3693=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
+Path3693=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
Line3694=500\r
-Path3694=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
+Path3694=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
Line3695=1403\r
-Path3695=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
+Path3695=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
Line3696=244\r
-Path3696=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+Path3696=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
Line3697=301\r
-Path3697=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+Path3697=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
Line3698=342\r
-Path3698=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+Path3698=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
Line3699=524\r
-Path3699=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+Path3699=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
Line3700=552\r
-Path3700=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+Path3700=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
Line3701=789\r
-Path3701=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+Path3701=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
Line3705=1609\r
-Path3705=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+Path3705=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
Line3706=898\r
-Path3706=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+Path3706=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
Line3707=1503\r
-Path3707=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+Path3707=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
Line3708=1664\r
-Path3708=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+Path3708=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
Line3710=922\r
-Path3710=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
+Path3710=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_scan_activity.c\r
Line3711=406\r
-Path3711=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\wb_report_filter.c\r
+Path3711=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\wb_report_filter.c\r
Line3712=457\r
-Path3712=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path3712=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line3713=2221\r
-Path3713=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path3713=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line3714=1646\r
-Path3714=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path3714=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line3715=896\r
-Path3715=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path3715=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line3716=1546\r
-Path3716=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path3716=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line3717=1986\r
-Path3717=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path3717=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line3718=946\r
-Path3718=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path3718=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line3720=1448\r
-Path3720=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path3720=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line3721=1439\r
-Path3721=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path3721=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line3722=1060\r
-Path3722=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path3722=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line3727=1477\r
-Path3727=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
+Path3727=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
Line3728=1306\r
-Path3728=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_activity_core.c\r
+Path3728=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_activity_core.c\r
Line3729=266\r
-Path3729=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\ble_upper_mac_interface.c\r
+Path3729=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\ble_upper_mac_interface.c\r
Line3730=389\r
-Path3730=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\ble_upper_mac_interface.c\r
+Path3730=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\ble_upper_mac_interface.c\r
Line3732=711\r
-Path3732=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
+Path3732=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_connection_activity.c\r
Line3733=1171\r
-Path3733=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_activity_core.c\r
+Path3733=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_activity_core.c\r
Line3734=438\r
-Path3734=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
+Path3734=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
Line3735=548\r
-Path3735=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
+Path3735=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
Line3736=514\r
-Path3736=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
+Path3736=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
Line3737=1780\r
-Path3737=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
+Path3737=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_testmode_activity.c\r
Line3738=225\r
-Path3738=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
+Path3738=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
Line3739=369\r
-Path3739=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
+Path3739=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
Line3740=390\r
-Path3740=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
+Path3740=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
Line3741=178\r
-Path3741=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
+Path3741=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
Line3742=401\r
-Path3742=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
+Path3742=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
Line3743=402\r
-Path3743=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
+Path3743=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\control_path\mini_synchronizer.c\r
Line3744=928\r
-Path3744=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
+Path3744=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
Line3745=496\r
-Path3745=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
+Path3745=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
Line3746=976\r
-Path3746=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
+Path3746=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
Line3747=743\r
-Path3747=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
+Path3747=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
Line3748=695\r
-Path3748=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
+Path3748=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
Line3749=597\r
-Path3749=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
+Path3749=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
Line3751=167\r
-Path3751=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
+Path3751=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
Line3755=1360\r
-Path3755=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
+Path3755=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\ble_advertise_activity.c\r
Line3756=637\r
-Path3756=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Nike_plus\nike_plus_scan.c\r
+Path3756=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Nike_plus\nike_plus_scan.c\r
Line3757=192\r
-Path3757=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\Nike_plus\nike_plus_um_data_path.c\r
+Path3757=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\Nike_plus\nike_plus_um_data_path.c\r
Line3758=279\r
-Path3758=M:\Omri_WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\nike_plus_activity.c\r
+Path3758=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BLE_MAC\activities\nike_plus_activity.c\r
Line3760=1149\r
-Path3760=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+Path3760=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
Line3761=935\r
-Path3761=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+Path3761=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
Line3763=527\r
-Path3763=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+Path3763=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
Line3763.2=543\r
-Path3763.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+Path3763.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
Line3763.3=740\r
-Path3763.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+Path3763.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
Line3763.4=755\r
-Path3763.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+Path3763.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
Line3764=1096\r
-Path3764=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
+Path3764=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_ACL_Data.c\r
Line3765=648\r
-Path3765=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+Path3765=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
Line3765.2=1057\r
-Path3765.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+Path3765.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
Line3766=959\r
-Path3766=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+Path3766=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
Line3766.2=1849\r
-Path3766.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+Path3766.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
Line3776=436\r
-Path3776=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
+Path3776=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Clk.c\r
Line3777=1034\r
-Path3777=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
+Path3777=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Timers\osa_timer.c\r
Line3778=1258\r
-Path3778=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
+Path3778=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
Line3779=1266\r
-Path3779=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
+Path3779=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
Line3780=1098\r
-Path3780=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
+Path3780=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
Line3781=1578\r
-Path3781=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
+Path3781=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
Line3782=887\r
-Path3782=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
+Path3782=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
Line3783=912\r
-Path3783=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
+Path3783=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
Line3783.2=925\r
-Path3783.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
+Path3783.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
Line3783.3=938\r
-Path3783.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
+Path3783.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
Line3783.4=945\r
-Path3783.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
+Path3783.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
Line3783.5=952\r
-Path3783.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
+Path3783.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
Line3783.6=977\r
-Path3783.6=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
+Path3783.6=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
Line3783.7=1009\r
-Path3783.7=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
+Path3783.7=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_PowerControl.c\r
Line3784=1351\r
-Path3784=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
+Path3784=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_bt_secure_connection.c\r
Line3785=891\r
-Path3785=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
+Path3785=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
Line3786=946\r
-Path3786=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
+Path3786=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
Line3787=1083\r
-Path3787=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
+Path3787=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
Line3788=1117\r
-Path3788=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
+Path3788=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
Line3789=1249\r
-Path3789=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
+Path3789=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
Line3790=1628\r
-Path3790=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
+Path3790=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\TOP\coex\top_mws_coex.c\r
Line3791=1005\r
-Path3791=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path3791=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line3791.2=1108\r
-Path3791.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
+Path3791.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line3792=175\r
-Path3792=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+Path3792=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
Line3793=200\r
-Path3793=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+Path3793=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
Line3794=757\r
-Path3794=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+Path3794=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
Line3795=864\r
-Path3795=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+Path3795=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
Line3796=1065\r
-Path3796=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+Path3796=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
Line3797=1143\r
-Path3797=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+Path3797=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
Line3798=1195\r
-Path3798=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+Path3798=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
Line3799=1368\r
-Path3799=M:\Omri_WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
+Path3799=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\TransportLayer\H4\H4_Protocol.c\r
Line3808=1095\r
-Path3808=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3808=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3809=1091\r
-Path3809=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3809=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3810=914\r
-Path3810=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3810=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3811=1312\r
-Path3811=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3811=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3812=1308\r
-Path3812=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3812=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3813=1299\r
-Path3813=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3813=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3814=1432\r
-Path3814=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3814=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3815=1397\r
-Path3815=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3815=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3816=1046\r
-Path3816=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3816=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3817=874\r
-Path3817=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3817=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3818=2368\r
-Path3818=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3818=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3819=2338\r
-Path3819=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3819=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3820=1915\r
-Path3820=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3820=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3821=1895\r
-Path3821=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3821=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3822=1896\r
-Path3822=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3822=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3823=2287\r
-Path3823=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3823=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3823.2=2304\r
-Path3823.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3823.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3824=1163\r
-Path3824=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3824=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3825=1597\r
-Path3825=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3825=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3826=1676\r
-Path3826=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3826=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3827=704\r
-Path3827=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3827=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3828=720\r
-Path3828=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3828=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3829=802\r
-Path3829=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3829=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3830=767\r
-Path3830=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3830=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3831=1187\r
-Path3831=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
+Path3831=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_LMAC.c\r
Line3832=352\r
-Path3832=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
+Path3832=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
Line3833=413\r
-Path3833=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
+Path3833=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
Line3833.2=595\r
-Path3833.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
+Path3833.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
Line3834=438\r
-Path3834=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
+Path3834=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
Line3835=443\r
-Path3835=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
+Path3835=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
Line3836=313\r
-Path3836=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
+Path3836=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
Line3837=318\r
-Path3837=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
+Path3837=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
Line3838=336\r
-Path3838=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
+Path3838=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
Line3839=356\r
-Path3839=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
+Path3839=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
Line3840=579\r
-Path3840=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
+Path3840=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
Line3841=622\r
-Path3841=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
+Path3841=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
Line3842=962\r
-Path3842=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
+Path3842=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
Line3843=940\r
-Path3843=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
+Path3843=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
Line3844=916\r
-Path3844=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
+Path3844=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
Line3845=867\r
-Path3845=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
+Path3845=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
Line3846=708\r
-Path3846=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
+Path3846=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
Line3847=578\r
-Path3847=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
+Path3847=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
Line3848=549\r
-Path3848=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
+Path3848=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
Line3849=509\r
-Path3849=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
+Path3849=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
Line3850=349\r
-Path3850=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
+Path3850=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
Line3851=339\r
-Path3851=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
+Path3851=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
Line3852=533\r
-Path3852=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
+Path3852=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
Line3853=485\r
-Path3853=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
+Path3853=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
Line3854=475\r
-Path3854=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
+Path3854=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
Line3855=401\r
-Path3855=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
+Path3855=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_LLR.c\r
Line3856=737\r
-Path3856=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
+Path3856=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LLR_FBF.c\r
Line3857=3552\r
-Path3857=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
+Path3857=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
Line3858=1790\r
-Path3858=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
+Path3858=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
Line3859=1574\r
-Path3859=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
+Path3859=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
Line3860=1962\r
-Path3860=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
+Path3860=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Sniff.c\r
Line3866=3965\r
-Path3866=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
+Path3866=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_AclManager.c\r
Line3867=1538\r
-Path3867=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
+Path3867=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
Line3868=2170\r
-Path3868=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
+Path3868=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_FrameByFrame.c\r
Line3869=364\r
-Path3869=M:\Omri_WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Main.c\r
+Path3869=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\BT\Core\LC\LC_Main.c\r
Line3870=948\r
-Path3870=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
+Path3870=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
Line3871=896\r
-Path3871=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
+Path3871=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\SleepModes.c\r
Line4001=613\r
-Path4001=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
+Path4001=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
Line4002=560\r
-Path4002=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
+Path4002=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
Line4003=1562\r
-Path4003=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_personality_mgmt.c\r
+Path4003=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_personality_mgmt.c\r
Line4004=568\r
-Path4004=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
+Path4004=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
Line4004.2=588\r
-Path4004.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
+Path4004.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
Line4005=670\r
-Path4005=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
+Path4005=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
Line4006=781\r
-Path4006=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
+Path4006=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
Line4007=750\r
-Path4007=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
+Path4007=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
Line4007.2=776\r
-Path4007.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
+Path4007.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
Line4008=1615\r
-Path4008=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_personality_mgmt.c\r
+Path4008=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_personality_mgmt.c\r
Line4009=1536\r
-Path4009=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_personality_mgmt.c\r
+Path4009=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_personality_mgmt.c\r
Line4009.2=1567\r
-Path4009.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_personality_mgmt.c\r
+Path4009.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_personality_mgmt.c\r
Line4010=817\r
-Path4010=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_listen.c\r
+Path4010=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_listen.c\r
Line4011=1437\r
-Path4011=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_interrupt.c\r
+Path4011=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_interrupt.c\r
Line4012=716\r
-Path4012=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
+Path4012=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
Line4012.2=724\r
-Path4012.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
+Path4012.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
Line4013=740\r
-Path4013=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
+Path4013=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
Line4013.2=766\r
-Path4013.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
+Path4013.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Tag\nfc_listen.c\r
Line4032=194\r
-Path4032=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep.c\r
+Path4032=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep.c\r
Line4033=189\r
-Path4033=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4033=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4033.2=499\r
-Path4033.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4033.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4034=677\r
-Path4034=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep.c\r
+Path4034=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep.c\r
Line4035=263\r
-Path4035=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4035=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4035.2=562\r
-Path4035.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4035.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4036=393\r
-Path4036=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4036=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4037=701\r
-Path4037=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4037=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4038=763\r
-Path4038=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4038=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4039=798\r
-Path4039=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4039=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4040=855\r
-Path4040=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4040=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4040.2=894\r
-Path4040.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4040.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4041=1607\r
-Path4041=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4041=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4042=932\r
-Path4042=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4042=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4043=943\r
-Path4043=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4043=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4044=960\r
-Path4044=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4044=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4045=980\r
-Path4045=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4045=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4046=1091\r
-Path4046=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4046=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4047=1132\r
-Path4047=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4047=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4048=1362\r
-Path4048=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4048=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4049=1405\r
-Path4049=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4049=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4050=1503\r
-Path4050=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4050=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4051=1525\r
-Path4051=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4051=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4052=1580\r
-Path4052=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4052=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4053=1641\r
-Path4053=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4053=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4054=1672\r
-Path4054=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4054=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4055=1710\r
-Path4055=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4055=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4056=1850\r
-Path4056=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4056=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4056.2=2115\r
-Path4056.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4056.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4057=1943\r
-Path4057=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4057=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4057.2=2275\r
-Path4057.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4057.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4058=1963\r
-Path4058=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4058=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4058.2=2209\r
-Path4058.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4058.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4059=2000\r
-Path4059=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4059=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4059.2=2144\r
-Path4059.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4059.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4060=2021\r
-Path4060=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4060=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4060.2=2158\r
-Path4060.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4060.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4061=2289\r
-Path4061=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4061=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4062=2365\r
-Path4062=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4062=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4064=148\r
-Path4064=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep.c\r
+Path4064=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep.c\r
Line4065=408\r
-Path4065=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep.c\r
+Path4065=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep.c\r
Line4066=504\r
-Path4066=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep.c\r
+Path4066=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep.c\r
Line4067=447\r
-Path4067=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_ce.c\r
+Path4067=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_ce.c\r
Line4068=469\r
-Path4068=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_rw.c\r
+Path4068=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_rw.c\r
Line4069=570\r
-Path4069=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_ce.c\r
+Path4069=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_ce.c\r
Line4070=733\r
-Path4070=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_rw.c\r
+Path4070=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_rw.c\r
Line4071=176\r
-Path4071=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
+Path4071=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
Line4071.2=429\r
-Path4071.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
+Path4071.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
Line4072=336\r
-Path4072=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
+Path4072=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
Line4073=350\r
-Path4073=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
+Path4073=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
Line4074=488\r
-Path4074=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
+Path4074=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
Line4075=621\r
-Path4075=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
+Path4075=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
Line4076=826\r
-Path4076=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
+Path4076=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
Line4077=909\r
-Path4077=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
+Path4077=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
Line4078=962\r
-Path4078=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
+Path4078=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
Line4079=1879\r
-Path4079=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
+Path4079=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
Line4080=658\r
-Path4080=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_ce.c\r
+Path4080=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_ce.c\r
Line4081=229\r
-Path4081=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_rw.c\r
+Path4081=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_rw.c\r
Line4081.2=243\r
-Path4081.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_rw.c\r
+Path4081.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_rw.c\r
Line4081.3=396\r
-Path4081.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_rw.c\r
+Path4081.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_rw.c\r
Line4082=258\r
-Path4082=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_rw.c\r
+Path4082=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_rw.c\r
Line4083=981\r
-Path4083=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_rw.c\r
+Path4083=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_rw.c\r
Line4084=527\r
-Path4084=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_rw.c\r
+Path4084=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_rw.c\r
Line4085=869\r
-Path4085=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_rw.c\r
+Path4085=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_rw.c\r
Line4086=874\r
-Path4086=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_rw.c\r
+Path4086=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_activation_rw.c\r
Line4087=223\r
-Path4087=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_activation_ce.c\r
+Path4087=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_activation_ce.c\r
Line4088=229\r
-Path4088=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_activation_ce.c\r
+Path4088=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_activation_ce.c\r
Line4089=456\r
-Path4089=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_activation_ce.c\r
+Path4089=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_activation_ce.c\r
Line4090=462\r
-Path4090=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_activation_ce.c\r
+Path4090=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_activation_ce.c\r
Line4091=214\r
-Path4091=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_activation_rw.c\r
+Path4091=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_activation_rw.c\r
Line4092=220\r
-Path4092=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_activation_rw.c\r
+Path4092=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_activation_rw.c\r
Line4093=364\r
-Path4093=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_activation_rw.c\r
+Path4093=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_activation_rw.c\r
Line4094=370\r
-Path4094=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_activation_rw.c\r
+Path4094=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_activation_rw.c\r
Line4095=235\r
-Path4095=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_data_exchange_defs.c\r
+Path4095=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_data_exchange_defs.c\r
Line4096=1092\r
-Path4096=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF.c\r
+Path4096=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF.c\r
Line4097=346\r
-Path4097=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
+Path4097=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
Line4097.2=435\r
-Path4097.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
+Path4097.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
Line4097.3=515\r
-Path4097.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
+Path4097.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
Line4097.4=660\r
-Path4097.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
+Path4097.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
Line4098=385\r
-Path4098=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
+Path4098=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
Line4098.2=474\r
-Path4098.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
+Path4098.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
Line4098.3=549\r
-Path4098.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
+Path4098.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
Line4098.4=686\r
-Path4098.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
+Path4098.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
Line4099=269\r
-Path4099=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
+Path4099=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
Line4100=848\r
-Path4100=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_listen.c\r
+Path4100=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_listen.c\r
Line4101=895\r
-Path4101=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_listen.c\r
+Path4101=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_listen.c\r
Line4102=1828\r
-Path4102=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
+Path4102=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
Line4103=331\r
-Path4103=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
+Path4103=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
Line4103.2=407\r
-Path4103.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
+Path4103.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
Line4103.3=492\r
-Path4103.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
+Path4103.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
Line4103.4=608\r
-Path4103.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
+Path4103.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
Line4104=678\r
-Path4104=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
+Path4104=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\nfc_dep\nfc_dep_protocol.c\r
Line4105=588\r
-Path4105=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
+Path4105=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
Line4107=700\r
-Path4107=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_calibrations.c\r
+Path4107=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_calibrations.c\r
Line4108=895\r
-Path4108=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
+Path4108=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
Line4109=921\r
-Path4109=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
+Path4109=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
Line4111=998\r
-Path4111=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
+Path4111=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF_poll.c\r
Line4112=702\r
-Path4112=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_calibrations.c\r
+Path4112=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\nfc_calibrations.c\r
Line4113=2250\r
-Path4113=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF.c\r
+Path4113=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF.c\r
Line4113.2=2286\r
-Path4113.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF.c\r
+Path4113.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF.c\r
Line4114=2168\r
-Path4114=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF.c\r
+Path4114=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF.c\r
Line4115=1735\r
-Path4115=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
+Path4115=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Data_Exchange\iso_dep\nfc_iso_dep_protocol.c\r
Line4116=721\r
-Path4116=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
+Path4116=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
Line4128=510\r
-Path4128=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path4128=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line4129=270\r
-Path4129=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path4129=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line4130=560\r
-Path4130=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path4130=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line4131=588\r
-Path4131=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path4131=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line4132=606\r
-Path4132=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path4132=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line4133=624\r
-Path4133=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path4133=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line4134=664\r
-Path4134=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path4134=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line4135=633\r
-Path4135=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path4135=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line4136=867\r
-Path4136=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path4136=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line4137=1291\r
-Path4137=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path4137=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line4138=1300\r
-Path4138=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path4138=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line4139=249\r
-Path4139=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path4139=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line4140=893\r
-Path4140=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path4140=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line4141=571\r
-Path4141=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path4141=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line4142=612\r
-Path4142=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path4142=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line4143=290\r
-Path4143=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path4143=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line4144=308\r
-Path4144=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path4144=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line4145=826\r
-Path4145=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path4145=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line4146=829\r
-Path4146=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path4146=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line4147=832\r
-Path4147=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path4147=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line4148=835\r
-Path4148=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path4148=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line4149=347\r
-Path4149=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path4149=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line4150=377\r
-Path4150=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path4150=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line4151=405\r
-Path4151=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path4151=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line4152=414\r
-Path4152=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path4152=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line4153=603\r
-Path4153=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_swp_hw.c\r
+Path4153=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_swp_hw.c\r
Line4154=781\r
-Path4154=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path4154=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line4155=1027\r
-Path4155=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path4155=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line4156=1023\r
-Path4156=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path4156=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line4157=1037\r
-Path4157=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path4157=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line4158=1033\r
-Path4158=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
+Path4158=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_shdlc_protocol.c\r
Line4159=1370\r
-Path4159=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path4159=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line4160=209\r
-Path4160=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_interrupt.c\r
+Path4160=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_interrupt.c\r
Line4161=271\r
-Path4161=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_interrupt.c\r
+Path4161=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_interrupt.c\r
Line4162=267\r
-Path4162=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
+Path4162=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
Line4163=184\r
-Path4163=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
+Path4163=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
Line4164=244\r
-Path4164=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
+Path4164=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
Line4165=782\r
-Path4165=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_main.c\r
+Path4165=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_main.c\r
Line4166=143\r
-Path4166=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
+Path4166=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
Line4167=806\r
-Path4167=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
+Path4167=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Reader\Technology_Detection\nfc_technology_detection.c\r
Line4168=383\r
-Path4168=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_interrupt.c\r
+Path4168=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_interrupt.c\r
Line4169=393\r
-Path4169=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_interrupt.c\r
+Path4169=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_interrupt.c\r
Line4170=639\r
-Path4170=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_interrupt.c\r
+Path4170=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_interrupt.c\r
Line4171=152\r
-Path4171=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF.c\r
+Path4171=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_RF.c\r
Line4172=904\r
-Path4172=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_interrupt.c\r
+Path4172=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_interrupt.c\r
Line4173=1097\r
-Path4173=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_interrupt.c\r
-Line4174=1179\r
-Path4174=M:\Omri_WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
-Line4174.2=704\r
-Path4174.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
+Path4173=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_interrupt.c\r
+Line4174=704\r
+Path4174=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
+Line4174.2=1179\r
+Path4174.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\Proj\sources\int_handler.c\r
Line4175=103\r
-Path4175=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_buffer.c\r
+Path4175=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_buffer.c\r
Line4176=236\r
-Path4176=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_buffer.c\r
+Path4176=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_buffer.c\r
Line4177=261\r
-Path4177=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_buffer.c\r
+Path4177=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Utils\nfc_buffer.c\r
Line4178=406\r
-Path4178=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
+Path4178=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
Line4179=411\r
-Path4179=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
+Path4179=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
Line4180=597\r
-Path4180=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
+Path4180=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
Line4181=623\r
-Path4181=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
+Path4181=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
Line4182=408\r
-Path4182=M:\Omri_WPAN_45nm_FW_4_SP\ti\OSA\Buffers\osa_buf.c\r
+Path4182=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\OSA\Buffers\osa_buf.c\r
Line4183=823\r
-Path4183=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_main.c\r
+Path4183=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_main.c\r
Line4184=485\r
-Path4184=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_interrupt.c\r
+Path4184=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_interrupt.c\r
Line4185=849\r
-Path4185=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
+Path4185=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_timer.c\r
Line4187=669\r
-Path4187=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_main.c\r
+Path4187=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_main.c\r
Line4188=674\r
-Path4188=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_main.c\r
+Path4188=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\main\nfc_main.c\r
Line4189=1358\r
-Path4189=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
+Path4189=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
Line4190=1121\r
-Path4190=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
+Path4190=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_persistent.c\r
Line4192=821\r
-Path4192=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
+Path4192=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
Line4193=844\r
-Path4193=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
+Path4193=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
Line4194=860\r
-Path4194=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
+Path4194=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_DCLB.c\r
Line4195=617\r
-Path4195=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_swp_hw.c\r
+Path4195=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\Drv\nfc_swp_hw.c\r
Line4224=165\r
-Path4224=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path4224=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line4225=1004\r
-Path4225=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
+Path4225=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\core\Secure_Element\nfc_swp_protocol.c\r
Line4226=1669\r
-Path4226=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_controller.c\r
+Path4226=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_controller.c\r
Line4227=353\r
-Path4227=M:\Omri_WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_admin_gate.c\r
+Path4227=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\NFC\hci\nfc_hci_admin_gate.c\r
Line5000=1311\r
-Path5000=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5000=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5001=478\r
-Path5001=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
+Path5001=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
Line5002=484\r
-Path5002=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
+Path5002=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
Line5003=730\r
-Path5003=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
+Path5003=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
Line5004=204\r
-Path5004=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_config.c\r
+Path5004=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_config.c\r
Line5005=245\r
-Path5005=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5005=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5006=159\r
-Path5006=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5006=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5007=862\r
-Path5007=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5007=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5010=2063\r
-Path5010=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
+Path5010=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
Line5011=2258\r
-Path5011=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
+Path5011=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
Line5011.2=2331\r
-Path5011.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
+Path5011.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
Line5011.3=2379\r
-Path5011.3=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
+Path5011.3=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
Line5011.4=2431\r
-Path5011.4=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
+Path5011.4=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
Line5011.5=2476\r
-Path5011.5=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
+Path5011.5=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
Line5011.6=2518\r
-Path5011.6=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
+Path5011.6=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
Line5013=840\r
-Path5013=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
+Path5013=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
Line5016=284\r
-Path5016=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_config.c\r
+Path5016=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_config.c\r
Line5017=339\r
-Path5017=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_config.c\r
+Path5017=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_config.c\r
Line5018=406\r
-Path5018=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_config.c\r
+Path5018=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_config.c\r
Line5019=451\r
-Path5019=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_config.c\r
+Path5019=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_config.c\r
Line5021=909\r
-Path5021=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5021=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5022=704\r
-Path5022=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5022=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5022.2=792\r
-Path5022.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5022.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5023=712\r
-Path5023=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5023=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5023.2=800\r
-Path5023.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5023.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5024=634\r
-Path5024=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5024=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5025=644\r
-Path5025=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5025=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5026=537\r
-Path5026=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5026=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5027=586\r
-Path5027=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5027=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5028=1126\r
-Path5028=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5028=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5029=1132\r
-Path5029=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5029=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5030=1137\r
-Path5030=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5030=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5030.2=1265\r
-Path5030.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5030.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5031=623\r
-Path5031=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5031=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5033=195\r
-Path5033=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5033=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5034=425\r
-Path5034=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5034=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5035=517\r
-Path5035=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5035=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5036=613\r
-Path5036=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5036=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5037=684\r
-Path5037=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5037=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5038=772\r
-Path5038=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5038=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5039=738\r
-Path5039=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5039=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5040=828\r
-Path5040=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5040=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5073=695\r
-Path5073=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5073=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5074=783\r
-Path5074=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5074=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5075=527\r
-Path5075=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5075=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5084=199\r
-Path5084=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5084=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5085=215\r
-Path5085=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5085=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5086=231\r
-Path5086=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5086=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5087=280\r
-Path5087=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5087=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5088=347\r
-Path5088=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5088=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5200=118\r
-Path5200=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_sleep.c\r
+Path5200=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_sleep.c\r
Line5201=142\r
-Path5201=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_sleep.c\r
+Path5201=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_sleep.c\r
Line5202=1174\r
-Path5202=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
+Path5202=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
Line5203=360\r
-Path5203=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5203=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5204=364\r
-Path5204=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5204=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5214=294\r
-Path5214=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_sleep.c\r
+Path5214=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_sleep.c\r
Line5216=1728\r
-Path5216=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5216=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5217=1761\r
-Path5217=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5217=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5221=1578\r
-Path5221=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5221=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5222=1634\r
-Path5222=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5222=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5223=1667\r
-Path5223=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5223=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5227=293\r
-Path5227=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5227=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5229=1653\r
-Path5229=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5229=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5230=1638\r
-Path5230=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5230=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5230.2=1449\r
-Path5230.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
+Path5230.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
Line5231=1642\r
-Path5231=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5231=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5231.2=1453\r
-Path5231.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
+Path5231.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
Line5232=1649\r
-Path5232=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5232=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5233=902\r
-Path5233=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5233=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5234=896\r
-Path5234=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5234=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5235=959\r
-Path5235=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5235=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5236=1047\r
-Path5236=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5236=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5237=375\r
-Path5237=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5237=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5238=371\r
-Path5238=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5238=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5239=469\r
-Path5239=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5239=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5240=473\r
-Path5240=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5240=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5241=537\r
-Path5241=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5241=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5242=541\r
-Path5242=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5242=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5243=487\r
-Path5243=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5243=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5244=491\r
-Path5244=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5244=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5245=552\r
-Path5245=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5245=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5246=556\r
-Path5246=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5246=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5249=1931\r
-Path5249=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5249=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5251=1937\r
-Path5251=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5251=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5252=411\r
-Path5252=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_sleep.c\r
+Path5252=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_sleep.c\r
Line5252.2=444\r
-Path5252.2=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_sleep.c\r
+Path5252.2=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_sleep.c\r
Line5253=448\r
-Path5253=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_sleep.c\r
+Path5253=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_sleep.c\r
Line5254=415\r
-Path5254=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_sleep.c\r
+Path5254=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_sleep.c\r
Line5255=1675\r
-Path5255=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
+Path5255=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_control.c\r
Line5257=556\r
-Path5257=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
+Path5257=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_interrupts.c\r
Line5258=2028\r
-Path5258=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
+Path5258=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
Line5259=846\r
-Path5259=M:\Omri_WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
+Path5259=C:\BTFW_Local\Altassian_SourceTree\WPAN_45nm_FW_4_SP\ti\SOC\SLIMbus\sb_messages.c\r
\r
[StringTable]\r
Str10.0=0,0,HV1\r
index b8c9f6c70f45156303649fc72f9aa0282014a73e..5145ee5a9e66d1d028387a426f0fbca3b35dec15 100644 (file)
Binary files a/initscripts/TIInit_11.8.32.bts and b/initscripts/TIInit_11.8.32.bts differ
Binary files a/initscripts/TIInit_11.8.32.bts and b/initscripts/TIInit_11.8.32.bts differ
index 585bce5fe376725de3a0e37583e6c7b756885c8b..946aa546cb73b4c6bf481a80442c8a86d7a7b31b 100644 (file)
Binary files a/initscripts/TIInit_12.10.28.bts and b/initscripts/TIInit_12.10.28.bts differ
Binary files a/initscripts/TIInit_12.10.28.bts and b/initscripts/TIInit_12.10.28.bts differ
index a6d063fb86462393bf16f7a98cf7fceb4d2fb2f7..5799aa9cf22b96299972a2c761d9957a4398c055 100644 (file)
Binary files a/initscripts/TIInit_6.12.26.bts and b/initscripts/TIInit_6.12.26.bts differ
Binary files a/initscripts/TIInit_6.12.26.bts and b/initscripts/TIInit_6.12.26.bts differ
index 6c11cf95fc016a67f621955a1ffe37fd3480c97e..2d24a9622eb6eba1a0b3e7fcd281b587aee6c09c 100644 (file)
Binary files a/initscripts/TIInit_6.7.16.bts and b/initscripts/TIInit_6.7.16.bts differ
Binary files a/initscripts/TIInit_6.7.16.bts and b/initscripts/TIInit_6.7.16.bts differ
diff --git a/initscripts/initscripts-TIInit_6.12.26.bts b/initscripts/initscripts-TIInit_6.12.26.bts
index 68072e47d46333c42b8c60ec8129497dc612c484..362814fef6160ae09434aae88f81ab2fd25773ff 100644 (file)
Binary files a/initscripts/initscripts-TIInit_6.12.26.bts and b/initscripts/initscripts-TIInit_6.12.26.bts differ
Binary files a/initscripts/initscripts-TIInit_6.12.26.bts and b/initscripts/initscripts-TIInit_6.12.26.bts differ
diff --git a/initscripts/initscripts-TIInit_6.7.16_bt_spec_4.1.bts b/initscripts/initscripts-TIInit_6.7.16_bt_spec_4.1.bts
index 69aaaad2a9747bd6c74c22a4789334d884a546ee..c7b9a28746d5cb07b8244ea10ed5e3c77fc9df2e 100644 (file)
Binary files a/initscripts/initscripts-TIInit_6.7.16_bt_spec_4.1.bts and b/initscripts/initscripts-TIInit_6.7.16_bt_spec_4.1.bts differ
Binary files a/initscripts/initscripts-TIInit_6.7.16_bt_spec_4.1.bts and b/initscripts/initscripts-TIInit_6.7.16_bt_spec_4.1.bts differ
index 31b94c4bdb721a8c4ff26714461a91a0a3b64f5e..136b0acb36f9a8350028695a3ff628ddbeb5276d 100644 (file)
--- a/xml/TIInit_12.10.28.xml
+++ b/xml/TIInit_12.10.28.xml
</Param>\r
</Type>\r
\r
-<Values name="WLAN_AFH_MAP_POLICY" type="enum">\r
- <Value val="0x00">give low priority to WLAN reported map</Value>\r
- <Value val="0x01">give high priority to WLAN reported map</Value>\r
- <Value val="0x02">ignore WLAN reported map</Value>\r
-</Values>\r
-\r
<Packet name="ve" type="ve" typemask="0x00000002">\r
<Param type="u" size="1">\r
<Name>Layer</Name>\r
<Value val="0x04">Bluetooth HCI Specification 2.1</Value>\r
<Value val="0x05">Bluetooth HCI Specification 3.0</Value>\r
<Value val="0x06">Bluetooth HCI Specification 4.0</Value>\r
+ <Value val="0x07">Bluetooth HCI Specification 4.1</Value>\r
+ <Value val="0x08">Bluetooth HCI Specification 4.2</Value>\r
+ <Value val="0x09">Bluetooth HCI Specification 5.0</Value> \r
<!-- \r
Taken from the following URL:\r
https://www.bluetooth.org/foundry/assignnumb/document/hci_assigned_numbers \r
<Value val="0x04">Bluetooth Core Specification 2.1</Value>\r
<Value val="0x05">Bluetooth Core Specification 3.0</Value>\r
<Value val="0x06">Bluetooth Core Specification 4.0</Value>\r
+ <Value val="0x07">Bluetooth Core Specification 4.1</Value>\r
+ <Value val="0x08">Bluetooth Core Specification 4.2</Value>\r
+ <Value val="0x09">Bluetooth Core Specification 5.0</Value> \r
<!-- \r
Taken from the following URL:\r
https://www.bluetooth.org/foundry/assignnumb/document/link_manager_protocol\r
<Value val="0x01">Clear Data</Value>\r
</Values>\r
\r
+<Values name="WLAN_AFH_MAP_POLICY" type="enum">\r
+ <Value val="0x00">give low priority to WLAN reported map</Value>\r
+ <Value val="0x01">give high priority to WLAN reported map</Value>\r
+ <Value val="0x02">ignore WLAN reported map</Value>\r
+</Values>\r
+\r
+\r
+\r
+\r
<!-- ******************************************************* -->\r
<!-- ******************************************************* -->\r
<!-- -->\r
</Param>\r
</Command>\r
\r
-<Command name="HCI_VS_Write_Memory_Block_To_DTST_Mem" type="sc" opcode="0xFD97">\r
- <Param type="o" size="2">\r
- <Name>Opcode</Name>\r
- <Default>0xFD97</Default>\r
- <Desc>HCIPP Write Memory Block To DTST Mem</Desc>\r
- </Param>\r
- <Param type="u" size="4">\r
- <Name>Address</Name>\r
- <Default>0x00190200</Default>\r
- <Desc />\r
- </Param>\r
- <Param type="u" size="1" label="len">\r
- <Name>Size</Name>\r
- <Default>04</Default>\r
- <Desc>1-200</Desc>\r
- </Param>\r
- <Param type="x" size="len">\r
- <Name>Values</Name>\r
- <Default>"00000000"</Default>\r
- <Desc>Data starts from left to right</Desc>\r
- </Param>\r
- <Param type="R">\r
- <Name>HCI_Command_Complete_Event</Name>\r
- <Default />\r
- <Desc />\r
- </Param>\r
-</Command>\r
-\r
-<Command name="HCI_VS_Read_Memory_Block_From_DTST" type="sc" opcode="0xFD7F">\r
- <Param type="o" size="2">\r
- <Name>Opcode</Name>\r
- <Default>0xFD7F</Default>\r
- <Desc>HCIPP Read Memory Block From DTST Mem</Desc>\r
- </Param>\r
- <Param type="u" size="4">\r
- <Name>Address</Name>\r
- <Default>0x00190200</Default>\r
- <Desc />\r
- </Param>\r
- <Param type="u" size="1" label="len">\r
- <Name>Size</Name>\r
- <Default>04</Default>\r
- <Desc>1-200</Desc>\r
- </Param>\r
- <Param type="R">\r
- <Name>HCI_Command_Complete_Event</Name>\r
- </Param>\r
- <Param type="u" size="1" valtype="Status">\r
- <Name>Status</Name>\r
- <Default>0x00</Default>\r
- <Desc>Status</Desc>\r
- </Param>\r
- <Param type="x" size="packet_remain">\r
- <Name>Data</Name>\r
- <Desc>any</Desc>\r
- </Param>\r
-</Command>\r
-\r
<Command name="HCI_VS_Write_BD_ADDR" type="sc" opcode="0xfc06">\r
<Param type="o" size="2">\r
<Name>Opcode</Name>\r
@@ -15606,179 +15557,6 @@
</Param>\r
</Command>\r
\r
-<Command name="HCI_VS_Config_Power_Mng_Params" type="sc" opcode="0xFD58">\r
- <Param type="o" size="2">\r
- <Name>Opcode</Name>\r
- <Default>0xFD58</Default>\r
- <Desc>HCIPP Config Power Mng Params</Desc>\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>Enable flag</Name>\r
- <Default>1</Default>\r
- <Desc>When set to 1, indicates enabling of power management algorithm</Desc>\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>rssi_thl_acl (dBm) </Name>\r
- <Default>-50</Default>\r
- <Desc />\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>rssi_thl_sco (dBm) </Name>\r
- <Default>-50</Default>\r
- <Desc />\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>rssi_thl_edr3 (dBm) </Name>\r
- <Default>-50</Default>\r
- <Desc />\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>rssi_thh_acl (dBm) </Name>\r
- <Default>-30</Default>\r
- <Desc />\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>rssi_thh_sco (dBm) </Name>\r
- <Default>-30</Default>\r
- <Desc />\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>rssi_thh_edr3 (dBm) </Name>\r
- <Default>-30</Default>\r
- <Desc />\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>rssi_vhth (dBm) </Name>\r
- <Default>-20</Default>\r
- <Desc />\r
- </Param>\r
- \r
- <Param type="u" size="1">\r
- <Name>rssi_vhth_edr3 (dBm) </Name>\r
- <Default>-20</Default>\r
- <Desc />\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>rssi_th_sensitivity</Name>\r
- <Default>-80</Default>\r
- <Desc></Desc>\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>snr_thl</Name>\r
- <Default>0</Default>\r
- <Desc>0 - disable SNR condition.</Desc>\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>snr_edr3_thl</Name>\r
- <Default>0</Default>\r
- <Desc>0 - disable SNR condition.</Desc>\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>snr_thh</Name>\r
- <Default>0</Default>\r
- <Desc>0 - disable SNR condition.</Desc>\r
- </Param>\r
- \r
- <Param type="u" size="1">\r
- <Name>snr_edr3_thh</Name>\r
- <Default>0</Default>\r
- <Desc>0 - disable SNR condition.</Desc>\r
- </Param>\r
- \r
- <Param type="u" size="1">\r
- <Name>bad_sync_count_th_sco</Name>\r
- <Default>3</Default>\r
- <Desc /> Used for SCO connection as threshold for req. in/decrease power.\r
- </Param>\r
- \r
- <Param type="u" size="1">\r
- <Name>fec_ration_thl_sco</Name>\r
- <Default>150</Default>\r
- <Desc> Threshold for req. decrease power in case of bad HEC. (bad_headers/Headers) < (1/fec_ration_thl_sco) </Desc>\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>fec_ration_thh_sco</Name>\r
- <Default>100</Default>\r
- <Desc> Threshold for req. increase power in case of bad HEC. (bad_headers/Headers) > (1/fec_ration_thh_sco) </Desc>\r
- </Param>\r
- \r
- <Param type="u" size="2">\r
- <Name>fec_min_headers_acl</Name>\r
- <Default>8</Default>\r
- <Desc> Minimum number of Headers to calculate HEC statistics for e/SCO connection</Desc>\r
- </Param>\r
- <Param type="u" size="2">\r
- <Name>fec_min_headers_sco</Name>\r
- <Default>8</Default>\r
- <Desc> Minimum number of Headers to calculate HEC statistics for ACL connection</Desc>\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>crc_ratio_thl_acl</Name>\r
- <Default>60</Default>\r
- <Desc> Threshold for req. decrease power in case of bad_crc. (bad_crc/(bad_crc + good_crc)) < (1/crc_ratio_thl_acl) </Desc>\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>crc_ratio_thh_acl</Name>\r
- <Default>10</Default>\r
- <Desc> Threshold for req. increase power in case of bad_crc. (bad_crc/(bad_crc + good_crc)) > (1/crc_ratio_thh_acl) </Desc>\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>crc_min_pkts_acl</Name>\r
- <Default>25</Default>\r
- <Desc>Minimum number of packets to calculate CRC statistics</Desc>\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>power_decision_time</Name>\r
- <Default>2</Default>\r
- <Desc>The interval, in which a decision is made whether to increase/decrease or not to change peer tx power (decision interval = power_decision_time x100ms)</Desc>\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>power_acl_response_time</Name>\r
- <Default>1</Default>\r
- <Desc>On ACL channel the minimal delay between the last command requested to increase power or decrease to the command request to increase power (delay interval = power_decision_time x power_response_time x 100ms)</Desc>\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>power_sco_response_time</Name>\r
- <Default>1</Default>\r
- <Desc>On E/SCO channel the minimal delay between the last command requested to increase power or decrease to the command request to increase power (delay interval = power_decision_time x power_response_time x 100ms)</Desc>\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>power_edr3_response_time</Name>\r
- <Default>1</Default>\r
- <Desc>On EDR3 channel the minimal delay between the last command requested to increase power or decrease to the command request to increase power (delay interval = power_decision_time x power_response_time x 100ms)</Desc>\r
- </Param>\r
- \r
- <Param type="u" size="1">\r
- <Name>power_delay_time</Name>\r
- <Default>20</Default>\r
- <Desc>The minimal delay between the last command requested to increase power or decrease to the command request to decrease power (delay interval = power_delay_time x power_decision_time x 100ms)</Desc>\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>deep_fade_rssi_delta1 (dBm)</Name>\r
- <Default>-10</Default>\r
- <Desc>rssi threshold between current measure and the previews measure to make decision if we in deep fade.(delta2 = rssi[N] - rssi[N-1]) </Desc>\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>deep_fade_rssi_delta2 (dBm)</Name>\r
- <Default>-20</Default>\r
- <Desc>rssi threshold between current measure and the one before the preview measure to make decision if we in deep fade.(delta2 = rssi[N] - rssi[N-2])</Desc>\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>deep_fade_edr3_rssi_delta1 (dBm)</Name>\r
- <Default>-10</Default>\r
- <Desc>rssi threshold between current measure and the previews measure to make decision if we in deep fade.(delta2 = rssi[N] - rssi[N-1] </Desc>\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>deep_fade_edr3_rssi_delta2 (dBm)</Name>\r
- <Default>-20</Default>\r
- <Desc>rssi threshold between current measure and the one before the preview measure to make decision if we in deep fade.(delta2 = rssi[N] - rssi[N-2])</Desc>\r
- </Param>\r
- <Param type="R">\r
- <Name>HCI_Command_Complete_Event</Name>\r
- <Default />\r
- <Desc />\r
- </Param>\r
-</Command>\r
\r
<Command name="HCI_VS_Config_CQDDR_Params" type="sc" opcode="0xFD64">\r
<Param type="o" size="2">\r
</Param>\r
</Command>\r
\r
+<Command name="HCI_VS_DRP_Reset_BER_Meter" type="sc" opcode="0xFE29">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFE29</Default>\r
+ <Desc>HCIPP Reset DRP BER Meter</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1" valtype="Status">\r
+ <Name>Status</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>0 - success, 1 - illegal command</Desc>\r
+ </Param>\r
+</Command>\r
\r
-<Command name="HCI_VS_DRP_Read_BER_Meter_Status" type="sc" opcode="0xFE2A">\r
+<Command name="HCI_VS_DRPb_BER_Meter_Start" type="sc" opcode="0xFD8B">\r
<Param type="o" size="2">\r
<Name>Opcode</Name>\r
- <Default>0xFE2A</Default>\r
- <Desc>HCIPP Read DRP BER Meter Status</Desc>\r
- </Param>\r
- <Param type="R">\r
- <Name>HCI_Command_Complete_Event</Name>\r
- <Default />\r
- <Desc />\r
- </Param>\r
- <Param type="u" size="1" valtype="Status">\r
- <Name>Status</Name>\r
- <Default>0x00</Default>\r
- <Desc>0 - success, 1 - illegal command</Desc>\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>Synced to master</Name>\r
- <Default>0x00</Default>\r
- <Desc>1 - synced to master, 0 - no sync detected</Desc>\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>Finished at least 1 test</Name>\r
- <Default>0x00</Default>\r
- <Desc>0 - First test has not been finished, 1 - Values are valid for current measurment</Desc>\r
- </Param>\r
- <Param type="u" size="4">\r
- <Name>Number of packet received in last test</Name>\r
- <Default>0x00</Default>\r
- <Desc>Number of packet received in last test</Desc>\r
- </Param>\r
- <Param type="u" size="4">\r
- <Name>Total bits counted in last test</Name>\r
- <Default>0x00</Default>\r
- <Desc>Total bits counted in last test</Desc>\r
- </Param>\r
- <Param type="u" size="4">\r
- <Name>Number of bits error found in last test</Name>\r
- <Default>0x00</Default>\r
- <Desc>Number of bits error found in last test</Desc>\r
- </Param>\r
- <Param type="u" size="4">\r
- <Name>Number of packet received in current test</Name>\r
- <Default>0x00</Default>\r
- <Desc>Number of packet received in current test</Desc>\r
- </Param>\r
-</Command>\r
- \r
- <Command name="HCI_VS_DRP_Reset_BER_Meter" type="sc" opcode="0xFE29">\r
- <Param type="o" size="2">\r
- <Name>Opcode</Name>\r
- <Default>0xFE29</Default>\r
- <Desc>HCIPP Reset DRP BER Meter</Desc>\r
- </Param>\r
- <Param type="R">\r
- <Name>HCI_Command_Complete_Event</Name>\r
- <Default />\r
- <Desc />\r
- </Param>\r
- <Param type="u" size="1" valtype="Status">\r
- <Name>Status</Name>\r
- <Default>0x00</Default>\r
- <Desc>0 - success, 1 - illegal command</Desc>\r
- </Param>\r
- </Command>\r
-\r
-<Command name="HCI_VS_DRPb_BER_Meter_Start" type="sc" opcode="0xFD8B">\r
- <Param type="o" size="2">\r
- <Name>Opcode</Name>\r
- <Default>0xFD8B</Default>\r
- <Desc>HCIPP Start DRP BER Meter</Desc>\r
+ <Default>0xFD8B</Default>\r
+ <Desc>HCIPP Start DRP BER Meter</Desc>\r
</Param>\r
<Param type="u" size="1">\r
<Name>Frequency Channel</Name>\r
</Param>\r
</Command>\r
\r
+ <Command name="HCI_VS_DRP_Read_BER_Meter_Status" type="sc" opcode="0xFE2A">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFE2A</Default>\r
+ <Desc>HCIPP Read DRP BER Meter Status</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1" valtype="Status">\r
+ <Name>Status</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>0 - success, 1 - illegal command</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Synced to master</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>1 - synced to master, 0 - no sync detected</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Finished at least 1 test</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>0 - First test has not been finished, 1 - Values are valid for current measurment</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Number of packet received in last test</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>Number of packet received in last test</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Total bits counted in last test</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>Total bits counted in last test</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Number of bits error found in last test</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>Number of bits error found in last test</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Number of packet received in current test</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>Number of packet received in current test</Desc>\r
+ </Param>\r
+ </Command>\r
+ \r
+\r
<Command name="HCI_VS_PADC2DC_Config" type="sc" opcode="0xFDE3">\r
<Param type="o" size="2">\r
<Name>Opcode</Name>\r
@@ -18891,326 +18669,113 @@
</Param>\r
</Command>\r
\r
-<Command name="HCI_VS_DRPb_Set_RF_Calibration_Info" type="sc" opcode="0xFD76">\r
+<Command name="HCI_VS_Auto_Recovery_State_Change" type="ve" opcode="0x1700">\r
<Param type="o" size="2">\r
<Name>Opcode</Name>\r
- <Default>0xFD76</Default>\r
- <Desc>HCI VS DRPb set RF calibration info</Desc>\r
+ <Default>0x1700</Default>\r
+ <Desc>Auto recovery status change event</Desc>\r
</Param>\r
- <Param type="u" size="1">\r
- <Name>Reserved</Name>\r
- <Default>0x00</Default>\r
- <Desc>Reserved Parameter</Desc>\r
+ <Param type="b" size="6">\r
+ <Name>BD Address</Name>\r
+ <Default></Default>\r
+ <Desc>BD address for which the recovery is being processed</Desc>\r
</Param>\r
- <Param type="u" size="4" valtype="RF_Calibration_DRPb_Bitmap">\r
- <Name>Short calibration indication</Name>\r
- <Default>0x00005421</Default>\r
- <Desc>Checked box = short calibration, Unchecked box = not short calibration; 0x0000-0xFFFF: short calibration bitmap, 0xFFFFFFFF: Keep last bitmap.</Desc>\r
- </Param>\r
- <Param type="u" size="4" valtype="RF_Calibration_DRPb_Bitmap">\r
- <Name>Calibrations with antenna</Name>\r
- <Default>0x00005761</Default>\r
- <Desc>Checked box = use antenna, Unchecked box = don't use antenna; 0x0000-0xFFFF: antenna bitmap, 0xFFFFFFFF: Keep last bitmap.</Desc>\r
- </Param>\r
- <Param type="u" size="1">\r
- <Name>SD delay in ms</Name>\r
- <Default>20</Default>\r
- <Desc>Trigger same calibration in [x] ms in case of non successive attempt due to shut-down</Desc>\r
+ <Param type="u" size="1" valtype="Auto_Recovery_States">\r
+ <Name>State</Name>\r
+ <Default>0</Default>\r
+ <Desc>Auto recovery state</Desc>\r
</Param>\r
- <Param type="u" size="1">\r
- <Name>Num of SD attempts</Name>\r
- <Default>5</Default>\r
- <Desc>Maximum number of additional non successive attempts due to shut-down during calibration process</Desc>\r
+ <Param type="u" size="1" valtype="Auto_Recovery_Roles">\r
+ <Name>Role</Name>\r
+ <Default>0</Default>\r
+ <Desc>Auto recovery Role: Pager or scanner</Desc>\r
</Param>\r
- <Param type="u" size="1">\r
- <Name>Interference delay_ms</Name>\r
- <Default>10</Default>\r
- <Desc>Trigger same calibration in [x] ms in case of non successive attempt due to general interference</Desc>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Auto_Recovery_Parameter_Request" type="vc" opcode="0xFDAA">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFDAA</Default>\r
+ <Desc>Request Parameters for an Auto recovery session</Desc>\r
</Param>\r
- <Param type="u" size="1">\r
- <Name>Num of calib interf attempts</Name>\r
- <Default>5</Default>\r
- <Desc>Maximum number of additional non successive attempts due to general interference during calibration process</Desc>\r
+ <Param type="u" size="2">\r
+ <Name>connection handle</Name>\r
+ <Default>1</Default>\r
+ <Desc>Connection handle to request parameters for</Desc>\r
</Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #1</Name>\r
- <Default>00</Default>\r
- <Desc>Calibrations order</Desc>\r
+ <Param type="u" size="8">\r
+ <Name>Reserved</Name>\r
+ <Default>0</Default>\r
+ <Desc>Reserved</Desc>\r
</Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #2</Name>\r
- <Default>07</Default>\r
- <Desc>Calibrations order</Desc>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
</Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #3</Name>\r
- <Default>06</Default>\r
- <Desc>Calibrations order</Desc>\r
+ <Param type="u" size="1" valtype="Status">\r
+ <Name>Status</Name>\r
+ <Default>0</Default>\r
+ <Desc>0 - Success, 1 - Illegal command</Desc>\r
</Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #4</Name>\r
- <Default>10</Default>\r
- <Desc>Calibrations order</Desc>\r
+ <Param type="u" size="2">\r
+ <Name>connection handle</Name>\r
+ <Default>1</Default>\r
+ <Desc>Connection handle to enable auto recovery on</Desc>\r
</Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #5</Name>\r
- <Default>04</Default>\r
- <Desc>Calibrations order</Desc>\r
+ <Param type="u" size="4">\r
+ <Name>Start Value</Name>\r
+ <Default>0x0</Default>\r
+ <Desc>BT CLK to act as a reference point for anchor points</Desc>\r
</Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #6</Name>\r
- <Default>05</Default>\r
- <Desc>Calibrations order</Desc>\r
+ <Param type="u" size="2">\r
+ <Name>Anchor Interval</Name>\r
+ <Default>0x400</Default>\r
+ <Desc>Interval between two recovery anchor points</Desc>\r
</Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #7</Name>\r
- <Default>08</Default>\r
- <Desc>Calibrations order</Desc>\r
+ <Param type="u" size="2">\r
+ <Name>Fast Timeout</Name>\r
+ <Default>1800</Default>\r
+ <Desc>Fast recovery timeout (In seconds)</Desc>\r
</Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #8</Name>\r
- <Default>09</Default>\r
- <Desc>Calibrations order</Desc>\r
+ <Param type="u" size="2">\r
+ <Name>Slow Timeout</Name>\r
+ <Default>48000</Default>\r
+ <Desc>Fast recovery timeout (In seconds)</Desc>\r
</Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #9</Name>\r
- <Default>11</Default>\r
- <Desc>Calibrations order</Desc>\r
+ \r
+</Command>\r
+\r
+<Command name="HCI_VS_Auto_Recovery_Enable" type="vc" opcode="0xFDAC">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFDAC</Default>\r
+ <Desc>Enable auto recovery on link</Desc>\r
</Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #10</Name>\r
- <Default>12</Default>\r
- <Desc>Calibrations order</Desc>\r
+ <Param type="u" size="2">\r
+ <Name>connection handle</Name>\r
+ <Default>1</Default>\r
+ <Desc>Connection handle to enable auto recovery on</Desc>\r
</Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #11</Name>\r
- <Default>13</Default>\r
- <Desc>Calibrations order</Desc>\r
+ <Param type="u" size="4">\r
+ <Name>Start Value</Name>\r
+ <Default>0x0</Default>\r
+ <Desc>BT CLK to act as a reference point for anchor points</Desc>\r
</Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #12</Name>\r
- <Default>14</Default>\r
- <Desc>Calibrations order</Desc>\r
+ <Param type="u" size="2">\r
+ <Name>Anchor Interval</Name>\r
+ <Default>0x400</Default>\r
+ <Desc>Interval between two recovery anchor points</Desc>\r
</Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #13</Name>\r
- <Default>255</Default>\r
- <Desc>Calibrations order</Desc>\r
+ <Param type="u" size="2">\r
+ <Name>Fast Timeout</Name>\r
+ <Default>1800</Default>\r
+ <Desc>Fast recovery timeout (In seconds)</Desc>\r
</Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #14</Name>\r
- <Default>255</Default>\r
- <Desc>Calibrations order</Desc>\r
- </Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #15</Name>\r
- <Default>255</Default>\r
- <Desc>Calibrations order</Desc>\r
- </Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #16</Name>\r
- <Default>255</Default>\r
- <Desc>Calibrations order</Desc>\r
- </Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #17</Name>\r
- <Default>255</Default>\r
- <Desc>Calibrations order</Desc>\r
- </Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #18</Name>\r
- <Default>255</Default>\r
- <Desc>Calibrations order</Desc>\r
- </Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #19</Name>\r
- <Default>255</Default>\r
- <Desc>Calibrations order</Desc>\r
- </Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #20</Name>\r
- <Default>255</Default>\r
- <Desc>Calibrations order</Desc>\r
- </Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #21</Name>\r
- <Default>255</Default>\r
- <Desc>Calibrations order</Desc>\r
- </Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #22</Name>\r
- <Default>255</Default>\r
- <Desc>Calibrations order</Desc>\r
- </Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #23</Name>\r
- <Default>255</Default>\r
- <Desc>Calibrations order</Desc>\r
- </Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #24</Name>\r
- <Default>255</Default>\r
- <Desc>Calibrations order</Desc>\r
- </Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #25</Name>\r
- <Default>255</Default>\r
- <Desc>Calibrations order</Desc>\r
- </Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #26</Name>\r
- <Default>255</Default>\r
- <Desc>Calibrations order</Desc>\r
- </Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #27</Name>\r
- <Default>255</Default>\r
- <Desc>Calibrations order</Desc>\r
- </Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #28</Name>\r
- <Default>255</Default>\r
- <Desc>Calibrations order</Desc>\r
- </Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #29</Name>\r
- <Default>255</Default>\r
- <Desc>Calibrations order</Desc>\r
- </Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #30</Name>\r
- <Default>255</Default>\r
- <Desc>Calibrations order</Desc>\r
- </Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #31</Name>\r
- <Default>255</Default>\r
- <Desc>Calibrations order</Desc>\r
- </Param>\r
- <Param type="u" size="1" valtype="RF_Calibrations">\r
- <Name>Calibration #32</Name>\r
- <Default>255</Default>\r
- <Desc>Calibrations order</Desc>\r
- </Param>\r
- <Param type="u" size="4" >\r
- <Name>Reserved</Name>\r
- <Default>0</Default>\r
- <Desc>Reserved</Desc>\r
- </Param>\r
- <Param type="R">\r
- <Name>HCI_Command_Complete_Event</Name>\r
- <Default />\r
- <Desc />\r
- </Param>\r
-</Command>\r
-\r
-<Command name="HCI_VS_Auto_Recovery_State_Change" type="ve" opcode="0x1700">\r
- <Param type="o" size="2">\r
- <Name>Opcode</Name>\r
- <Default>0x1700</Default>\r
- <Desc>Auto recovery status change event</Desc>\r
- </Param>\r
- <Param type="b" size="6">\r
- <Name>BD Address</Name>\r
- <Default></Default>\r
- <Desc>BD address for which the recovery is being processed</Desc>\r
- </Param>\r
- <Param type="u" size="1" valtype="Auto_Recovery_States">\r
- <Name>State</Name>\r
- <Default>0</Default>\r
- <Desc>Auto recovery state</Desc>\r
- </Param>\r
- <Param type="u" size="1" valtype="Auto_Recovery_Roles">\r
- <Name>Role</Name>\r
- <Default>0</Default>\r
- <Desc>Auto recovery Role: Pager or scanner</Desc>\r
- </Param>\r
-</Command>\r
-\r
-<Command name="HCI_VS_Auto_Recovery_Parameter_Request" type="vc" opcode="0xFDAA">\r
- <Param type="o" size="2">\r
- <Name>Opcode</Name>\r
- <Default>0xFDAA</Default>\r
- <Desc>Request Parameters for an Auto recovery session</Desc>\r
- </Param>\r
- <Param type="u" size="2">\r
- <Name>connection handle</Name>\r
- <Default>1</Default>\r
- <Desc>Connection handle to request parameters for</Desc>\r
- </Param>\r
- <Param type="u" size="8">\r
- <Name>Reserved</Name>\r
- <Default>0</Default>\r
- <Desc>Reserved</Desc>\r
- </Param>\r
- <Param type="R">\r
- <Name>HCI_Command_Complete_Event</Name>\r
- <Default />\r
- <Desc />\r
- </Param>\r
- <Param type="u" size="1" valtype="Status">\r
- <Name>Status</Name>\r
- <Default>0</Default>\r
- <Desc>0 - Success, 1 - Illegal command</Desc>\r
- </Param>\r
- <Param type="u" size="2">\r
- <Name>connection handle</Name>\r
- <Default>1</Default>\r
- <Desc>Connection handle to enable auto recovery on</Desc>\r
- </Param>\r
- <Param type="u" size="4">\r
- <Name>Start Value</Name>\r
- <Default>0x0</Default>\r
- <Desc>BT CLK to act as a reference point for anchor points</Desc>\r
- </Param>\r
- <Param type="u" size="2">\r
- <Name>Anchor Interval</Name>\r
- <Default>0x400</Default>\r
- <Desc>Interval between two recovery anchor points</Desc>\r
- </Param>\r
- <Param type="u" size="2">\r
- <Name>Fast Timeout</Name>\r
- <Default>1800</Default>\r
- <Desc>Fast recovery timeout (In seconds)</Desc>\r
- </Param>\r
- <Param type="u" size="2">\r
- <Name>Slow Timeout</Name>\r
- <Default>48000</Default>\r
- <Desc>Fast recovery timeout (In seconds)</Desc>\r
- </Param>\r
- \r
-</Command>\r
-\r
-<Command name="HCI_VS_Auto_Recovery_Enable" type="vc" opcode="0xFDAC">\r
- <Param type="o" size="2">\r
- <Name>Opcode</Name>\r
- <Default>0xFDAC</Default>\r
- <Desc>Enable auto recovery on link</Desc>\r
- </Param>\r
- <Param type="u" size="2">\r
- <Name>connection handle</Name>\r
- <Default>1</Default>\r
- <Desc>Connection handle to enable auto recovery on</Desc>\r
- </Param>\r
- <Param type="u" size="4">\r
- <Name>Start Value</Name>\r
- <Default>0x0</Default>\r
- <Desc>BT CLK to act as a reference point for anchor points</Desc>\r
- </Param>\r
- <Param type="u" size="2">\r
- <Name>Anchor Interval</Name>\r
- <Default>0x400</Default>\r
- <Desc>Interval between two recovery anchor points</Desc>\r
- </Param>\r
- <Param type="u" size="2">\r
- <Name>Fast Timeout</Name>\r
- <Default>1800</Default>\r
- <Desc>Fast recovery timeout (In seconds)</Desc>\r
- </Param>\r
- <Param type="u" size="2">\r
- <Name>Slow Timeout</Name>\r
- <Default>48000</Default>\r
- <Desc>Fast recovery timeout (In seconds)</Desc>\r
+ <Param type="u" size="2">\r
+ <Name>Slow Timeout</Name>\r
+ <Default>48000</Default>\r
+ <Desc>Fast recovery timeout (In seconds)</Desc>\r
</Param>\r
<Param type="u" size="8">\r
<Name>Reserved</Name>\r
<Desc />\r
</Param>\r
</Command>\r
- \r
-<Command name="HCI_VS_LOAD_Cortex" type="vc" opcode="0xFDA8">\r
- <Cat>Wibree</Cat>\r
- <Param type="o" size="2">\r
- <Name>Opcode</Name>\r
- <Default>0xFDA8</Default>\r
- <Desc>Load Cortex</Desc>\r
- </Param>\r
- <Param type="u" size="1" valtype="EnableDisable">\r
- <Name>Mode</Name>\r
- <Default>0x00</Default>\r
- <Desc>0x01 = Disable Cortex Sleep</Desc>\r
- </Param>\r
- <Param type="R">\r
- <Name>HCI_Command_Complete_Event</Name>\r
- </Param>\r
-</Command>\r
\r
<Command name="HCI_VS_DRPB_Run_Self_Test" type="vc" opcode="0xFDC4">\r
<Cat>Wibree</Cat>\r
</Param>\r
</Command>\r
\r
+<Command name="HCI_VS_Set_WLAN_Coex_Params" type="vc" opcode="0xfe30">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name> \r
+ <Default>0xfe30</Default> \r
+ <Desc>Set host configurable WLAN coex parameters</Desc> \r
+ </Param>\r
+ <Param type="u" size="1" valtype="WLAN_AFH_MAP_POLICY">\r
+ <Name>WLAN_AFH_map_handling_policy</Name> \r
+ <Default>2</Default> \r
+ <Desc>Set the priority BT IP applies to WLAN reported channel map</Desc> \r
+ </Param> \r
+ <Param type="u" size="1">\r
+ <Name>RFU8_1</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>RFU</Desc>\r
+ </Param> \r
+ <Param type="u" size="1">\r
+ <Name>RFU8_2</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>RFU</Desc>\r
+ </Param> \r
+ <Param type="u" size="1">\r
+ <Name>RFU8_3</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>RFU</Desc>\r
+ </Param> \r
+ <Param type="u" size="2">\r
+ <Name>RFU16_1</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>RFU</Desc>\r
+ </Param> \r
+ <Param type="u" size="2">\r
+ <Name>RFU16_2</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>RFU</Desc>\r
+ </Param> \r
+ <Param type="u" size="4">\r
+ <Name>RFU32_1</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>RFU</Desc>\r
+ </Param> \r
+ <Param type="u" size="4">\r
+ <Name>RFU32_2</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>RFU</Desc>\r
+ </Param> \r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name> \r
+ <Default /> \r
+ <Desc />\r
+ </Param> \r
+</Command>\r
+\r
<!-- ================================================================== -->\r
<Command name="Tester Commands" type="gb" />\r
<!-- ================================================================== -->\r
@@ -23398,4 +22999,16060 @@
</Param>\r
</Command>\r
\r
+\r
+<!-- ================================================================== -->\r
+<Command name="HCI VS Legacy Commands (Not released to customers)" type="gb" />\r
+<!-- ================================================================== -->\r
+\r
+<Command name="HCI_VS_Set_Fixed_PIN_Code" type="sc" opcode="0xFF2B">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFF2B</Default>\r
+ <Desc>set encryption key parameters.</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>PIN Length</Name>\r
+ <Default>16</Default>\r
+ <Desc>Pin Code Length.</Desc>\r
+ </Param>\r
+ <Param type="x" size="16">\r
+ <Name>Pin Code Bytes</Name>\r
+ <Default>00000000000000000000000000000000</Default>\r
+ <Desc>LSB to MSB in HEX</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_L2cap_Flow_and_Length" type="sc" opcode="0xFE46">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFE46</Default>\r
+ <Desc>control l2cap payload header and length for testing l2cap flow using zero l2cap payload length in the payload header.</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="OnOff">\r
+ <Name>L2cap flow</Name>\r
+ <Default>0</Default>\r
+ <Desc>Sets the l2cap flow.</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="L2cap_len_flags">\r
+ <Name>L2cap length flag</Name>\r
+ <Default>0</Default>\r
+ <Desc>Sets the l2cap length in the header (Zero or positive).</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Select_Change_Pkt_Type_Event_EDR_Mode" type="sc" opcode="0xFD0D">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFD0D</Default>\r
+ <Desc>Select the mode which defines how the packet type field of the Change Packet Type Event is set in regard to the EDR bits</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="EDR_Mode">\r
+ <Name>EDR Mode</Name>\r
+ <Default>0</Default>\r
+ <Desc>Show or diregard the real value of the EDR packet bit.</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Set_UDI_Connection" type="sc" opcode="0xFD2F">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFD2F</Default>\r
+ <Desc>HCIPP Set Udi connection</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>udi_enable</Name>\r
+ <Default>0</Default>\r
+ <Desc>0=Disabled 1=Enabled. When set to 1, indicates enabling pcm synchronization for udi.</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>synch channel</Name>\r
+ <Default>0</Default>\r
+ <Desc>voice channel that the pcm should synchronize to.0 - channel one, 1- channel two</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Write_EPLC" type="sc" opcode="0xfd08">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFD08</Default>\r
+ <Desc>HCIPP Write EPLC (Enhanced packet loss concealment)</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>EPLC enable</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>Enhanced packet loss control feature: 0 - diabled, 1 - enabled. Enable only when there is no active voice connection.</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>EPLC R value</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>[0-15] R parameter used in EPLC (previous packet transmissions count), recommended max of 3. Updated only when enabling.</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>EPLC N value</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>[0-15] N parameter used in EPLC (noise packet transmissions count). Updated only when enabling.</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Reserved</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>This field is reserved for future use</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Config_Pcm_Synch_For_UDI" type="sc" opcode="0xFD1F">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFD1F</Default>\r
+ <Desc>Config pcm synch params</Desc>\r
+ </Param>\r
+ <Param type="2" size="2">\r
+ <Name>T_Check</Name>\r
+ <Default>2400</Default>\r
+ <Desc>Monitoring time of pcm buffer [frames]</Desc>\r
+ </Param>\r
+ <Param type="2" size="2">\r
+ <Name>T_Hold</Name>\r
+ <Default>4000</Default>\r
+ <Desc>Stabilizing time of pcm clock [frames]</Desc>\r
+ </Param>\r
+ <Param type="1" size="1">\r
+ <Name>Interrupt Threshold</Name>\r
+ <Default>12</Default>\r
+ <Desc>Min Threshold in percentage of the sco buffer size</Desc>\r
+ </Param>\r
+ <Param type="1" size="1">\r
+ <Name>Complement interrupt Threshold</Name>\r
+ <Default>37</Default>\r
+ <Desc>Max Threshold in percentage of the sco buffer size</Desc>\r
+ </Param>\r
+ <Param type="1" size="1">\r
+ <Name>PPM fix</Name>\r
+ <Default>2</Default>\r
+ <Desc>delta of ppm fix in pcm synchronization</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Enable_Disable_UART_Debug" type="sc" opcode="0xFDC5">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFDC5</Default>\r
+ <Desc>Enable or Disable the UART Debug HW output (does not affect debug-over-HCI) </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>action</Name>\r
+ <Default>1</Default>\r
+ <Desc>0 - Enable, 1 - Disable (as soon as the SW FIFO gets empty), 2 - Disable immediately (may casue logger corruption) </Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Set_RF_Link_Timer" type="sc" opcode="0xff76">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFF76</Default>\r
+ <Desc>HCIPP Set RF Link Timer</Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Interval</Name>\r
+ <Default>0x14</Default>\r
+ <Desc>20 frames - 25 mili</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Set_Test_Mux_Pin" type="sc" opcode="0xfd14">\r
+ \r
+ <Param type="u" size="1" label="Module_Name" valtype="SetTestMuxModuleName">\r
+ <Name>Module Name</Name>\r
+ <Default>0xFF</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ \r
+ <Param type="u" size="1" label="pin_id" valtype="SetTestMuxPinNumber">\r
+ <Name>PIN ID</Name>\r
+ <Default>1</Default>\r
+ <Desc>Pin nuber (from table)</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="Module_Name==7">\r
+ <Param type="u" size="1" valtype="BT_Debug_pins">\r
+ <Name>Test Mux value - Enter Value</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>Register Value </Desc>\r
+ </Param>\r
+ \r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux number of bits - Don't Touch </Name>\r
+ <Default>0x7</Default>\r
+ <Desc>number of bits each pin requires</Desc>\r
+ </Param>\r
+ <Param cond="pin_id==1">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 1 Address - Don't Touch </Name>\r
+ <Default>0x200E0F00</Default>\r
+ <Desc>Test Mux 1 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>7</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==2">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 1 Address - Don't Touch </Name>\r
+ <Default>0x200E0F00</Default>\r
+ <Desc>Test Mux 1 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>7</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>4</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>7</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==3">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 2 Address - Don't Touch </Name>\r
+ <Default>0x200E0F02</Default>\r
+ <Desc>Test Mux 2 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>8</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>7</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==4">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 2 Address - Don't Touch </Name>\r
+ <Default>0x200E0F02</Default>\r
+ <Desc>Test Mux 2 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>7</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>7</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==5">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 3 Address - Don't Touch </Name>\r
+ <Default>0x200E0F04</Default>\r
+ <Desc>Test Mux 3 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>7</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==6">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 3 Address - Don't Touch </Name>\r
+ <Default>0x200E0F04</Default>\r
+ <Desc>Test Mux 3 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>7</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>4</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>7</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==7">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 4 Address - Don't Touch </Name>\r
+ <Default>0x200E0F06</Default>\r
+ <Desc>Test Mux 4 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>8</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>7</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==8">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 4 Address - Don't Touch </Name>\r
+ <Default>0x200E0F06</Default>\r
+ <Desc>Test Mux 4 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>7</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>7</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Module_Name==2" >\r
+ <Param type="u" size="1" valtype="SDIO_Debug_pins">\r
+ <Name>Test Mux value - Enter Value</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>Register Value </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux number of bits - Don't Touch </Name>\r
+ <Default>0x3</Default>\r
+ <Desc>number of bits each pin requires</Desc>\r
+ </Param>\r
+ <Param cond="pin_id==1">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 0 Address</Name>\r
+ <Default>0x200E2018</Default>\r
+ <Desc>Test Mux 0 Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>2</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==2">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 0 Address</Name>\r
+ <Default>0x200E2018</Default>\r
+ <Desc>Test Mux 0 Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>4</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>2</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==3">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 1 Address - Don't Touch </Name>\r
+ <Default>0x200E2018</Default>\r
+ <Desc>Test Mux 1 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>8</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>6</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>2</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==4">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 1 Address - Don't Touch </Name>\r
+ <Default>0x200E2018</Default>\r
+ <Desc>Test Mux 1 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>9</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>2</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==5">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 2 Address - Don't Touch </Name>\r
+ <Default>0x200E201A</Default>\r
+ <Desc>Test Mux 2 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>2</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==6">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 2 Address - Don't Touch </Name>\r
+ <Default>0x200E201A</Default>\r
+ <Desc>Test Mux 2 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>4</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>2</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==7">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 3 Address - Don't Touch </Name>\r
+ <Default>0x200E201A</Default>\r
+ <Desc>Test Mux 3 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>8</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>2</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==8">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 3 Address - Don't Touch </Name>\r
+ <Default>0x200E201A</Default>\r
+ <Desc>Test Mux 3 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>6</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>2</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==9">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 4 Address - Don't Touch </Name>\r
+ <Default>0x200E201C</Default>\r
+ <Desc>Test Mux 4 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>9</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>2</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==10">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 4 Address - Don't Touch </Name>\r
+ <Default>0x200E201C</Default>\r
+ <Desc>Test Mux 4 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>4</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>2</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Module_Name==3">\r
+ <Param type="u" size="1" valtype="DMA_Debug_pins">\r
+ <Name>Test Mux value - Enter Value</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>Register Value \r
+ (*) - bit 0 of this signal will appear on test_bus bits: 0,2,4,6,8 \r
+ bit 1 of this signal will appear on test_bus bits: 1,3,5,7,9 \r
+ </Desc>\r
+ </Param>\r
+ <Param cond="pin_id==1">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux number of bits - Don't Touch </Name>\r
+ <Default>0x4</Default>\r
+ <Desc>number of bits each pin requires</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 3 Address - Don't Touch </Name>\r
+ <Default>0x200EF12A</Default>\r
+ <Desc>Test Mux 3 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==2">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux number of bits - Don't Touch </Name>\r
+ <Default>0x4</Default>\r
+ <Desc>number of bits each pin requires</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 1 Address - Don't Touch </Name>\r
+ <Default>0x200EF12A</Default>\r
+ <Desc>Test Mux 1 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>4</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==3">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux number of bits - Don't Touch </Name>\r
+ <Default>0x4</Default>\r
+ <Desc>number of bits each pin requires</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 1 Address - Don't Touch </Name>\r
+ <Default>0x200EF12A</Default>\r
+ <Desc>Test Mux 1 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>8</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>6</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==4">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux number of bits - Don't Touch </Name>\r
+ <Default>0x4</Default>\r
+ <Desc>number of bits each pin requires</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 1 Address - Don't Touch </Name>\r
+ <Default>0x200EF12A</Default>\r
+ <Desc>Test Mux 1 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>9</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==5">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux number of bits - Don't Touch </Name>\r
+ <Default>0x4</Default>\r
+ <Desc>number of bits each pin requires</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 2 Address - Don't Touch </Name>\r
+ <Default>0x200EF12C</Default>\r
+ <Desc>Test Mux 2 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==6">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux number of bits - Don't Touch </Name>\r
+ <Default>0x4</Default>\r
+ <Desc>number of bits each pin requires</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 2 Address - Don't Touch </Name>\r
+ <Default>0x200EF12C</Default>\r
+ <Desc>Test Mux 2 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>4</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==7">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux number of bits - Don't Touch </Name>\r
+ <Default>0x4</Default>\r
+ <Desc>number of bits each pin requires</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 2 Address - Don't Touch </Name>\r
+ <Default>0x200EF12C</Default>\r
+ <Desc>Test Mux 2 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>8</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==8">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux number of bits - Don't Touch </Name>\r
+ <Default>0x4</Default>\r
+ <Desc>number of bits each pin requires</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 2 Address - Don't Touch </Name>\r
+ <Default>0x200EF12C</Default>\r
+ <Desc>Test Mux 2 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>6</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==9">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux number of bits - Don't Touch </Name>\r
+ <Default>0x4</Default>\r
+ <Desc>number of bits each pin requires</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 3 Address - Don't Touch </Name>\r
+ <Default>0x200EF12E</Default>\r
+ <Desc>Test Mux 3 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>9</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==10">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux number of bits - Don't Touch </Name>\r
+ <Default>0x4</Default>\r
+ <Desc>number of bits each pin requires</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 3 Address - Don't Touch </Name>\r
+ <Default>0x200EF12E</Default>\r
+ <Desc>Test Mux 3 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>4</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ </Param>\r
+ \r
+ \r
+ <Param cond="Module_Name==4">\r
+ <Param type="u" size="1" valtype="OCP_IC_Debug_pins">\r
+ <Name>Test Mux value - Enter Value</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>Register Value \r
+ (*) - bit 0 of this signal will appear on test_bus bits: 0,2,4,6,8 \r
+ bit 1 of this signal will appear on test_bus bits: 1,3,5,7,9 \r
+ </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux number of bits - Don't Touch </Name>\r
+ <Default>6</Default>\r
+ <Desc>number of bits each pin requires</Desc>\r
+ </Param>\r
+ <Param cond="pin_id==1">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 1 Address - Don't Touch </Name>\r
+ <Default>0x200EF616</Default>\r
+ <Desc>Test Mux 1 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>4</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==2">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 1 Address - Don't Touch </Name>\r
+ <Default>0x200EF616</Default>\r
+ <Desc>Test Mux 1 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>8</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>4</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==3">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 2 Address - Don't Touch </Name>\r
+ <Default>0x200EF618</Default>\r
+ <Desc>Test Mux 2 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>6</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>4</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==4">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 2 Address - Don't Touch </Name>\r
+ <Default>0x200EF618</Default>\r
+ <Desc>Test Mux 2 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>8</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>9</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>4</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==5">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 3 Address - Don't Touch </Name>\r
+ <Default>0x200EF61A</Default>\r
+ <Desc>Test Mux 3 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>4</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==6">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 3 Address - Don't Touch </Name>\r
+ <Default>0x200EF61A</Default>\r
+ <Desc>Test Mux 3 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>8</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>4</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==7">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 4 Address - Don't Touch </Name>\r
+ <Default>0x200EF61C</Default>\r
+ <Desc>Test Mux 4 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>4</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==8">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 4 Address - Don't Touch </Name>\r
+ <Default>0x200EF61C</Default>\r
+ <Desc>Test Mux 4 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>8</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>6</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>4</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==9">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 5 Address - Don't Touch </Name>\r
+ <Default>0x200EF61E</Default>\r
+ <Desc>Test Mux 5 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>9</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>4</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==10">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 5 Address - Don't Touch </Name>\r
+ <Default>0x200EF61E</Default>\r
+ <Desc>Test Mux 5 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>8</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>4</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Module_Name==5">\r
+ <Param type="u" size="1" valtype="UART_Debug_pins">\r
+ <Name>Test Mux value - Enter Value</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>Register Value </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux number of bits - Don't Touch </Name>\r
+ <Default>4</Default>\r
+ <Desc>number of bits each pin requires</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="pin_id==1">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 1 Address - Don't Touch </Name>\r
+ <Default>0x200E1020</Default>\r
+ <Desc>Test Mux 1 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>5</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==2">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 1 Address - Don't Touch </Name>\r
+ <Default>0x200E1020</Default>\r
+ <Desc>Test Mux 1 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>4</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>5</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==3">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 1 Address - Don't Touch </Name>\r
+ <Default>0x200E1020</Default>\r
+ <Desc>Test Mux 1 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>8</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>6</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>5</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==4">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 1 Address - Don't Touch </Name>\r
+ <Default>0x200E1020</Default>\r
+ <Desc>Test Mux 1 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>9</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>5</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==5">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 2 Address - Don't Touch </Name>\r
+ <Default>0x200E1022</Default>\r
+ <Desc>Test Mux 2 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>5</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==6">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 2 Address - Don't Touch </Name>\r
+ <Default>0x200E1022</Default>\r
+ <Desc>Test Mux 2 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>4</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>5</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==7">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 2 Address - Don't Touch </Name>\r
+ <Default>0x200E1022</Default>\r
+ <Desc>Test Mux 2 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>8</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>5</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==8">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 2 Address - Don't Touch </Name>\r
+ <Default>0x200E1022</Default>\r
+ <Desc>Test Mux 2 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>6</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>5</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==9">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 3 Address - Don't Touch </Name>\r
+ <Default>0x200E1024</Default>\r
+ <Desc>Test Mux 3 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>9</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>5</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==10">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 3 Address - Don't Touch </Name>\r
+ <Default>0x200E1024</Default>\r
+ <Desc>Test Mux 3 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>4</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>5</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Module_Name==0">\r
+ <Param type="u" size="1" valtype="DRP_Debug_pins_empty_list">\r
+ <Name>Test Mux value - don't touch</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>Register Value </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux number of bits - Don't Touch </Name>\r
+ <Default>0x3</Default>\r
+ <Desc>number of bits each pin requires</Desc>\r
+ </Param>\r
+ <Param cond="pin_id==1">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 1 Address - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Test Mux 1 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==2">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 1 Address - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Test Mux 1 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==3">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 1 Address - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Test Mux 1 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>6</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>6</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==4">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 2 Address - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Test Mux 2 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>9</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>9</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==5">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 2 Address - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Test Mux 2 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==6">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 3 Address - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Test Mux 3 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==7">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 3 Address - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Test Mux 3 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==8">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 4 Address - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Test Mux 4 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>6</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>6</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==9">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 4 Address - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Test Mux 4 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>9</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>9</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==10">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 4 Address - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Test Mux 4 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Module_Name==1">\r
+ <Param type="u" size="1" valtype="WB_Debug_pins">\r
+ <Name>Test Mux value - Don't touch1</Name>\r
+ <Default>0x01</Default>\r
+ <Desc>Register Value </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux number of bits - Don't Touch </Name>\r
+ <Default>0x3</Default>\r
+ <Desc>number of bits each pin requires</Desc>\r
+ </Param>\r
+ <Param cond="pin_id==1">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 1 Address - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Test Mux 1 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>1</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==2">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 1 Address - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Test Mux 1 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>1</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==3">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 1 Address - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Test Mux 1 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>6</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>6</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>1</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==4">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 2 Address - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Test Mux 2 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>9</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>9</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>1</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==5">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 2 Address - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Test Mux 2 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300A</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>1</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==6">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 3 Address - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Test Mux 3 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>0</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>1</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==7">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 3 Address - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Test Mux 3 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>3</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>1</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==8">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 4 Address - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Test Mux 4 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>6</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>6</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>1</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==9">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 4 Address - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Test Mux 4 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>9</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>9</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>1</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="pin_id==10">\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Test Mux 4 Address - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Test Mux 4 Address - Don't Touch </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Test Mux Offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>offset inside test_mux register</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Debug Module register - Don't Touch </Name>\r
+ <Default>0x200E300C</Default>\r
+ <Desc>Register Address</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module offset - Don't Touch </Name>\r
+ <Default>12</Default>\r
+ <Desc>Offset within the register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Debug Module value - Don't Touch </Name>\r
+ <Default>1</Default>\r
+ <Desc>Register Value (3 bits)</Desc>\r
+ </Param>\r
+ </Param>\r
+ </Param>\r
+ \r
+ \r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_HW_Reset" type="sc" opcode="0xfe39">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFE39</Default>\r
+ <Desc>HCIPP HW Reset</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Run_Long_Self_Test" type="sc" opcode="0xfe32">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFE32</Default>\r
+ <Desc>HCIPP Run Long Seflf Test</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Get_Rf_Meters" type="sc" opcode="0xfe1e">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFE1E</Default>\r
+ <Desc>HCIPP Get Rf Meters</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Read_Stream_from_EEPROM" type="sc" opcode="0xff84">\r
+ \r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFF84</Default>\r
+ <Desc>HCIPP Read Stream from EEPROM</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Address</Name>\r
+ <Default>0x00000000</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Size</Name>\r
+ <Default>01</Default>\r
+ <Desc>1-200</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Param1_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Write_Stream_to_EEPROM" type="sc" opcode="0xff85">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFF85</Default>\r
+ <Desc>HCIPP Write Stream to EEPROM</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Address</Name>\r
+ <Default>0x00000000</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Size</Name>\r
+ <Default>04</Default>\r
+ <Desc>1-200</Desc>\r
+ </Param>\r
+ <Param type="x" size="200">\r
+ <Name>Values</Name>\r
+ <Default>"0000"</Default>\r
+ <Desc>stream in hex, from left to right</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Read_Error_Statistics" type="sc" opcode="0xFF93">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFF93</Default>\r
+ <Desc>HCIPP_READ_ERROR_STATISTICS</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Request </Name>\r
+ <Default>3</Default>\r
+ <Desc>1 - BER, 2 - PER, 3 - Both</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Handle </Name>\r
+ <Default>0</Default>\r
+ <Desc> </Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1" valtype="Status">\r
+ <Name>Status</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>Status</Desc>\r
+ </Param>\r
+ <Param type="x" size="10">\r
+ <Name>Data</Name>\r
+ <Default>Any</Default>\r
+ </Param>\r
+ \r
+</Command>\r
+\r
+<Command name="HCI_VS_TestMode_Override_PowerControl" type="sc" opcode="0xfe05">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFE05</Default>\r
+ <Desc>HCIPP TestMode Override PowerControl</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Power_Control_Override</Name>\r
+ <Default>1</Default>\r
+ <Desc>If TRUE, power control commands will never be ignored in Test Mode. 1=TRUE, 0=FALSE</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_CDC_Enable" type="sc" opcode="0xff71">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFF71</Default>\r
+ <Desc>HCIPP CDC Enable</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Enable CDC</Name>\r
+ <Default>0x0</Default>\r
+ <Desc>1- Enable, 0- Disable</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Set_Classification_Req_Params" type="sc" opcode="0xff3a">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFF3A</Default>\r
+ <Desc>HCIPP Set AFH Classification Req Parameters</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Classification Req Mode</Name>\r
+ <Default>1</Default>\r
+ <Desc>0-Disable, 1-Enable</Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Classification Req Min Interval</Name>\r
+ <Default>0x1F40</Default>\r
+ <Desc>slots (0-30 sec)</Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Classification Req Max Interval</Name>\r
+ <Default>0x3E80</Default>\r
+ <Desc>slots (0-30 sec)</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Scan_All_Stacks" type="sc" opcode="0xff63">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFF63</Default>\r
+ <Desc>HCIPP Scan All Stacks</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Mode</Name>\r
+ <Default>0</Default>\r
+ <Desc>0 - Print , 1 - Enable ; You must call this command with 'Enable' before ever entering deep sleep.</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Scan_All_Buffers" type="sc" opcode="0xff64">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFF64</Default>\r
+ <Desc>HCIPP Scan All Buffers</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Write_Inquiry_Scan_Mode" type="sc" opcode="0xff65">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFF65</Default>\r
+ <Desc>HCIPP Write Inquiry Scan Mode</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Scanning Mode</Name>\r
+ <Default>0x10</Default>\r
+ <Desc>0x00 - Chain Mode, 0x01 - Distributed Mode, 0x10 - Default Mode</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Measure_CPU_Idle_Time" type="sc" opcode="0xff67">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFF67</Default>\r
+ <Desc>HCIPP Measure CPU Idle Time</Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Time</Name>\r
+ <Default>80</Default>\r
+ <Desc>0-Enter CPU test mode , 1-Exit CPU test mode, other - start and check for "param" BT Frames</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Self_Test_Result" type="sc" opcode="0xff37">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFF37</Default>\r
+ <Desc>HCIPP Self Test Result</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Send_LMP_Frame" type="sc" opcode="0xFF16">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFF16</Default>\r
+ <Desc>HCIPP Send LMP Frame</Desc>\r
+ </Param>\r
+ <Param type="h" size="2">\r
+ <Name>Connection Handle</Name>\r
+ <Default>0x0001</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Length</Name>\r
+ <Default>1</Default>\r
+ <Desc>Number of bytes for the inserted parameters (excluding the opcode)</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>LMP Opcode</Name>\r
+ <Default>31</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Trans started by slave</Name>\r
+ <Default>0</Default>\r
+ <Desc>0- Master initiate, 1- Slave initiate</Desc>\r
+ </Param>\r
+ <Param type="x" size="30">\r
+ <Name>Parameters</Name>\r
+ <Default>"00"</Default>\r
+ <Desc>If a parameter is longer than 1 byte, the bytes order should be reverse for that param.</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Send_LMP_Frame_Extended" type="sc" opcode="0xfe00">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFE00</Default>\r
+ <Desc>HCIPP Send LMP Frame Extended</Desc>\r
+ </Param>\r
+ <Param type="h" size="2">\r
+ <Name>Connection Handle</Name>\r
+ <Default>0x0001</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Length</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>number of bytes for the inserted parameters, including lmp ext opcode</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>lmp opcode</Name>\r
+ <Default>0x7F</Default>\r
+ <Desc>must enter a value between 124-127</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>lmp ext opcode</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>lmp opcode must be between 124-127 for usage of this field</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>trans started by slave</Name>\r
+ <Default>0x0</Default>\r
+ <Desc>0- master initiate, 1- slave initiate</Desc>\r
+ </Param>\r
+ <Param type="x" size="30">\r
+ <Name>params</Name>\r
+ <Default>"0000"</Default>\r
+ <Desc>if parameter is longer than 1 byte, the bytes order should be revrse for that param.</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Set_LM_Bypass" type="sc" opcode="0xff18">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFF18</Default>\r
+ <Desc>HCIPP Set LM Bypass</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>new value</Name>\r
+ <Default>01</Default>\r
+ <Desc>0- normal, 1-bypass LM when receiving LMPs</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Set_LBT" type="sc" opcode="0xff0f">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFF0F</Default>\r
+ <Desc>HCIPP Set LBT</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Clock Value</Name>\r
+ <Default>0x3FF447F</Default>\r
+ <Desc>0-min, 0x3FFFFFF -max</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Set_Whitening_Mode" type="sc" opcode="0xff0a">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFF0A</Default>\r
+ <Desc>HCIPP Set Whitening Mode</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Whitening Mode</Name>\r
+ <Default>01</Default>\r
+ <Desc>0-enable, 1-disable</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_RX_RX_Debug_enable_parameters" type="vc" opcode="0xFDE9">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name> \r
+ <Default>0xFDE9</Default> \r
+ <Desc>This command enables RXRX in debug mode</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>RxRx enable source</Name>\r
+ <Default>00</Default>\r
+ <Desc>0x0 - RXRX enable source is WLAN, 0x01 - RXRX enable source is Vs command, 0xFF - Don\92t Change</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>RxRx mode</Name>\r
+ <Default>00</Default>\r
+ <Desc>0x0 - RXRX is disabled-relevant only if RXRX enable source is Vs command, 0x01 - RXRX is enabled-relevant only if RXRX enable source is Vs command, 0xFF - Don't change</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>WLAN Force calibrations</Name> \r
+ <Default>00</Default> \r
+ <Desc>0x0 - Calibration values are taken from WLAN, 0x1 - Calibration values are taken from USER, 0xFFDon't Change</Desc> \r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>RXRX PM Enable Disable on sleep feature</Name> \r
+ <Default>00</Default> \r
+ <Desc>0x0 - RXRX PM sequences on sleep are disabled, 0x1 - RXRX PM sequences on sleep are enabled, 0xFFDon't Change</Desc> \r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>User_calibration_info_0</Name> \r
+ <Default>0000</Default> \r
+ <Desc>1st user data for calibration values</Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>User_calibration_info_1</Name> \r
+ <Default>0000</Default> \r
+ <Desc>2nd user data for calibration values</Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>User_calibration_info_2</Name> \r
+ <Default>0000</Default> \r
+ <Desc>3rd user data for calibration values</Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>User_calibration_info_3</Name> \r
+ <Default>0000</Default> \r
+ <Desc>4th user data for calibration values</Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>User_calibration_info_4</Name> \r
+ <Default>0000</Default> \r
+ <Desc>5th user data for calibration values</Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>User_calibration_info_5</Name> \r
+ <Default>0000</Default> \r
+ <Desc>6th user data for calibration values</Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>User_calibration_info_6</Name> \r
+ <Default>0000</Default> \r
+ <Desc>7th user data for calibration values</Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>User_calibration_info_7</Name> \r
+ <Default>0000</Default> \r
+ <Desc>8th user data for calibration values</Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>User_calibration_info_8</Name> \r
+ <Default>0000</Default> \r
+ <Desc>9th user data for calibration values</Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>User_calibration_info_9</Name> \r
+ <Default>0000</Default> \r
+ <Desc>10th user data for calibration values</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Reserved</Name>\r
+ <Default>00</Default>\r
+ <Desc>Reserved parameter for any additional debug use</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Rx_Rx_Mode" type="vc" opcode="0xFDF8">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name> \r
+ <Default>0xFDF8</Default> \r
+ <Desc>This command enables/disables RXRX mode</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>RxRx mode</Name>\r
+ <Default>00</Default>\r
+ <Desc>0x0 - Rx_Rx disable, 0x01 - Rx_Rx_enable, 0xFF - Don't change</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Rx_Rx BT standelone</Name>\r
+ <Default>00</Default>\r
+ <Desc>0x0 - not Stanalone mode, 0x01 - Standalone mode, 0xFF - Don't change</Desc>\r
+ </Param>\r
+</Command>\r
+ \r
+<Command name="HCI_VS_LOAD_Cortex" type="vc" opcode="0xFDA8">\r
+ <Cat>Wibree</Cat>\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFDA8</Default>\r
+ <Desc>Load Cortex</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="EnableDisable">\r
+ <Name>Mode</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>0x01 = Disable Cortex Sleep</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Write_Memory_Block_To_DTST_Mem" type="sc" opcode="0xFD97">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFD97</Default>\r
+ <Desc>HCIPP Write Memory Block To DTST Mem</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Address</Name>\r
+ <Default>0x00190200</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1" label="len">\r
+ <Name>Size</Name>\r
+ <Default>04</Default>\r
+ <Desc>1-200</Desc>\r
+ </Param>\r
+ <Param type="x" size="len">\r
+ <Name>Values</Name>\r
+ <Default>"00000000"</Default>\r
+ <Desc>Data starts from left to right</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Read_Memory_Block_From_DTST" type="sc" opcode="0xFD7F">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFD7F</Default>\r
+ <Desc>HCIPP Read Memory Block From DTST Mem</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Address</Name>\r
+ <Default>0x00190200</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1" label="len">\r
+ <Name>Size</Name>\r
+ <Default>04</Default>\r
+ <Desc>1-200</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="Status">\r
+ <Name>Status</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>Status</Desc>\r
+ </Param>\r
+ <Param type="x" size="packet_remain">\r
+ <Name>Data</Name>\r
+ <Desc>any</Desc>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Config_Power_Mng_Params" type="sc" opcode="0xFD58">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFD58</Default>\r
+ <Desc>HCIPP Config Power Mng Params</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Enable flag</Name>\r
+ <Default>1</Default>\r
+ <Desc>When set to 1, indicates enabling of power management algorithm</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>rssi_thl_acl (dBm) </Name>\r
+ <Default>-50</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>rssi_thl_sco (dBm) </Name>\r
+ <Default>-50</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>rssi_thl_edr3 (dBm) </Name>\r
+ <Default>-50</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>rssi_thh_acl (dBm) </Name>\r
+ <Default>-30</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>rssi_thh_sco (dBm) </Name>\r
+ <Default>-30</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>rssi_thh_edr3 (dBm) </Name>\r
+ <Default>-30</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>rssi_vhth (dBm) </Name>\r
+ <Default>-20</Default>\r
+ <Desc />\r
+ </Param>\r
+ \r
+ <Param type="u" size="1">\r
+ <Name>rssi_vhth_edr3 (dBm) </Name>\r
+ <Default>-20</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>rssi_th_sensitivity</Name>\r
+ <Default>-80</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>snr_thl</Name>\r
+ <Default>0</Default>\r
+ <Desc>0 - disable SNR condition.</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>snr_edr3_thl</Name>\r
+ <Default>0</Default>\r
+ <Desc>0 - disable SNR condition.</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>snr_thh</Name>\r
+ <Default>0</Default>\r
+ <Desc>0 - disable SNR condition.</Desc>\r
+ </Param>\r
+ \r
+ <Param type="u" size="1">\r
+ <Name>snr_edr3_thh</Name>\r
+ <Default>0</Default>\r
+ <Desc>0 - disable SNR condition.</Desc>\r
+ </Param>\r
+ \r
+ <Param type="u" size="1">\r
+ <Name>bad_sync_count_th_sco</Name>\r
+ <Default>3</Default>\r
+ <Desc /> Used for SCO connection as threshold for req. in/decrease power.\r
+ </Param>\r
+ \r
+ <Param type="u" size="1">\r
+ <Name>fec_ration_thl_sco</Name>\r
+ <Default>150</Default>\r
+ <Desc> Threshold for req. decrease power in case of bad HEC. (bad_headers/Headers) < (1/fec_ration_thl_sco) </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>fec_ration_thh_sco</Name>\r
+ <Default>100</Default>\r
+ <Desc> Threshold for req. increase power in case of bad HEC. (bad_headers/Headers) > (1/fec_ration_thh_sco) </Desc>\r
+ </Param>\r
+ \r
+ <Param type="u" size="2">\r
+ <Name>fec_min_headers_acl</Name>\r
+ <Default>8</Default>\r
+ <Desc> Minimum number of Headers to calculate HEC statistics for e/SCO connection</Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>fec_min_headers_sco</Name>\r
+ <Default>8</Default>\r
+ <Desc> Minimum number of Headers to calculate HEC statistics for ACL connection</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>crc_ratio_thl_acl</Name>\r
+ <Default>60</Default>\r
+ <Desc> Threshold for req. decrease power in case of bad_crc. (bad_crc/(bad_crc + good_crc)) < (1/crc_ratio_thl_acl) </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>crc_ratio_thh_acl</Name>\r
+ <Default>10</Default>\r
+ <Desc> Threshold for req. increase power in case of bad_crc. (bad_crc/(bad_crc + good_crc)) > (1/crc_ratio_thh_acl) </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>crc_min_pkts_acl</Name>\r
+ <Default>25</Default>\r
+ <Desc>Minimum number of packets to calculate CRC statistics</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>power_decision_time</Name>\r
+ <Default>2</Default>\r
+ <Desc>The interval, in which a decision is made whether to increase/decrease or not to change peer tx power (decision interval = power_decision_time x100ms)</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>power_acl_response_time</Name>\r
+ <Default>1</Default>\r
+ <Desc>On ACL channel the minimal delay between the last command requested to increase power or decrease to the command request to increase power (delay interval = power_decision_time x power_response_time x 100ms)</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>power_sco_response_time</Name>\r
+ <Default>1</Default>\r
+ <Desc>On E/SCO channel the minimal delay between the last command requested to increase power or decrease to the command request to increase power (delay interval = power_decision_time x power_response_time x 100ms)</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>power_edr3_response_time</Name>\r
+ <Default>1</Default>\r
+ <Desc>On EDR3 channel the minimal delay between the last command requested to increase power or decrease to the command request to increase power (delay interval = power_decision_time x power_response_time x 100ms)</Desc>\r
+ </Param>\r
+ \r
+ <Param type="u" size="1">\r
+ <Name>power_delay_time</Name>\r
+ <Default>20</Default>\r
+ <Desc>The minimal delay between the last command requested to increase power or decrease to the command request to decrease power (delay interval = power_delay_time x power_decision_time x 100ms)</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>deep_fade_rssi_delta1 (dBm)</Name>\r
+ <Default>-10</Default>\r
+ <Desc>rssi threshold between current measure and the previews measure to make decision if we in deep fade.(delta2 = rssi[N] - rssi[N-1]) </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>deep_fade_rssi_delta2 (dBm)</Name>\r
+ <Default>-20</Default>\r
+ <Desc>rssi threshold between current measure and the one before the preview measure to make decision if we in deep fade.(delta2 = rssi[N] - rssi[N-2])</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>deep_fade_edr3_rssi_delta1 (dBm)</Name>\r
+ <Default>-10</Default>\r
+ <Desc>rssi threshold between current measure and the previews measure to make decision if we in deep fade.(delta2 = rssi[N] - rssi[N-1] </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>deep_fade_edr3_rssi_delta2 (dBm)</Name>\r
+ <Default>-20</Default>\r
+ <Desc>rssi threshold between current measure and the one before the preview measure to make decision if we in deep fade.(delta2 = rssi[N] - rssi[N-2])</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_DRPb_Set_RF_Calibration_Info" type="sc" opcode="0xFD76">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFD76</Default>\r
+ <Desc>HCI VS DRPb set RF calibration info</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Reserved</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>Reserved Parameter</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" valtype="RF_Calibration_DRPb_Bitmap">\r
+ <Name>Short calibration indication</Name>\r
+ <Default>0x00005421</Default>\r
+ <Desc>Checked box = short calibration, Unchecked box = not short calibration; 0x0000-0xFFFF: short calibration bitmap, 0xFFFFFFFF: Keep last bitmap.</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" valtype="RF_Calibration_DRPb_Bitmap">\r
+ <Name>Calibrations with antenna</Name>\r
+ <Default>0x00005761</Default>\r
+ <Desc>Checked box = use antenna, Unchecked box = don't use antenna; 0x0000-0xFFFF: antenna bitmap, 0xFFFFFFFF: Keep last bitmap.</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>SD delay in ms</Name>\r
+ <Default>20</Default>\r
+ <Desc>Trigger same calibration in [x] ms in case of non successive attempt due to shut-down</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Num of SD attempts</Name>\r
+ <Default>5</Default>\r
+ <Desc>Maximum number of additional non successive attempts due to shut-down during calibration process</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Interference delay_ms</Name>\r
+ <Default>10</Default>\r
+ <Desc>Trigger same calibration in [x] ms in case of non successive attempt due to general interference</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Num of calib interf attempts</Name>\r
+ <Default>5</Default>\r
+ <Desc>Maximum number of additional non successive attempts due to general interference during calibration process</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #1</Name>\r
+ <Default>00</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #2</Name>\r
+ <Default>07</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #3</Name>\r
+ <Default>06</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #4</Name>\r
+ <Default>10</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #5</Name>\r
+ <Default>04</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #6</Name>\r
+ <Default>05</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #7</Name>\r
+ <Default>08</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #8</Name>\r
+ <Default>09</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #9</Name>\r
+ <Default>11</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #10</Name>\r
+ <Default>12</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #11</Name>\r
+ <Default>13</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #12</Name>\r
+ <Default>14</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #13</Name>\r
+ <Default>255</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #14</Name>\r
+ <Default>255</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #15</Name>\r
+ <Default>255</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #16</Name>\r
+ <Default>255</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #17</Name>\r
+ <Default>255</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #18</Name>\r
+ <Default>255</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #19</Name>\r
+ <Default>255</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #20</Name>\r
+ <Default>255</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #21</Name>\r
+ <Default>255</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #22</Name>\r
+ <Default>255</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #23</Name>\r
+ <Default>255</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #24</Name>\r
+ <Default>255</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #25</Name>\r
+ <Default>255</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #26</Name>\r
+ <Default>255</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #27</Name>\r
+ <Default>255</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #28</Name>\r
+ <Default>255</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #29</Name>\r
+ <Default>255</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #30</Name>\r
+ <Default>255</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #31</Name>\r
+ <Default>255</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RF_Calibrations">\r
+ <Name>Calibration #32</Name>\r
+ <Default>255</Default>\r
+ <Desc>Calibrations order</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" >\r
+ <Name>Reserved</Name>\r
+ <Default>0</Default>\r
+ <Desc>Reserved</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<!-- ================================================================== -->\r
+<Command name="ACL Macroes" type="gb" />\r
+<!-- ================================================================== -->\r
+<Command name="HCI_ACL_Data" type="cc">\r
+ <Cat>Spec 1.1</Cat>\r
+ \r
+ <Macro><![CDATA[\r
+ _handle_ = %1\r
+ _text_ = %2\r
+ _bdry_ = %3\r
+ _brdcst_ = %4\r
+\r
+ _size_ = size(_text_)\r
+\r
+ _handle_ |= (((_bdry_ & 3)<<12) | ((_brdcst_ & 3) << 14))\r
+\r
+ _data_ = todata(2, 1)\r
+ _data_ += todata(_handle_, 2)\r
+\r
+ if (g_bACL_L2CAP) then \r
+ _data_ += todata(_size_, 2)\r
+ _data_ += _text_\r
+ else\r
+ _data_ += todata(_size_+4, 2)\r
+ _data_ += todata(_size_, 2)\r
+ _data_ += todata(0xDAD1, 2)\r
+ _data_ += _text_\r
+ end if\r
+\r
+ WritePort _data_\r
+\r
+]]></Macro>\r
+ \r
+ <Param type="h" size="2" bits="12" label="handle">\r
+ <Name>Connection Handle</Name>\r
+ <Default>Handle</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s" label="data">\r
+ <Name>Text</Name>\r
+ <Default>"Hello World"</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="2" bits="2" valtype="BoundaryPacketTypes">\r
+ <Name>Boundary</Name>\r
+ <Default>0x02</Default>\r
+ <Desc>0-Start Non-Flushable 1-Continuation 2-Start Flushable</Desc>\r
+ </Param>\r
+ <Param type="u" size="2" bits="2" valtype="BroadcastTypes">\r
+ <Name>Broadcast flag</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>0-No broadcast 1-active 2-all</Desc>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_ACL_Data_Event" type="ce">\r
+ <Cat>Spec 1.1</Cat>\r
+ \r
+ <Macro><![CDATA[\r
+ _timeout_ = %1\r
+ _handle_ = %2\r
+ _bdry_ = %3\r
+ _text_ = %4\r
+ _brdcst_ = %5\r
+\r
+ _size_ = size(_text_)\r
+\r
+ Wait_HCI_ACL_Packet_Event _timeout_, _handle_, _bdry_, _brdcst_, &_data_\r
+\r
+ if (!g_bACL_L2CAP) then\r
+ # discard the L2CAP part\r
+ _data_ = mid(_data_, 4)\r
+ end if\r
+\r
+ if 0 != strcomp(_text_, _data_) then\r
+ Fail "Text mismatch. Expected: \"%s\", Got: \"%s\"", _text_, str(_data_)\r
+ end if\r
+\r
+]]></Macro>\r
+ \r
+ <Param type="t">\r
+ <Name>Timeout</Name>\r
+ <Default>5000</Default>\r
+ <Desc>Time in msec</Desc>\r
+ </Param>\r
+ <Param type="u">\r
+ <Name>Connection Handle</Name>\r
+ <Default>Handle</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" valtype="BoundaryTypes">\r
+ <Name>Boundary</Name>\r
+ <Default>0x02</Default>\r
+ <Desc>0-Start Non-Flushable 1-Continuation 2-Start Flushable</Desc>\r
+ </Param>\r
+ <Param type="s">\r
+ <Name>Data</Name>\r
+ <Default>"Hello World"</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1" valtype="BroadcastTypes">\r
+ <Name>Broadcast flag</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>0-No broadcast 1-active 2-all</Desc>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_L2CAP_Packet_Data" type="sc" prop="h">\r
+ <Cat>Spec 1.1</Cat>\r
+ \r
+ <Macro><![CDATA[\r
+ _handle_ = %1\r
+ _cid_ = %2\r
+ _data_ = %3\r
+ _brdcst_ = %4\r
+\r
+ # Only on init\r
+ if _acl_size_ > 0 && _acl_count_ > 0 then\r
+ # Already set, Do nothing\r
+ else\r
+ _acl_size_ = 0\r
+ _acl_count_ = 0\r
+ _acl_available_ = 0\r
+ end if\r
+\r
+ # Make sure we have the size of ACL packets and the buffers count\r
+ if _acl_size_ == 0 || _acl_count_ == 0 then\r
+ Send_HCI_Read_Buffer_Size\r
+ Wait_HCI_Command_Complete_Read_Buffer_Size_Event 5000, any, HCI_Read_Buffer_Size, 0, &_acl_size_, any, &_acl_count_, any\r
+ end if\r
+\r
+ # If still no information the error\r
+ if _acl_size_ == 0 || _acl_count_ == 0 then\r
+ Fail "ACL Buffer Size Error"\r
+ end if\r
+\r
+ _acl_available_ = _acl_count_\r
+\r
+ # Create the whole payload (to be splited later for each ACL\r
+ _data_ = todata(size(_data_), 2) + todata(_cid_,2) + todata(_data_)\r
+ _size_ = size(_data_)\r
+\r
+ _pos_ = 0\r
+ _segment_ = _acl_size_\r
+\r
+ if _segment_ > 0 then\r
+ while _pos_ < _size_\r
+ \r
+ # Loop on all free buffers available\r
+ while _pos_ < _size_ && _acl_available_ > 0\r
+ abPayload = mid(_data_, _pos_, _segment_)\r
+ Send_HCI_ACL_Packet _handle_, _pos_==0 ? 2 : 1, _brdcst_, todata(abPayload)\r
+ _pos_ += _segment_\r
+ _acl_available_--\r
+ wend\r
+ \r
+ Wait_HCI_Number_Of_Completed_Packets_Event 45000, 0x01, _handle_, &_freed_\r
+ _acl_available_ += _freed_\r
+ wend\r
+ \r
+ # Wait for all completed events that still need to come up \r
+ while _acl_available_ < _acl_count_\r
+ Wait_HCI_Number_Of_Completed_Packets_Event 45000, 0x01, _handle_, &_freed_\r
+ _acl_available_ += _freed_\r
+ wend\r
+ end if\r
+]]></Macro>\r
+ \r
+ <Param type="u">\r
+ <Name>Connection Handle</Name>\r
+ <Default>Handle</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u">\r
+ <Name>CID</Name>\r
+ <Default>0xDAD1</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="x">\r
+ <Name>Data</Name>\r
+ <Default>"Hello World"</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" valtype="BroadcastTypes">\r
+ <Name>Broadcast flag</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>0-No broadcast 1-active 2-all</Desc>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_L2CAP_Packet" type="sc">\r
+ <Cat>Spec 1.1</Cat>\r
+ \r
+ <Macro><![CDATA[\r
+ _handle_ = %1\r
+ _cid_ = %2\r
+ _data_ = %3\r
+ _brdcst_ = %4\r
+\r
+ # Only on init\r
+ if _acl_size_ > 0 && _acl_count_ > 0 then\r
+ # Already set, Do nothing\r
+ else\r
+ _acl_size_ = 0\r
+ _acl_count_ = 0\r
+ _acl_available_ = 0\r
+ end if\r
+\r
+ # Make sure we have the size of ACL packets and the buffers count\r
+ if _acl_size_ == 0 || _acl_count_ == 0 then\r
+ Send_HCI_Read_Buffer_Size\r
+ Wait_HCI_Command_Complete_Read_Buffer_Size_Event 5000, any, HCI_Read_Buffer_Size, 0, &_acl_size_, any, &_acl_count_, any\r
+ end if\r
+\r
+ # If still no information the error\r
+ if _acl_size_ == 0 || _acl_count_ == 0 then\r
+ Fail "ACL Buffer Size Error"\r
+ end if\r
+\r
+ _acl_available_ = _acl_count_\r
+\r
+ # Create the whole payload (to be splited later for each ACL\r
+ _data_ = todata(size(_data_)+1, 2) + todata(_cid_,2) + todata(_data_) + todata(0, 1)\r
+ _size_ = size(_data_)\r
+\r
+ _pos_ = 0\r
+ _segment_ = _acl_size_\r
+\r
+ if _segment_ > 0 then\r
+ while _pos_ < _size_\r
+ \r
+ # Loop on all free buffers available\r
+ while _pos_ < _size_ && _acl_available_ > 0\r
+ abPayload = mid(_data_, _pos_, _segment_)\r
+ Send_HCI_ACL_Packet _handle_, _pos_==0 ? 2 : 1, _brdcst_, todata(abPayload)\r
+ _pos_ += _segment_\r
+ _acl_available_--\r
+ wend\r
+ \r
+ Wait_HCI_Number_Of_Completed_Packets_Event 45000, 0x01, _handle_, &_freed_\r
+ _acl_available_ += _freed_\r
+ wend\r
+ \r
+ # Wait for all completed events that still need to come up \r
+ while _acl_available_ < _acl_count_\r
+ Wait_HCI_Number_Of_Completed_Packets_Event 45000, 0x01, _handle_, &_freed_\r
+ _acl_available_ += _freed_\r
+ wend\r
+ end if\r
+]]></Macro>\r
+ \r
+ <Param type="u">\r
+ <Name>Connection Handle</Name>\r
+ <Default>Handle</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u">\r
+ <Name>CID</Name>\r
+ <Default>0xDAD1</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s">\r
+ <Name>Text</Name>\r
+ <Default>"Hello World"</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" valtype="BroadcastTypes">\r
+ <Name>Broadcast flag</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>0-No broadcast 1-active 2-all</Desc>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_L2CAP_Packet_Event" type="se">\r
+ <Cat>Spec 1.1</Cat>\r
+ \r
+ <Macro><![CDATA[\r
+ _timeout_ = %1\r
+ _handle_ = %2\r
+ _cid_ = %3\r
+ _text_ = %4\r
+\r
+ _size_ = size(_text_)\r
+ _got_ = 0\r
+\r
+ while _got_ < _size_\r
+ Wait_HCI_ACL_Packet_Event _timeout_, _handle_, _got_==0 ? 2 : 1, any, &_data_\r
+\r
+ if (_got_==0) then\r
+ \r
+ # Match CID\r
+ _cidin_ = val(mid(_data_, 2, 2))\r
+ if _cid_ != _cidin_ then\r
+ Fail "CID mismatch. Expected: 0x%04x, Got: 0x%04x", _cid_, _cidin_\r
+ end if\r
+\r
+ _whole_ = mid(_data_, 4)\r
+ _got_ += size(_data_) - 4\r
+ \r
+ else\r
+ \r
+ _whole_ += _data_\r
+ _got_ += size(_data_)\r
+ \r
+ end if\r
+\r
+ wend\r
+\r
+ # Match text\r
+ if 0 != strcomp(_text_, _whole_) then\r
+ Fail "Text mismatch. Expected: \"%s\", Got: \"%s\"", _text_, str(_whole_)\r
+ end if\r
+\r
+]]></Macro>\r
+ \r
+ <Param type="t">\r
+ <Name>Timeout</Name>\r
+ <Default>5000</Default>\r
+ <Desc>Time in msec to wait for the event</Desc>\r
+ </Param>\r
+ <Param type="u">\r
+ <Name>Connection Handle</Name>\r
+ <Default>Handle</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u">\r
+ <Name>CID</Name>\r
+ <Default>0xDAD1</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s">\r
+ <Name>Text</Name>\r
+ <Default>"Hello World"</Default>\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_ACL_Data_Types" type="sc">\r
+ <Cat>Spec 1.1</Cat>\r
+ \r
+ <Macro><![CDATA[\r
+ _handle_ = %1\r
+ _type_ = %2\r
+ _path_ = %3\r
+ _bdry_ = %4\r
+ _brdcst_ = %5\r
+ _fmt_ = %6\r
+\r
+ If _type_==1 Then\r
+ Send_HCI_ACL_L2CAP_Text _handle_, _bdry_, _brdcst_, 0xDad1, _path_\r
+ Else\r
+ # Extract the file name without the path\r
+ _pos_ = InStrRev(_path_, "\\")\r
+ \r
+ if (_pos_ >= 0) then\r
+ _name_ = mid(_path_, _pos_+1)\r
+ else\r
+ _name_ = _path_\r
+ end if\r
+ \r
+ if _fmt_==2 then\r
+ LoadFile _FileData_, _path_\r
+ _size_ = size(_FileData_)\r
+ Send_HCI_L2CAP_Packet_Data _handle_, 0xDA00, todata(_name_) + todata(0, 1) + _FileData_, _brdcst_\r
+ else\r
+ # Only on init\r
+ if _acl_size_ > 0 && _acl_count_ > 0 then\r
+ # Already set, Do nothing\r
+ else\r
+ _acl_size_ = 0\r
+ _acl_count_ = 0\r
+ _acl_available_ = 0\r
+ end if\r
+ \r
+ # Make sure we have the size of ACL packets and the buffers count\r
+ if _acl_size_ == 0 || _acl_count_ == 0 then\r
+ Send_HCI_Read_Buffer_Size\r
+ Wait_HCI_Command_Complete_Read_Buffer_Size_Event 5000, any, HCI_Read_Buffer_Size, 0, &_acl_size_, any, &_acl_count_, any\r
+ end if\r
+ \r
+ # If still no information the error\r
+ if _acl_size_ == 0 || _acl_count_ == 0 then\r
+ Fail "ACL Buffer Size Error"\r
+ end if\r
+ \r
+ _acl_available_ = _acl_count_\r
+ \r
+ ##############################\r
+ # Write Header\r
+ ##############################\r
+ \r
+ LoadFile _FileData_, _path_\r
+ \r
+ _size_ = size(_FileData_)\r
+ abHeaderData = todata(_size_, 4) + todata(_name_) + todata(0, 1)\r
+ \r
+ Send_HCI_ACL_L2CAP_Data _handle_, _bdry_, _brdcst_, 0xDada, abHeaderData\r
+ \r
+ _acl_available_--\r
+ _pos_ = 0\r
+ _segment_ = _acl_size_ - 4\r
+ \r
+ if _segment_ > 0 then\r
+ while _pos_ < _size_\r
+ \r
+ # Loop on all free buffers available\r
+ while _pos_ < _size_ && _acl_available_ > 0\r
+ abPayload = mid(_FileData_, _pos_, _segment_)\r
+ Send_HCI_ACL_L2CAP_Data _handle_, _bdry_, _brdcst_, 0xDada, abPayload\r
+ _pos_ += _segment_\r
+ _acl_available_--\r
+ wend\r
+ \r
+ Wait_HCI_Number_Of_Completed_Packets_Event 45000, 0x01, _handle_, &_freed_\r
+ _acl_available_ += _freed_\r
+ WEnd\r
+ \r
+ # Wait for all completed events that still need to come up \r
+ while _acl_available_ < _acl_count_\r
+ Wait_HCI_Number_Of_Completed_Packets_Event 45000, 0x01, _handle_, &_freed_\r
+ _acl_available_ += _freed_\r
+ WEnd\r
+ End If\r
+ End If\r
+ End If\r
+]]></Macro>\r
+ \r
+ <Param type="u">\r
+ <Name>Connection Handle</Name>\r
+ <Default>Handle</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" valtype="ACLSendType" label="type">\r
+ <Name>Type</Name>\r
+ <Default>0</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s" cond="type==0">\r
+ <Name>File Path</Name>\r
+ <Default>""</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s" cond="type!=0">\r
+ <Name>Text</Name>\r
+ <Default>"Hello World"</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" valtype="BoundaryTypes">\r
+ <Name>Boundary</Name>\r
+ <Default>0x02</Default>\r
+ <Desc>1-Continuation 2-Start</Desc>\r
+ </Param>\r
+ <Param type="u" valtype="BroadcastTypes">\r
+ <Name>Broadcast flag</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>0-No broadcast 1-active 2-all</Desc>\r
+ </Param>\r
+ <Param type="u" valtype="L2CAPFmt">\r
+ <Name>Format</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>0-UPF 1-HCICommander 2-L2CAP</Desc>\r
+ </Param>\r
+</Command>\r
+\r
+<!-- ================================================================== -->\r
+<Command name="DOT events" type="gb" />\r
+<!-- ================================================================== -->\r
+\r
+<Command name="DOT_STT_Data_Event" type="DOT_STT_Event" opcode="0x0001">\r
+ <Param type="t">\r
+ <Name>Timeout</Name>\r
+ <Default>5000</Default>\r
+ <Desc>Time in msec to wait for the event</Desc>\r
+ </Param>\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0x01</Default>\r
+ <Desc>get statistics string</Desc>\r
+ </Param>\r
+ <Param type="s" size="30">\r
+ <Name>handle</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s" size="30">\r
+ <Name>TX rate (bit/sec)</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s" size="30">\r
+ <Name>RX rate (bit/sec)</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s" size="30">\r
+ <Name>TX packets (Since prv msg)</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s" size="30">\r
+ <Name>RX packets (Since prv msg)</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s" size="30">\r
+ <Name>RX ERR packets (Since prv msg)</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s" size="75">\r
+ <Name>notes</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_STT_Assert_Event" type="DOT_STT_Event" opcode="0x0002">\r
+ <Param type="t">\r
+ <Name>Timeout</Name>\r
+ <Default>5000</Default>\r
+ <Desc>Time in msec to wait for the event</Desc>\r
+ </Param>\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0x02</Default>\r
+ <Desc>assert</Desc>\r
+ </Param>\r
+ <Param type="s" size="80">\r
+ <Name>ASSERT</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s" size="80">\r
+ <Name>File</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Line</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Var</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s" size="87">\r
+ <Name>File</Name>\r
+ <Default />\r
+ <Desc>Fill</Desc>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_DBG_String_Event" type="DOT_Dbg_Event" opcode="0x0001">\r
+ <Param type="t">\r
+ <Name>Timeout</Name>\r
+ <Default>5000</Default>\r
+ <Desc>Time in msec to wait for the event</Desc>\r
+ </Param>\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0x01</Default>\r
+ <Desc>get debug string</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>data</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s" size="251">\r
+ <Name>string</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_DBG_String2_Event" type="DOT_Dbg_Event" opcode="0x0004">\r
+ <Param type="t">\r
+ <Name>Timeout</Name>\r
+ <Default>5000</Default>\r
+ <Desc>Time in msec to wait for the event</Desc>\r
+ </Param>\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0x04</Default>\r
+ <Desc>get debug string</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>data</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s" size="11">\r
+ <Name>string</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_DBG_Assert_Event" type="DOT_Dbg_Event" opcode="0x0002">\r
+ <Param type="t">\r
+ <Name>Timeout</Name>\r
+ <Default>5000</Default>\r
+ <Desc>Time in msec to wait for the event</Desc>\r
+ </Param>\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0x02</Default>\r
+ <Desc>assert</Desc>\r
+ </Param>\r
+ <Param type="s" size="80">\r
+ <Name>ASSERT</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s" size="80">\r
+ <Name>File</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Line</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Var</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_DBG_Response_Event" type="DOT_Dbg_Event" opcode="0x0003">\r
+ <Param type="t">\r
+ <Name>Timeout</Name>\r
+ <Default>5000</Default>\r
+ <Desc>Time in msec to wait for the event</Desc>\r
+ </Param>\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0x03</Default>\r
+ <Desc>response</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" valtype="Status">\r
+ <Name>Status</Name>\r
+ <Default>0</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s" size="80">\r
+ <Name> </Name>\r
+ <Default>any</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s" size="171">\r
+ <Name></Name>\r
+ <Default>any</Default>\r
+ <Desc>Fill</Desc>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_DBG_Data_Event" type="DOT_Dbg_Event" opcode="0x0005">\r
+ <Param type="t">\r
+ <Name>Timeout</Name>\r
+ <Default>5000</Default>\r
+ <Desc>Time in msec to wait for the event</Desc>\r
+ </Param>\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0x05</Default>\r
+ <Desc>get statistics string</Desc>\r
+ </Param>\r
+ <Param type="s" size="30">\r
+ <Name>handle</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s" size="30">\r
+ <Name>TX rate (bit/sec)</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s" size="30">\r
+ <Name>RX rate (bit/sec)</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s" size="30">\r
+ <Name>TX packets (Since prv msg)</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s" size="30">\r
+ <Name>RX packets (Since prv msg)</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s" size="30">\r
+ <Name>RX ERR packets (Since prv msg)</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+ <Param type="s" size="75">\r
+ <Name>notes</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<!-- ================================================================== -->\r
+<Command name="DOT Commands" type="gb" />\r
+<!-- ================================================================== -->\r
+\r
+<Command name="DOT_General" type="dc" opcode="0x0001">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0001</Value>\r
+ <Desc>General</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x04</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Baud rate</Name>\r
+ <Default>0 </Default>\r
+ <Desc>0=low=115.2kbps, 1=high= either 921.6kbps or 1000kbps, or type the baudrate directly.</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Reset_&_Negotiation" type="dc" opcode="0x0002">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0002</Value>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x24</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Reset BT now, Init baudrate</Name>\r
+ <Default>0</Default>\r
+ <Desc>0 = Don't Reset, baudtare = FREF/320,\r
+ 1 = Reset BT, baudtare = FREF/320, \r
+ 2 = Don't Reset, baudtare = 115200,\r
+ 3 = Reset BT, baudtare = 115200 \r
+ </Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Start Negotiation now</Name>\r
+ <Default>1</Default>\r
+ <Desc>0= No 1= Yes </Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Flow control </Name>\r
+ <Default>0</Default>\r
+ <Desc>0= Byte wise, 1= Reserved (Packet wise - Not Supported), 0x0002-0xFFFE = segmentation (segment size in bytes)</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Clock of BT device </Name>\r
+ <Default>13000000</Default>\r
+ <Desc>Hz</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Baud rate </Name>\r
+ <Default>0</Default>\r
+ <Desc>0=low=115.2kbps, 1=high= either 921.6kbps or 1000kbps, or type the baudrate directly.</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Palau spec 3.0</Name>\r
+ <Default>1</Default>\r
+ <Desc>0=old spec, 1=new (16-bit align, new negotiation, Etc.)</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Reserved (RTS pulse width)</Name>\r
+ <Default>0</Default>\r
+ <Desc>Minumum width of RTS pulse in packet wise (T5)</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Enable Deep sleep after negotiation</Name>\r
+ <Default>1</Default>\r
+ <Desc>0=Keep previous (Enb/Dis), 1=Enable, 2=Disable deep sleep after negotiation</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Padding needed </Name>\r
+ <Default>0</Default>\r
+ <Desc>0= No 1= Yes </Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Data_Generation_Configuration" type="dc" opcode="0x0003">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0003</Value>\r
+ <Desc>Data Generation Configuration</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x18</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Period of statistic message</Name>\r
+ <Default>20 </Default>\r
+ <Desc>Sec.</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Send ACL Data packets to host</Name>\r
+ <Default>0 </Default>\r
+ <Desc>0=No 1=Yes</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Order of packets</Name>\r
+ <Default>0 </Default>\r
+ <Desc>(Not supported) 0=Cyclic 1=Random. For 2 or more connections</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Read Buffer size</Name>\r
+ <Default>0 </Default>\r
+ <Desc>0=DOT sends the command, Else=Buffer size of BT</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Context of packets</Name>\r
+ <Default>0 </Default>\r
+ <Desc>0=Incremental data, 1=All bytes are zero</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>ThreshHold for statistics</Name>\r
+ <Default>0 </Default>\r
+ <Desc>0=STT_Event only, 1 and above= DBG_Event</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Host_Flow_Control" type="dc" opcode="0x0004">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0004</Value>\r
+ <Desc>TBD, Host flow Control</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x20</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Enable</Name>\r
+ <Default>1 </Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Number of host ACL buffers</Name>\r
+ <Default>5 </Default>\r
+ <Desc>0..20</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Host packet size </Name>\r
+ <Default>100 </Default>\r
+ <Desc>0..65535</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Threshold, for host_num.. </Name>\r
+ <Default>4 </Default>\r
+ <Desc>1..20, minimum number of ACL packets</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Timeout to send host_num..</Name>\r
+ <Default>2000 </Default>\r
+ <Desc>ms, 10..10000, if threhold didn't happen</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Algorithm to choose handle</Name>\r
+ <Default>0 </Default>\r
+ <Desc>0=Recived handle, 1=Round Robin</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Time between commands </Name>\r
+ <Default>0 </Default>\r
+ <Desc>Not supported</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Burst of commands </Name>\r
+ <Default>0 </Default>\r
+ <Desc>0=Normal, 1=Dot trys to send burst of commands</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event </Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Deep_Sleep" type="dc" opcode="0x0006">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0006</Value>\r
+ <Desc>Deep Sleep (Nokia Only)</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x10</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Enable deep sleep </Name>\r
+ <Default>1 </Default>\r
+ <Desc>0=Disable 1=Enable</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Minimum sleep time</Name>\r
+ <Default>0 </Default>\r
+ <Desc>ms, Minimum low time for BT_WAKEUP signal.</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Minimum awake time</Name>\r
+ <Default>0 </Default>\r
+ <Desc>ms, Minimum high time for BT_WAKEUP signal.</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Wait for cts before rising bt wakeup</Name>\r
+ <Default>0</Default>\r
+ <Desc>0=Drop and Immediate raise of BT wakeup is Alowed. 1=After Droping the bt_wakeup, Wait for RTS.</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Deep_Sleep_Motorola" type="dc" opcode="0x001B">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x001B</Value>\r
+ <Desc>Deep Sleep (Motorola Only)</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x14</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Enable deep sleep </Name>\r
+ <Default>1 </Default>\r
+ <Desc>0=Disable 1=Enable</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Minimum sleep time</Name>\r
+ <Default>0 </Default>\r
+ <Desc>ms, Minimum deassert time for BT_WAKE signal.</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Minimum awake time</Name>\r
+ <Default>0 </Default>\r
+ <Desc>ms, Minimum assert time for BT_WAKE signal.</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Polarity of BT_WAKE signal</Name>\r
+ <Default>0</Default>\r
+ <Desc>0=active low, 1=active high.</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Polarity of HOST_WAKE signal</Name>\r
+ <Default>0</Default>\r
+ <Desc>0=active low, 1=active high.</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Deep_Sleep_HCILL" type="dc" opcode="0x0010">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0010</Value>\r
+ <Desc>Deep Sleep</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x1C</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Enable and Protocol</Name>\r
+ <Default>2 </Default>\r
+ <Desc>0=Disable, 2=HCILL</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Just Sleep Time range1</Name>\r
+ <Default>0 </Default>\r
+ <Desc>ms, Minimum low time for BT_WAKEUP signal. Random LOWER range</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Just Sleep Time range2</Name>\r
+ <Default>100 </Default>\r
+ <Desc>ms, Minimum low time for BT_WAKEUP signal. Random UPPER range</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Just Wake Time range1</Name>\r
+ <Default>0 </Default>\r
+ <Desc>ms, Minimum high time for BT_WAKEUP signal. Random LOWER range</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Just Wake Time range2</Name>\r
+ <Default>100 </Default>\r
+ <Desc>ms, Minimum high time for BT_WAKEUP signal. Random UPPER range</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Delay before Wakeup Ack</Name>\r
+ <Default>0 </Default>\r
+ <Desc>ms</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Delay before Sleep Ack</Name>\r
+ <Default>0 </Default>\r
+ <Desc>ms</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Deep_Sleep_EMP" type="dc" opcode="0x0039">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0039</Value>\r
+ <Desc>Deep Sleep</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x14</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Enable and Protocol</Name>\r
+ <Default>4 </Default>\r
+ <Desc>0=Disable, 4=EMP</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Just Sleep Time lower range</Name>\r
+ <Default>0 </Default>\r
+ <Desc>ms, Minimum time that the device will be sleeping </Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Just Sleep Time upper range</Name>\r
+ <Default>100 </Default>\r
+ <Desc>ms, Minimum time that the device will be sleeping </Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Just Wake Time lower range</Name>\r
+ <Default>0 </Default>\r
+ <Desc>ms, Minimum time that the device will be awake (before setting the break indication) </Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Just Wake Time upper range</Name>\r
+ <Default>100 </Default>\r
+ <Desc>ms, Minimum time that the device will be awake (before setting the break indication)</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Write_Hardware_Register" type="dc" opcode="0x0011">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0011</Value>\r
+ <Desc>Write Hardware Register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x06</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Address </Name>\r
+ <Default>0x03007ffc</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Value </Name>\r
+ <Default>0x0000</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Read_Hardware_Register" type="dc" opcode="0x0012">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0012</Value>\r
+ <Desc>Read Hardware Register</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x04</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Address</Name>\r
+ <Default>0x03007ffc</Default>\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Configure_ARMIO" type="dc" opcode="0x0032">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0032</Value>\r
+ <Desc>Configure ARMIO Port</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x02</Value>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Port number</Name>\r
+ <Default>2</Default>\r
+ <Desc>Available IO's - 2,3,5,14</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>port direction</Name>\r
+ <Default>0x0</Default>\r
+ <Desc>1-Input, 0 -output</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Write_ARMIO_Port" type="dc" opcode="0x0036">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0036</Value>\r
+ <Desc>Write ARMIO Port</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x02</Value>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>ARMIO Port Number</Name>\r
+ <Default>2</Default>\r
+ <Desc>Available IO's - 2,3,5,14</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>ARMIO Port Level</Name>\r
+ <Default>0</Default>\r
+ <Desc>0=False, 1=True</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Read_ARMIO_Port" type="dc" opcode="0x0033">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0033</Value>\r
+ <Desc>Read ARMIO Port</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x01</Value>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>ARMIO Port Number</Name>\r
+ <Default>0</Default>\r
+ <Desc>Available IO's - 2,3,5,14</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_force_bt_wakeup" type="dc" opcode="0x0015">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0015</Value>\r
+ <Desc>Force BT wakeup signal</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x04</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Value</Name>\r
+ <Default>0</Default>\r
+ <Desc>0=low=, 1=high. Dot Deep sleep protocol must be 'Disable'</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Alive" type="dc" opcode="0x0016">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0016</Value>\r
+ <Desc>Dot will send a palau alive message to BT devive</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x04</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Period (sec)</Name>\r
+ <Default>70</Default>\r
+ <Desc>0=disable, other=period</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Generate_SCO_Data" type="dc" opcode="0x0017">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0017</Value>\r
+ <Desc>Generate_SCO_Data</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x0c</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Channel</Name>\r
+ <Default>0 </Default>\r
+ <Desc>0/1 - SCO Channel</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" valtype="SCO_generation_type">\r
+ <Name>Data Genration Type</Name>\r
+ <Default>0 </Default>\r
+ <Desc>0=Off, 1=Loopback, 2=Codec, 3=Pattern Sine, 4=Pattern Byte Saw Tooth, 5=Pattern Packet Saw Tooth</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Data Genration Rate</Name>\r
+ <Default>8000</Default>\r
+ <Desc>Rate [Bytes/sec]. Valid Params for Codec: 8000 (8KHz 8bit),\r
+ 16000 (8KHz 16bit), 24000 (8KHz 24bit), 32000 (32KHz 8bit)\r
+ </Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Configure_SCO_Data" type="dc" opcode="0x0018">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0018</Value>\r
+ <Desc>Configure_SCO_Data - The DOT executes read buffer size</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x14</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Channel</Name>\r
+ <Default>0 </Default>\r
+ <Desc>0/1 - SCO Channel</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Min SCO Buffer Threshold</Name>\r
+ <Default>30</Default>\r
+ <Desc>Min SCO Buffer threshold [bytes]</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Max SCO Buffer Threshold</Name>\r
+ <Default>30</Default>\r
+ <Desc>Max SCO Buffer threshold [bytes]</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Min SCO Packet Size</Name>\r
+ <Default>30</Default>\r
+ <Desc>Min SCO Packet Size [bytes]</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Max SCO Packet Size</Name>\r
+ <Default>30</Default>\r
+ <Desc>Max SCO Packet Size [bytes]</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Host_SCO_Flow_Control" type="dc" opcode="0x001A">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x001A</Value>\r
+ <Desc>Host SCO flow Control</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>24</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>BT Flow Control Enable</Name>\r
+ <Default>0</Default>\r
+ <Desc>1/0 - Enable/Disable Flow control from the Host to the BT</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" label="host_flow">\r
+ <Name>Host Flow Control Enable</Name>\r
+ <Default>0</Default>\r
+ <Desc>1/0 - Enable/Disable Flow control from the BT to the host</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Number of host SCO buffers</Name>\r
+ <Default>10</Default>\r
+ <Desc>0..40, DOT3: 0..6</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Host SCO buffer size</Name>\r
+ <Default>120</Default>\r
+ <Desc>0..255</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Threshold, for host_num.. </Name>\r
+ <Default>4</Default>\r
+ <Desc>1..20, minimum number of SCO buffers</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" prop="h">\r
+ <Name>Algorithm to choose handle</Name>\r
+ <Default>0</Default>\r
+ <Desc>0=Received handle, 1=Round Robin</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event </Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_H5" type="dc" opcode="0x0019">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0019</Value>\r
+ <Desc>Activate H5 protocol</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x14</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Enable</Name>\r
+ <Default>5</Default>\r
+ <Desc>5=Use H5 protocol, 4=Use H4 protocol</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Baudrate</Name>\r
+ <Default>115200</Default>\r
+ <Desc>bps</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Window size</Name>\r
+ <Default>4</Default>\r
+ <Desc>1-7</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Flow control</Name>\r
+ <Default>1</Default>\r
+ <Desc>0=None, 1=HW(cts/rts), 2=SW (xon/xoff)</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>CRC allowed</Name>\r
+ <Default>0</Default>\r
+ <Desc>0=crc is not allowed, 1=crc is allowed</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_SDIO" type="dc" opcode="0x001E">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x001E</Value>\r
+ <Desc>Activate SDIO</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x08</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>SDIO Mode</Name>\r
+ <Default>0</Default>\r
+ <Desc>SDIO Data bus width \r
+ 0 = 1 bit , 1 = 4 bits \r
+ </Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Receive over Transmit priority</Name>\r
+ <Default>1</Default>\r
+ <Desc>Value more then 0, determines during interleaving how many packets are to be received before resume of current tranmission. Zero means NO interleaving</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_SDIO_Deep_Sleep" type="dc" opcode="0x0029">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0029</Value>\r
+ <Desc>SDIO deep sleep</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x14</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Deep Sleep Enable</Name>\r
+ <Default>0</Default>\r
+ <Desc>0 - Disable, 1 - Enable</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Just Sleep Time range1</Name>\r
+ <Default>0 </Default>\r
+ <Desc>ms, </Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Just Sleep Time range2</Name>\r
+ <Default>100 </Default>\r
+ <Desc>ms, Make sure that max value range for deassertion timer in DOT must be smaller than deassertion timer in sleep protocol configurations VS.</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>SDIO Sleep Mode</Name>\r
+ <Default>0</Default>\r
+ <Desc>0 - Commands will wake up the device, 1 - SDIO Clocks will wakeup the device </Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>SDIO min wake time before sending commands</Name>\r
+ <Default>0</Default>\r
+ <Desc>Time (in us) between waking up the device and sending the first packet (relevant when clocks will wakeup the device)</Desc>\r
+ </Param>\r
+ \r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_SDIO_Change_Retry" type="dc" opcode="0x001F">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x001F</Value>\r
+ <Desc>Change read acknowledgement behavior</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x04</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Set Read Acknowledgement </Name>\r
+ <Default>0</Default>\r
+ <Desc>0 = Disable , 1 = Enable</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_SDIO_Change_Max_Clock_Rate" type="dc" opcode="0x0020">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0020</Value>\r
+ <Desc>Change SDIO max clock</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x04</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Clock</Name>\r
+ <Default>25000000</Default>\r
+ <Desc>Clock im Hz</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_SDIO_Send_Command_52" type="dc" opcode="0x0021">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0021</Value>\r
+ <Desc>Issue command 52</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>20</Value>\r
+ </Param>\r
+ <Param type="u" size="2" valtype="SDIO Dest CMD52">\r
+ <Name>SDIO destination</Name>\r
+ <Default>0</Default>\r
+ <Desc>0 - Legacy mode,\r
+ 1 - Shared SDIO, BT \r
+ 2 - Shared SDIO, WLAN\r
+ </Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Read / write</Name>\r
+ <Default>0</Default>\r
+ <Desc>0 - Read, 1 - Write</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Function Number</Name>\r
+ <Default>0</Default>\r
+ <Desc>0 - 7</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Read After Write flag</Name>\r
+ <Default>0</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Register Address</Name>\r
+ <Default>0</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Write Data</Name>\r
+ <Default>0</Default>\r
+ <Desc>Must be 0 in read commands</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_SDIO_Send_Command_53" type="dc" opcode="0x0022">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0022</Value>\r
+ <Desc>Issue command 52</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>84</Value>\r
+ </Param>\r
+ <Param type="u" size="2" valtype="SDIO Dest CMD53">\r
+ <Name>SDIO destination</Name>\r
+ <Default>0</Default>\r
+ <Desc>0 - Legacy mode,\r
+ 1 - Shared SDIO, BT \r
+ 2 - Shared SDIO, WLAN\r
+ </Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Read / write</Name>\r
+ <Default>0</Default>\r
+ <Desc>0 - Read, 1 - Write</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Function Number</Name>\r
+ <Default>0</Default>\r
+ <Desc>0 - 7</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Block Mode and Opcode</Name>\r
+ <Default>0</Default>\r
+ <Desc>0 - R/W from fixed address, 1 - R/W from incrementing address</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Register Address</Name>\r
+ <Default>0</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Byte / Block count</Name>\r
+ <Default>0</Default>\r
+ <Desc>Must be 0 in read commands</Desc>\r
+ </Param>\r
+ <Param type="x" size="64">\r
+ <Name>Data to be sent</Name>\r
+ <Default></Default>\r
+ <Desc>Relevant only in write commands</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_SDIO_Send_Command" type="dc" opcode="0x0023">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0023</Value>\r
+ <Desc>Issue SDIO General command</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>8</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>SDIO destination </Name>\r
+ <Default>0</Default>\r
+ <Desc>0 = Legacy mode,\r
+ 1 = Shared SDIO, BT\r
+ 2 = Shared SDIO, WLAN\r
+ </Desc>\r
+ </Param>\r
+ <Param type="u" size="2" valtype="SDIO Commands">\r
+ <Name>SDIO Command value</Name>\r
+ <Default>0</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Argument</Name>\r
+ <Default>0</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Configure_Codec_Emulator" type="dc" opcode="0x0024">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0024</Value>\r
+ <Desc>Configure codec emulator. This command stops the sco generation.</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>60</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Enable/Disable</Name>\r
+ <Default>0</Default>\r
+ <Desc>1 - Enable, 0 - Disable</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Emulator clock rate</Name>\r
+ <Default>2048</Default>\r
+ <Desc>[64-16000] The PCM clock rate is between 64k to 4096k (Master mode) or 64K to 16M (Slave mode), it influence other params like: wait cycles, freq rate calcs and therefore shall be configured even if external clock is used</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" valtype="Role">\r
+ <Name>Emulator role</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>PCM clock and fsync direction: 0x00 - output (Master on PCM bus) sampled on rising edge. 0x01 - input (Slave on PCM bus).</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Frame sync frequency</Name>\r
+ <Default>8000</Default>\r
+ <Desc>[100Hz-173KHz] Actual frame sync frequency in Hz.</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Frame sync duty cycle</Name>\r
+ <Default>0x0001</Default>\r
+ <Desc>0x0000 - 50 % of Fsync period, [0x0001-0xFFFF] - Number of PCM clock cycles</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" valtype="Sampling_edge_type">\r
+ <Name>Frame sync edge</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>0x00 - Driven/sampled at rising edge, 0x01 - Driven/sampled at falling edge</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Frame sync polarity</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>0x00 - Active-high, 0x01 - Active-low</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Data out size</Name>\r
+ <Default>0x0010</Default>\r
+ <Desc>[0x0001-0x0280] Sample size in bits for each codec fsync. In case data size is greater than 24 bits, the size should be able to divide by 8.</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Data out offset ch1</Name>\r
+ <Default>1</Default>\r
+ <Desc>[0x00-0xFF] Number of pcm clock cycles between rising of frame sync to data start.</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Data out offset ch2</Name>\r
+ <Default>17</Default>\r
+ <Desc>[0x00-0xFF] Number of pcm clock cycles between rising of frame sync to data start.</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" valtype="Sampling_edge_type">\r
+ <Name>Data out edge</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>Data driven: 0x00 - rising edge, 0x01 - falling edge</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Data in size</Name>\r
+ <Default>0x10</Default>\r
+ <Desc>[0x0001-0x0280] Sample size in bits for each codec fsync. In case data size is greater than 24 bits, the size should be able to divide by 8.</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Data in offset ch1</Name>\r
+ <Default>1</Default>\r
+ <Desc>[0x00-0xFF] Number of pcm clock cycles between rising of frame sync to data start.</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Data in offset ch2</Name>\r
+ <Default>17</Default>\r
+ <Desc>[0x00-0xFF] Number of pcm clock cycles between rising of frame sync to data start.</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" valtype="Sampling_edge_type">\r
+ <Name>Data in edge</Name>\r
+ <Default>0x01</Default>\r
+ <Desc>Data sampled: 0x00- rising edge, 0x01 - falling edge</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_eSPI" type="dc" opcode="0x0025">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0025</Value>\r
+ <Desc>eSPI configuration</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>48</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>eSPI Mode </Name>\r
+ <Default>1</Default>\r
+ <Desc>0 = Init,\r
+ 1 = Change timing parameters\r
+ </Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>RX Delay Interrupt -> CS</Name>\r
+ <Default>0</Default>\r
+ <Desc>Delay between Interrupt line assertion until CS assertion [u sec]</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>TX Delay Interrupt -> Header</Name>\r
+ <Default>0</Default>\r
+ <Desc>Delay between Interrupt line assertion until header (type1) is sent [u sec]</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>RX Delay CS -> Header</Name>\r
+ <Default>0</Default>\r
+ <Desc>Delay between CS line assertion until header (type3) is sent [u sec]</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Delay Header -> Data</Name>\r
+ <Default>0</Default>\r
+ <Desc>Delay between header to data [u sec]</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Delay Data -> CS</Name>\r
+ <Default>0</Default>\r
+ <Desc>Delay between last data byte until CS deassertion [u sec]</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Reserved</Name>\r
+ <Default>0</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Reserved</Name>\r
+ <Default>0</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Reserved</Name>\r
+ <Default>0</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Reserved</Name>\r
+ <Default>0</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Time between two consequtive HCI packets</Name>\r
+ <Default>0</Default>\r
+ <Desc>Time between two consequtive HCI packets [u sec]</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Reset BT Device</Name>\r
+ <Default>0</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_RX_Data_Validity" type="dc" opcode="0x0026">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0026</Value>\r
+ <Desc>configure RX validity checking</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>4</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Mode</Name>\r
+ <Default>1</Default>\r
+ <Desc>0 = Disable checking validity,\r
+ 1 = Enable checking validity\r
+ </Desc>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_TI_SPI_Mode" type="dc" opcode="0x002B">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x002B</Value>\r
+ <Desc>SPI mode</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>2</Value>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>SPI Mode </Name>\r
+ <Default>1</Default>\r
+ <Desc>0 = eSPI mode, 1 = TI SPI Mode</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>SPI SWAP Mode (Reserved) </Name>\r
+ <Default>0</Default>\r
+ <Desc>(Reserved)</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_SDIO_Rx_Error_Generation" type="dc" opcode="0x0027">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0027</Value>\r
+ <Desc>Configure SDIO error generation for Rx flow\r
+ (NACK generation instead of ACK)\r
+ </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x10</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Random Mode</Name>\r
+ <Default>0</Default>\r
+ <Desc>0 = Non random, 1 = Random mode \r
+ (errors are generated at random times on random blocks)\r
+ </Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Packet number</Name>\r
+ <Default>0</Default>\r
+ <Desc>Upon reception of which packet error will be generated.\r
+ 0 - No error will be generated\r
+ </Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Block number</Name>\r
+ <Default>0</Default>\r
+ <Desc>Upon reception of which SD block error generated.</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>One shot</Name>\r
+ <Default>1</Default>\r
+ <Desc>1 - one shot. 0 - forever</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_SDIO_Tx_Error_Generation" type="dc" opcode="0x0028">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0028</Value>\r
+ <Desc>Configure SDIO error generation for Tx flow.\r
+ Noise generation on DAT line while SDIO transmits\r
+ </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x10</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Random Mode</Name>\r
+ <Default>0</Default>\r
+ <Desc>0 = Non random, 1 = Random mode \r
+ (errors are generated at random times on random blocks)\r
+ </Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Packet number</Name>\r
+ <Default>0</Default>\r
+ <Desc>Upon transmission of which packet error will be generated.\r
+ 0 - No error will be generated\r
+ </Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Block number</Name>\r
+ <Default>0</Default>\r
+ <Desc>Upon transmission of which SD block error generated.</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>One shot</Name>\r
+ <Default>1</Default>\r
+ <Desc>1 - one shot. 0 - forever</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Set_Uart_HCI_Baudrate" type="dc" opcode="0x002A">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0x002A</Default>\r
+ <Desc>Set Uart HCI Baudrate parameters</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x10</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Divider</Name>\r
+ <Default>0</Default>\r
+ <Desc>Baudrate Uart Divider</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Oversampling</Name>\r
+ <Default>0</Default>\r
+ <Desc>Baudrate Uart Oversampling</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Swallow Period</Name>\r
+ <Default>0</Default>\r
+ <Desc>Baudrate Uart Swallow Period</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Middle of Bit</Name>\r
+ <Default>0</Default>\r
+ <Desc>Middle of Bit value</Desc>\r
+ </Param>\r
+ \r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Cpu_Idle_Time" type="dc" opcode="0x0034">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0x0034</Default>\r
+ <Desc>DOT_Cpu_Idle_Time</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x2</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Time</Name>\r
+ <Default>80</Default>\r
+ <Desc>0-Enter CPU test mode , 1-Exit CPU test mode, other - start and check for "param" * 8ms (Dot Timer ticks) </Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Set_Uart_Debug_Baud_Rate" type="dc" opcode="0x002E">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x002E</Value>\r
+ <Desc>Set DOT uart debug baud rate</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x04</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Baud Rate</Name>\r
+ <Default>921600</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Test" type="dc" opcode="0x0035">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0035</Value>\r
+ <Desc>DOT test debug</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x04</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Param</Name>\r
+ <Default>0</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_SLIMbus" type="dc" opcode="0x0040">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0040</Value>\r
+ <Desc>DOT SLIMbus initialization and Configuration</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x0A</Value>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Mode</Name>\r
+ <Default>1</Default>\r
+ <Desc>1: Initialize and Configure, 0: Configure (already initialize). This parameter should be set to 1 at the first time this command being called, and only then.</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Dot is Active Framer</Name>\r
+ <Default>1</Default>\r
+ <Desc>1: Active Framer role is done by the DOT, 0: Active Framer role is done by another framer on the bus. If the setup includes only DOT and WL7, this parameter must be set to 1. This parameter is "Don't care" if Mode == 0</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Initial Root Frequency</Name>\r
+ <Default>1</Default>\r
+ <Desc>All frequencies are in MHz: 1: 24.576, 2: 22.5792, 3: 15.36, 4: 16.8, 5: 19.2 6: 24, 7: 25, 8: 26, 9: 27. Note: At the moment, Initial Root Frequency must be 24.576, Initial Clock Gear must be 9, and Clock Divider must be 4. This parameter is "Don't care" if Mode == 0</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Initial Clock Gear</Name>\r
+ <Default>9</Default>\r
+ <Desc>0 to 10, in respect to the definitions in the SLIMbus Specification. 10: clock is not divided, 9: clock is divided by 2, 8: divided by 4, and so on. Note: At the moment, Initial Root Frequency must be 24.576, Initial Clock Gear must be 9, and Clock Divider must be 4. This parameter is "Don't care" if Mode == 0</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Initial Subframe Mode</Name>\r
+ <Default>0xB</Default>\r
+ <Desc>Subframe Mode according to the SLIMbus Specification, to be used initially until reconfigured otherwise using normal SLIMbus sequence (NEXT_SUBFRAME_MODE). This parameter is "Don't care" if Mode == 0</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Clock Source Select</Name>\r
+ <Default>0</Default>\r
+ <Desc>0 - CODEC (12.288 MHz or 12 MHz), 1 - External (FPGA external clock), 2 - FREF (19.2 MHz). This parameter is "Don't care" if Mode == 0</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Clock Divider</Name>\r
+ <Default>4</Default>\r
+ <Desc>0 - ratio 1:32 (gears 6 to 10 forbidden), 1 - ratio 1:16 (gears 7 to 10 forbidden), 2 - ratio 1:8 (gears 8 to 10 forbidden), 3 - ratio 1:4 (gears 9 to 10 forbidden), 4 - ratio 1:2 (gear 10 forbidden), 5 - ratio 1:1 (root frequency = input frequency), 6 - 1:2, 7 - 1:4, 8 - 1:8, 9 - 1:16, 10 - 1:32. Note: At the moment, Initial Root Frequency must be 24.576, Initial Clock Gear must be 9, and Clock Divider must be 4. This parameter is "Don't care" if Mode == 0</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Enable HCI</Name>\r
+ <Default>1</Default>\r
+ <Desc>1 - Enable, 0 - Disable, 0xFF - Don't change</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Enable Debug Level 1 Trace Messages</Name>\r
+ <Default>1</Default>\r
+ <Desc>1 - Enable, 0 - Disable, 0xFF - Don't change</Desc>\r
+ </Param>\r
+ \r
+ <Param type="u" size="1">\r
+ <Name>Enable Debug Level 2 Trace Messages</Name>\r
+ <Default>0</Default>\r
+ <Desc>1 - Enable, 0 - Disable, 0xFF - Don't change</Desc>\r
+ </Param>\r
+ \r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_SLIMbus_Manual_Clock_Resume" type="dc" opcode="0x0042">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0042</Value>\r
+ <Desc>DOT SLIMbus manual clock resume</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x00</Value>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_SLIMbus_Audio_CODEC_Configuration" type="dc" opcode="0x0044">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0044</Value>\r
+ <Desc>DOT SLIMbus Audio CODEC Configuration</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x04</Value>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>audio format</Name>\r
+ <Default>0x53</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>sample rate</Name>\r
+ <Default>0x0C</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>left volume</Name>\r
+ <Default>0x17</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>right volume</Name>\r
+ <Default>0x17</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_SLIMbus_Audio" type="dc" opcode="0x0041">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0041</Value>\r
+ <Desc>DOT SLIMbus initialize Audio</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x26</Value>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>audio format</Name>\r
+ <Default>0x53</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>sample rate</Name>\r
+ <Default>0x0C</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>left volume</Name>\r
+ <Default>0x17</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>right volume</Name>\r
+ <Default>0x17</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1" label="ch0_mode">\r
+ <Name>Channel 0</Name>\r
+ <Default>1</Default>\r
+ <Desc>0-disable 1-TX 2-RX</Desc>\r
+ </Param>\r
+ <Param cond="ch0_mode!=0">\r
+ <Param type="u" size="1">\r
+ <Name>Source Device ID</Name>\r
+ <Default>2</Default>\r
+ <Desc>TX Device logical number</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Sink Device ID</Name>\r
+ <Default>5</Default>\r
+ <Desc>Rx Device logical number</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>TX Port index</Name>\r
+ <Default>4</Default>\r
+ <Desc>1-HCI_TX;\r
+ 4-BT_AUDIO_TX_0;5-BT_AUDIO_TX_1\r
+ 8-FM_AUDIO_TX_0;9-FM_AUDIO_TX_1\r
+ </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>RX Port index</Name>\r
+ <Default>2</Default>\r
+ <Desc>0-HCI_RX;\r
+ 2-BT_AUDIO_RX_0;3-BT_AUDIO_RX_1\r
+ 6-FM_AUDIO_RX_0;7FM_AUDIO_RX_1\r
+ </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Channel number</Name>\r
+ <Default>0</Default>\r
+ <Desc>channel number from 0 to 7</Desc>\r
+ </Param>\r
+ \r
+ <Param type="u" size="1">\r
+ <Name>Transport protocol</Name>\r
+ <Default>0</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>segment distribution</Name>\r
+ <Default>0x24</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>segment length</Name>\r
+ <Default>4</Default>\r
+ <Desc> </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>frequency locked</Name>\r
+ <Default>0</Default>\r
+ <Desc> </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>presence rate</Name>\r
+ <Default>0x11</Default>\r
+ <Desc> </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>auxiliary bit format</Name>\r
+ <Default>0</Default>\r
+ <Desc> </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>data type</Name>\r
+ <Default>0</Default>\r
+ <Desc> </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>channel link</Name>\r
+ <Default>0</Default>\r
+ <Desc> </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>data length</Name>\r
+ <Default>4</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="ch0_mode == 0">\r
+ <Param type="s" size="15" prop="h">\r
+ <Name></Name>\r
+ </Param>\r
+ </Param>\r
+ <Param type="u" size="1" label="ch1_mode">\r
+ <Name>Channel 1</Name>\r
+ <Default>2</Default>\r
+ <Desc>0-disable 1-TX 2-RX</Desc>\r
+ </Param>\r
+ <Param cond="ch1_mode!=0">\r
+ <Param type="u" size="1">\r
+ <Name>Source Device ID</Name>\r
+ <Default>5</Default>\r
+ <Desc>TX Device logical number</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Sink Device ID</Name>\r
+ <Default>2</Default>\r
+ <Desc>RX Device logical number</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>TX Port index</Name>\r
+ <Default>4</Default>\r
+ <Desc>1-HCI_TX\r
+ 4-BT_AUDIO_TX_0;5-BT_AUDIO_TX_1\r
+ 8-FM_AUDIO_TX_0;9-FM_AUDIO_TX_1\r
+ </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>RX Port index</Name>\r
+ <Default>2</Default>\r
+ <Desc>0-HCI_RX\r
+ 2-BT_AUDIO_RX_0;3-BT_AUDIO_RX_1\r
+ 6-FM_AUDIO_RX_0;7FM_AUDIO_RX_1\r
+ </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Channel number</Name>\r
+ <Default>1</Default>\r
+ <Desc>channel number from 0 to 7</Desc>\r
+ </Param>\r
+ \r
+ <Param type="u" size="1">\r
+ <Name>Transport protocol</Name>\r
+ <Default>0</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>segment distribution</Name>\r
+ <Default>0x28</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>segment length</Name>\r
+ <Default>4</Default>\r
+ <Desc> </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>frequency locked</Name>\r
+ <Default>0</Default>\r
+ <Desc> </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>presence rate</Name>\r
+ <Default>0x11</Default>\r
+ <Desc> </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>auxiliary bit format</Name>\r
+ <Default>0</Default>\r
+ <Desc> </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>data type</Name>\r
+ <Default>0</Default>\r
+ <Desc> </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>channel link</Name>\r
+ <Default>0</Default>\r
+ <Desc> </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>data length</Name>\r
+ <Default>4</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="ch1_mode == 0">\r
+ <Param type="s" size="15" prop="h">\r
+ <Name></Name>\r
+ </Param>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Subframe mode</Name>\r
+ <Default>0xA</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Clock gear</Name>\r
+ <Default>8</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ \r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_SLIMbus_Send_Message" type="dc" opcode="0x0048">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0048</Value>\r
+ <Desc>DOT SLIMbus send message for Debug purpose</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>3 + size(dest) + size(data)</Value>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Message ID</Name>\r
+ <Default>0x0C</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Destination Length</Name>\r
+ <Value>size(dest)</Value>\r
+ </Param>\r
+ <Param type="x" size="input" label="dest">\r
+ <Name>Destination</Name>\r
+ <Default>"11:22:33:44:55:66"</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Payload Length</Name>\r
+ <Value>size(data)</Value>\r
+ </Param>\r
+ <Param type="x" size="input" label="data">\r
+ <Name>Data</Name>\r
+ <Default>"00:11:22"</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_SlimBus_Deep_Sleep" type="dc" opcode="0x0043">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0043</Value>\r
+ <Desc>Slimbus Deep Sleep in band and out of band</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x18</Value>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Enable and Protocol</Name>\r
+ <Default>5 </Default>\r
+ <Desc>0=Disable, 5=SBIS 6=SB Out of Band</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Just Sleep Time range1</Name>\r
+ <Default>0 </Default>\r
+ <Desc>ms, Minimum low time for BT_WAKEUP signal. Random LOWER range</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Just Sleep Time range2</Name>\r
+ <Default>100 </Default>\r
+ <Desc>ms, Minimum low time for BT_WAKEUP signal. Random UPPER range</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Just Wake Time range1</Name>\r
+ <Default>0 </Default>\r
+ <Desc>ms, Minimum high time for BT_WAKEUP signal. Random LOWER range</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Just Wake Time range2</Name>\r
+ <Default>100 </Default>\r
+ <Desc>ms, Minimum high time for BT_WAKEUP signal. Random UPPER range</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Automatic Clock Pause on HCI SUSPENDED</Name>\r
+ <Default>0 </Default>\r
+ <Desc>Contols whether when both TX and RX are suspended, the DOT automatically sends a clock pause sequence (begin/pause/now). 0: Disable, 1: Enable, 0xFF: Don't change</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Start" type="dc" opcode="0x000b">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x000B</Value>\r
+ <Desc>Start Data Generation</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x04</Value>\r
+ </Param>\r
+ <Param type="h" size="2">\r
+ <Name>Connection Handle</Name>\r
+ <Default>0x0001</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Test Type</Name>\r
+ <Default>3</Default>\r
+ <Desc>1=RX 2=TX 3=RX+TX </Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Stop" type="dc" opcode="0x000c">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x000C</Value>\r
+ <Desc>Stop Data Generation</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x02</Value>\r
+ </Param>\r
+ <Param type="h" size="2">\r
+ <Name>Connection Handle</Name>\r
+ <Default>0x0001</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Packet_size" type="dc" opcode="0x000d">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x000D</Value>\r
+ <Desc>Packet size</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x12</Value>\r
+ </Param>\r
+ <Param type="h" size="2">\r
+ <Name>Connection Handle</Name>\r
+ <Default>0x0001</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Unit of packet size</Name>\r
+ <Default>0 </Default>\r
+ <Desc>0=Packet has a Fix size , 1=Random</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Fix packet size</Name>\r
+ <Default>339 </Default>\r
+ <Desc>5-339, Affective only with Fix size</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Random lower range</Name>\r
+ <Default>5 </Default>\r
+ <Desc>5-339, Affective only with Random</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Random upper range</Name>\r
+ <Default>339 </Default>\r
+ <Desc>5-339, Affective only with Random</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Rate" type="dc" opcode="0x000e">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x000E</Value>\r
+ <Desc>Rate</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>14</Value>\r
+ </Param>\r
+ <Param type="h" size="2">\r
+ <Name>Connection Handle</Name>\r
+ <Default>0x0001</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Maximum rate</Name>\r
+ <Default>0 </Default>\r
+ <Desc>Bit per second. 0= Maximum rate</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Resolution</Name>\r
+ <Default>2 </Default>\r
+ <Desc>1=Delay every 1 second, 2=Delay every 8ms</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Number of Packets</Name>\r
+ <Default>0 </Default>\r
+ <Desc>limit the number of bt buffers to use in TX. 0=Max buffers, 1 - Max buffers (lowest - highest)</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_L2CAP_Header" type="dc" opcode="0x000f">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x000F</Value>\r
+ <Desc>L2CAP Header</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x12</Value>\r
+ </Param>\r
+ <Param type="h" size="2">\r
+ <Name>Connection Handle</Name>\r
+ <Default>0x0001</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Number of TX channel ID's</Name>\r
+ <Default>1 </Default>\r
+ <Desc>How many headers are in this list</Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Algoritm to choose an ID</Name>\r
+ <Default>1 </Default>\r
+ <Desc>0=Cyclyc, 1=Random</Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>TX Channel ID #1</Name>\r
+ <Default>0x0041</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>TX Channel ID #2</Name>\r
+ <Default>0xDADA</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>TX Channel ID #3</Name>\r
+ <Default>0x0042</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>TX Channel ID #4</Name>\r
+ <Default>0x0043</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>TX Channel ID #5</Name>\r
+ <Default>0x0044</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>A3DP RX channel ID</Name>\r
+ <Default>0x0000</Default>\r
+ <Desc>0 - No ID</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Host_Flow_Control_Rate" type="dc" opcode="0x0014">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x0014</Value>\r
+ <Desc>Host flow control Rate</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>6</Value>\r
+ </Param>\r
+ <Param type="h" size="2">\r
+ <Name>Connection Handle</Name>\r
+ <Default>0x0001</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Maximum rate</Name>\r
+ <Default>0 </Default>\r
+ <Desc>Bit per second. 0= Maximum rate</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Configure_ACL" type="dc" opcode="0x002C">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x2C</Value>\r
+ <Desc>ACL Header</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x10</Value>\r
+ </Param>\r
+ <Param type="h" size="2">\r
+ <Name>Connection Handle</Name>\r
+ <Default>0x0001</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="u" size="2" label="mode">\r
+ <Name>Configure ACL Header</Name>\r
+ <Default>1</Default>\r
+ <Desc>0-Set header with fixed params 1-Set header according to the following params</Desc>\r
+ </Param>\r
+ <Param cond="mode==1">\r
+ <Param type="u" size="2">\r
+ <Name>ACL Boundary</Name>\r
+ <Default>2</Default>\r
+ <Desc>0-Force Start 1-Force Continuation 2-Auto according to the L2CAP packet size</Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>ACL Automatically Flushable</Name>\r
+ <Default>1</Default>\r
+ <Desc>0=No, 1=Yes.</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" valtype="BroadcastTypes">\r
+ <Name>ACL Broadcast flag</Name>\r
+ <Default>0</Default>\r
+ <Desc>0-No broadcast 1-active 2-all</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>L2CAP Payload Size</Name>\r
+ <Default>1021</Default>\r
+ <Desc>Packet size in bytes.</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="mode == 0">\r
+ <Param type="s" size="12" prop="h">\r
+ <Name></Name>\r
+ </Param>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Generate_GPS_Data" type="dc" opcode="0x002D">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x2D</Value>\r
+ <Desc>GPS data</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x0A</Value>\r
+ </Param>\r
+ <Param type="u" size="2" label="start">\r
+ <Name>Start Test</Name>\r
+ <Default>1</Default>\r
+ <Desc>0-Stop test, 1-Start test</Desc>\r
+ </Param>\r
+ <Param cond="start==1">\r
+ <Param type="u" size="2">\r
+ <Name>Min Packet length</Name>\r
+ <Default>800</Default>\r
+ <Desc>1-Max packet length in bytes</Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Max Packet length</Name>\r
+ <Default>2000</Default>\r
+ <Desc>(bytes)</Desc>\r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Interval</Name>\r
+ <Default>1000</Default>\r
+ <Desc>time in between packets (millisec)</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="start == 0">\r
+ <Param type="s" size="8" prop="h">\r
+ <Name></Name>\r
+ </Param>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DOT_Configure_ACL_Buffers" type="dc" opcode="0x002F">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0xF0</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>Opcode</Name>\r
+ <Value>0x2F</Value>\r
+ <Desc>Configure ACL buffers</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>0x4</Value>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>TX Buffer Length</Name>\r
+ <Default>1021</Default>\r
+ <Desc>10 to 1021 (default 1021 = 5 buffers)</Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>RX Buffer Length</Name>\r
+ <Default>1021</Default>\r
+ <Desc>10 to 1021 (default 1021 = 6 buffers)</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>DOT_DBG_Response_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<!-- ================================================================== -->\r
+<Command name="Custom Commands" type="gb" />\r
+<!-- ================================================================== -->\r
+\r
+<Command name="Bulk" type="cc">\r
+ <Param type="x" size="input">\r
+ <Name>Data</Name>\r
+ <Default>"00:11:22"</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_SCO_Data" type="cc">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0x03</Value>\r
+ </Param>\r
+ <Param type="h" size="2">\r
+ <Name>Handle</Name>\r
+ <Default>SCO_Handle</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>size(data)</Value>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="x" size="input" label="data">\r
+ <Name>SCO Data</Name>\r
+ <Default>"00:11:22"</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_SCO_Text" type="cc">\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0x03</Value>\r
+ </Param>\r
+ <Param type="h" size="2">\r
+ <Name>Handle</Name>\r
+ <Default>SCO_Handle</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>size(data)</Value>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="s" size="input" label="data">\r
+ <Name>SCO Text</Name>\r
+ <Default>"Hello Bluetooth"</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="Bulk_Event" type="ce">\r
+ <Param type="t">\r
+ <Name>Timeout</Name>\r
+ <Default>5000</Default>\r
+ <Desc>Time in msec to wait for the event</Desc>\r
+ </Param>\r
+ <Param type="x" size="input">\r
+ <Name>Data</Name>\r
+ <Default>"00:11:22"</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="Any_HCI_Event" type="ce">\r
+ <Param type="t">\r
+ <Name>Timeout</Name>\r
+ <Default>5000</Default>\r
+ <Desc>Time in msec to wait for the event</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0x04</Value>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Event Type</Name>\r
+ <Default>Any</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Param Length</Name>\r
+ <Value>size(data)</Value>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="x" size="input" label="data">\r
+ <Name>Parameters</Name>\r
+ <Default>"00:11:22"</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_SCO_Data_Event" type="ce">\r
+ <Param type="t">\r
+ <Name>Timeout</Name>\r
+ <Default>5000</Default>\r
+ <Desc>Time in msec to wait for the event</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Layer</Name>\r
+ <Value>0x03</Value>\r
+ </Param>\r
+ <Param type="h" size="2">\r
+ <Name>Handle</Name>\r
+ <Default>SCO_Handle</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="u" size="1" prop="h">\r
+ <Name>Length</Name>\r
+ <Value>size(data)</Value>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="x" size="input" label="data">\r
+ <Name>SCO Data</Name>\r
+ <Default>"00:11:22"</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+</Command>\r
+\r
+<!-- ================================================================== -->\r
+<Command name="Macroes" type="gb" />\r
+<!-- ================================================================== -->\r
+\r
+<Command name="Reset_Logger" type="vc">\r
+ <Macro><![CDATA[\r
+ Execute True, "C:\Program Files\ResetLooger\ResetLooger.exe", "", ""\r
+ ]]></Macro>\r
+</Command>\r
+\r
+<Command name="Set_IO_Pin_Mux_BTIP" type="sc">\r
+ \r
+ <Cat>Spec 1.1</Cat>\r
+ \r
+ <Macro><![CDATA[\r
+ _IO_Pin_Number = %1\r
+ _Mux_Select = %2\r
+ _BitShift = _IO_Pin_Number % 4\r
+ If _BitShift == 0 Then\r
+ _BitShift = 4\r
+ End If\r
+ _BitsToSend = _Mux_Select << 4*(_BitShift-1)\r
+ _BitsMask = 15 << 4*(_BitShift-1) \r
+ _Pin_Group = (_IO_Pin_Number-1) / 4\r
+ _Register_Address = 0x200Ef510 + (_Pin_Group << 1) \r
+ log "Pin Number 0x%x", _IO_Pin_Number\r
+ log "Mux_Select 0x%x", _Mux_Select\r
+ log "_BitShift 0x%x", _BitShift\r
+ log "_BitsToSend 0x%x", _BitsToSend\r
+ log "_BitsMask 0x%x", _BitsMask\r
+ log "_Pin_Group 0x%x", _Pin_Group\r
+ log "_Register_Address 0x%x", _Register_Address\r
+ \r
+\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, _Register_Address, _BitsToSend, _BitsMask\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+ ]]></Macro>\r
+ \r
+ <Param type="u" size="1" label="Pin_Name" valtype="PinName_btip">\r
+ <Name>Pin Name</Name>\r
+ <Default>1</Default>\r
+ <Desc>Select pin to Mux</Desc>\r
+ </Param>\r
+ <Param cond="Pin_Name==1">\r
+ <Param type="u" size="1" valtype="AUD_IN_btip">\r
+ <Name>AUD_IN Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>AUD_IN Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="Pin_Name==2">\r
+ <Param type="u" size="1" valtype="AUD_OUT_btip">\r
+ <Name>AUD_OUT Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>AUD_OUT Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="Pin_Name==3">\r
+ <Param type="u" size="1" valtype="AUD_CLK_btip">\r
+ <Name>AUD_CLK Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>AUD_CLK Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="Pin_Name==4">\r
+ <Param type="u" size="1" valtype="AUD_FSYNC_btip">\r
+ <Name>AUD_FSYNC Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>AUD_FSYNC Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==6">\r
+ <Param type="u" size="1" valtype="TX_HCI_btip">\r
+ <Name>TX_HCI Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>TX_HCI Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="Pin_Name==7">\r
+ <Param type="u" size="1" valtype="RX_HCI_btip">\r
+ <Name>RX_HCI Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>TX_HCI Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="Pin_Name==8">\r
+ <Param type="u" size="1" valtype="CTS_HCI_btip">\r
+ <Name>CTS_HCI Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>CTS_HCI Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="Pin_Name==9">\r
+ <Param type="u" size="1" valtype="RTS_HCI_btip">\r
+ <Name>RTS_HCI Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>RTS_HCI Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="Pin_Name==10">\r
+ <Param type="u" size="1" valtype="BT_FUNC_1_btip">\r
+ <Name>BT_FUNC_1 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>BT_FUNC1 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="Pin_Name==11">\r
+ <Param type="u" size="1" valtype="BT_FUNC_2_btip">\r
+ <Name>BT_FUNC_2 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>BT_FUNC2 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==12">\r
+ <Param type="u" size="1" valtype="BT_FUNC_3_btip">\r
+ <Name>BT_FUNC_3 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>BT_FUNC3 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==13">\r
+ <Param type="u" size="1" valtype="BT_FUNC_4_btip">\r
+ <Name>BT_FUNC_4 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>BT_FUNC4 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==14">\r
+ <Param type="u" size="1" valtype="BT_FUNC_5_btip">\r
+ <Name>BT_FUNC_5 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>BT_FUNC5 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==15">\r
+ <Param type="u" size="1" valtype="BT_FUNC_6_btip">\r
+ <Name>BT_FUNC_1 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>BT_FUNC6 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==16">\r
+ <Param type="u" size="1" valtype="BT_FUNC_7_btip">\r
+ <Name>BT_FUNC_7 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>BT_FUNC1 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==17">\r
+ <Param type="u" size="1" valtype="BT_FUNC_8_btip">\r
+ <Name>BT_FUNC_8 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>BT_FUNC8 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==18">\r
+ <Param type="u" size="1" valtype="BT_FUNC_9_btip">\r
+ <Name>BT_FUNC_1 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>BT_FUNC1 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==19">\r
+ <Param type="u" size="1" valtype="BT_FUNC_10_btip">\r
+ <Name>BT_FUNC_10 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>BT_FUNC10 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="Set_IO_Pin_Mux_Orca_top" type="sc">\r
+ \r
+ <Cat>Spec 1.1</Cat>\r
+ \r
+ <Macro><![CDATA[\r
+ _IO_Pin_Number = %1\r
+ _Mux_Select = %2\r
+ _BitShift = ((_IO_Pin_Number-1) % 2) * 8\r
+ _BitsToSend = _Mux_Select << _BitShift\r
+ _BitsMask = 15 << _BitShift\r
+ _Pin_Group = (_IO_Pin_Number-1) / 2\r
+ _Register_Address = 0x1a7c80 + (_Pin_Group << 1) \r
+ If _Register_Address == 0x1a7c94 Then\r
+ _Register_Address = 0x1a7c9A\r
+ End If\r
+ If _Register_Address == 0x1a7c8e Then\r
+ _Register_Address = 0x1a7c94\r
+ End If\r
+ If _Register_Address == 0x1a7c90 Then\r
+ _Register_Address = 0x1a7c96\r
+ End If\r
+ If _Register_Address == 0x1a7c92 Then\r
+ _Register_Address = 0x1a7c98\r
+ End If\r
+\r
+ log "Pin Number 0x%x", _IO_Pin_Number\r
+ log "Mux_Select 0x%x", _Mux_Select\r
+ log "_BitShift 0x%x", _BitShift\r
+ log "_BitsToSend 0x%x", _BitsToSend\r
+ log "_BitsMask 0x%x", _BitsMask\r
+ log "_Pin_Group 0x%x", _Pin_Group\r
+ log "_Register_Address 0x%x", _Register_Address\r
+ \r
+\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, _Register_Address, _BitsToSend, _BitsMask\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+ ]]></Macro>\r
+ \r
+ <Param type="u" size="1" label="Pin_Name" valtype="PinName_orca">\r
+ <Name>Pin Name</Name>\r
+ <Default>1</Default>\r
+ <Desc>Select pin to Mux</Desc>\r
+ </Param>\r
+ <Param cond="Pin_Name==1">\r
+ <Param type="u" size="1" valtype="TX_HCI_orca">\r
+ <Name>TX_HCI Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>TX_HCI Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="Pin_Name==2">\r
+ <Param type="u" size="1" valtype="RX_HCI_orca">\r
+ <Name>RX_HCI Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>RX_HCI Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="Pin_Name==3">\r
+ <Param type="u" size="1" valtype="CTS_HCI_orca">\r
+ <Name>CTS_HCI Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>CTS_HCI Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="Pin_Name==4">\r
+ <Param type="u" size="1" valtype="RTS_HCI_orca">\r
+ <Name>RTS_HCI Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>RTS_HCI Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==5">\r
+ <Param type="u" size="1" valtype="AUD_IN_orca">\r
+ <Name>AUD_IN Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>AUD_IN Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="Pin_Name==6">\r
+ <Param type="u" size="1" valtype="AUD_OUT_orca">\r
+ <Name>AUD_OUT Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>AUD_OUT Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="Pin_Name==7">\r
+ <Param type="u" size="1" valtype="AUD_CLK_orca">\r
+ <Name>AUD_CLK Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>AUD_CLK Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="Pin_Name==8">\r
+ <Param type="u" size="1" valtype="AUD_FSYNC_orca">\r
+ <Name>AUD_FSYNC Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>AUD_FSYNC Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="Pin_Name==9">\r
+ <Param type="u" size="1" valtype="BT_FUNC_1_orca">\r
+ <Name>BT_FUNC_1 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>BT_FUNC1 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="Pin_Name==10">\r
+ <Param type="u" size="1" valtype="BT_FUNC_2_orca">\r
+ <Name>BT_FUNC_2 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>BT_FUNC2 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==11">\r
+ <Param type="u" size="1" valtype="TX_DBG_orca">\r
+ <Name>TX_DBG Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>TX_DBG Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==12">\r
+ <Param type="u" size="1" valtype="BT_FUNC_4_orca">\r
+ <Name>BT_FUNC_4 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>BT_FUNC4 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==13">\r
+ <Param type="u" size="1" valtype="BT_FUNC_6_orca">\r
+ <Name>BT_FUNC_6 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>BT_FUNC6 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==14">\r
+ <Param type="u" size="1" valtype="BT_FUNC_7_orca">\r
+ <Name>BT_FUNC_7 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>BT_FUNC_7 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==15">\r
+ <Param type="u" size="1" valtype="CLK_REQ_OUT_orca">\r
+ <Name>CLK_REQ_OUT Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>CLK_REQ_OUT Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==16">\r
+ <Param type="u" size="1" valtype="FM_IRQ_orca">\r
+ <Name>FM_IRQ Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>FM_IRQ Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==17">\r
+ <Param type="u" size="1" valtype="FM_SCL_orca">\r
+ <Name>FM_SCL Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>FM_SCL Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==18">\r
+ <Param type="u" size="1" valtype="FM_SDA_orca">\r
+ <Name>FM_SDA Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>FM_SDA Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="Pin_Name==19">\r
+ <Param type="u" size="1" valtype="FM_I2S_DI_orca">\r
+ <Name>FM_I2S_DI Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>FM_I2S_DI Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="Pin_Name==20">\r
+ <Param type="u" size="1" valtype="FM_I2S_DO_orca">\r
+ <Name>FM_I2S_DO Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>FM_I2S_DO Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="Pin_Name==21">\r
+ <Param type="u" size="1" valtype="FM_I2S_CLK_orca">\r
+ <Name>FM_I2S_CLK Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>FM_I2S_CLK Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="Pin_Name==22">\r
+ <Param type="u" size="1" valtype="FM_I2S_WS_orca">\r
+ <Name>FM_I2S_WS Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>FM_I2S_WS Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="Set_IO_Pin_Mux_Quattro_top" type="sc">\r
+ \r
+ <Cat>Spec 1.1</Cat>\r
+ \r
+ <Macro><![CDATA[\r
+ _IO_Pin_Number = %1\r
+ _Mux_Select = %2\r
+ _BitShift = ((_IO_Pin_Number-1) % 2) * 8\r
+ _BitsToSend = _Mux_Select << _BitShift\r
+ _BitsMask = 15 << _BitShift\r
+ _Pin_Group = (_IO_Pin_Number-1) / 2\r
+ _Register_Address = 0x1a7c80 + (_Pin_Group << 1) \r
+ If _Register_Address == 0x1a7c92 Then\r
+ _Register_Address = 0x1a7c94\r
+ End If\r
+ If _Register_Address == 0x1a7c9E Then\r
+ _Register_Address = 0x1a7cA2\r
+ End If\r
+ If _Register_Address == 0x1a7cA0 Then\r
+ _Register_Address = 0x1a7cA2\r
+ End If\r
+ log "Pin Number 0x%x", _IO_Pin_Number\r
+ log "Mux_Select 0x%x", _Mux_Select\r
+ log "_BitShift 0x%x", _BitShift\r
+ log "_BitsToSend 0x%x", _BitsToSend\r
+ log "_BitsMask 0x%x", _BitsMask\r
+ log "_Pin_Group 0x%x", _Pin_Group\r
+ log "_Register_Address 0x%x", _Register_Address\r
+ \r
+\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, _Register_Address, _BitsToSend, _BitsMask\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+ ]]></Macro>\r
+ \r
+ <Param type="u" size="1" label="Pin_Name" valtype="PinName_Quattro">\r
+ <Name>Pin Name</Name>\r
+ <Default>1</Default>\r
+ <Desc>Select pin to Mux</Desc>\r
+ </Param>\r
+ <Param cond="Pin_Name==1">\r
+ <Param type="u" size="1" valtype="TX_HCI_Quattro">\r
+ <Name>TX_HCI Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>TX_HCI Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="Pin_Name==2">\r
+ <Param type="u" size="1" valtype="RX_HCI_Quattro">\r
+ <Name>RX_HCI Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>RX_HCI Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="Pin_Name==3">\r
+ <Param type="u" size="1" valtype="CTS_HCI_Quattro">\r
+ <Name>CTS_HCI Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>CTS_HCI Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==4">\r
+ <Param type="u" size="1" valtype="RTS_HCI_Quattro">\r
+ <Name>RTS_HCI Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>RTS_HCI Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==5">\r
+ <Param type="u" size="1" valtype="AUD_IN_Quattro">\r
+ <Name>AUD_IN Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>AUD_IN Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==6">\r
+ <Param type="u" size="1" valtype="AUD_OUT_Quattro">\r
+ <Name>AUD_OUT Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>AUD_OUT Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==7">\r
+ <Param type="u" size="1" valtype="AUD_CLK_Quattro">\r
+ <Name>AUD_CLK Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>AUD_CLK Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==8">\r
+ <Param type="u" size="1" valtype="AUD_FSYNC_Quattro">\r
+ <Name>AUD_FSYNC Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>AUD_FSYNC Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==9">\r
+ <Param type="u" size="1" valtype="BT_FUNC_1_Quattro">\r
+ <Name>BT_FUNC_1 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>BT_FUNC_1 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==10">\r
+ <Param type="u" size="1" valtype="BT_FUNC_2_Quattro">\r
+ <Name>BT_FUNC_2 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>BT_FUNC_2 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==11">\r
+ <Param type="u" size="1" valtype="BT_FUNC_5_Quattro">\r
+ <Name>BT_FUNC_5 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>BT_FUNC_5 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==12">\r
+ <Param type="u" size="1" valtype="BT_FUNC_3_Quattro">\r
+ <Name>BT_FUNC_3 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>BT_FUNC_3 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==13">\r
+ <Param type="u" size="1" valtype="BT_FUNC_6_Quattro">\r
+ <Name>BT_FUNC_6 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>BT_FUNC_6 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==14">\r
+ <Param type="u" size="1" valtype="BT_FUNC_7_Quattro">\r
+ <Name>BT_FUNC_7 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>BT_FUNC_7 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==15">\r
+ <Param type="u" size="1" valtype="SB_DATA_Quattro">\r
+ <Name>SB_DATA Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>SB_DATA Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==16">\r
+ <Param type="u" size="1" valtype="SB_CLK_Quattro">\r
+ <Name>CSB_CLK Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>SB_CLK Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==17">\r
+ <Param type="u" size="1" valtype="WL_TX_Quattro">\r
+ <Name>WL_TX Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>WL_TX Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==18">\r
+ <Param type="u" size="1" valtype="WL_RX_Quattro">\r
+ <Name>WL_RX Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>WL_RX Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==21">\r
+ <Param type="u" size="1" valtype="FREF_CLK_REQ_Quattro">\r
+ <Name>FREF_CLK_REQ Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>FREF_CLK_REQ Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==25">\r
+ <Param type="u" size="1" valtype="FM_I2S_DI_Quattro">\r
+ <Name>FM_I2S_DI Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>FM_I2S_DI Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==26">\r
+ <Param type="u" size="1" valtype="FM_I2S_DO_Quattro">\r
+ <Name>FM_I2S_DO Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>FM_I2S_DO Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==27">\r
+ <Param type="u" size="1" valtype="FM_I2S_CLK_Quattro">\r
+ <Name>FM_I2S_CLK Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>FM_I2S_CLK Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==28">\r
+ <Param type="u" size="1" valtype="FM_I2S_WS_Quattro">\r
+ <Name>FM_I2S_WS Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>FM_I2S_WS Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==30">\r
+ <Param type="u" size="1" valtype="SPI_CSX_Quattro">\r
+ <Name>SPI_CSX Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>SPI_CSX Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==35">\r
+ <Param type="u" size="1" valtype="WLAN_IRQ_Quattro">\r
+ <Name>WLAN_IRQ Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>WLAN_IRQ Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==36">\r
+ <Param type="u" size="1" valtype="WL_UART_DBG_Quattro">\r
+ <Name>WL_UART_DBG Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>WL_UART_DBG Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==37">\r
+ <Param type="u" size="1" valtype="WL_PAEN_A_Quattro">\r
+ <Name>WL_PAEN_A Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>WL_PAEN_A Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==38">\r
+ <Param type="u" size="1" valtype="WL_PAEN_B_Quattro">\r
+ <Name>WL_PAEN_B Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>WL_PAEN_B Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==39">\r
+ <Param type="u" size="1" valtype="WL_BTH_SW_Quattro">\r
+ <Name>WL_BTH_SW Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>WL_BTH_SW Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==40">\r
+ <Param type="u" size="1" valtype="WL_EXT_LNA_EN_Quattro">\r
+ <Name>WL_EXT_LNA_EN Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>WL_EXT_LNA_EN Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==41">\r
+ <Param type="u" size="1" valtype="WL_RS232_RX_Quattro">\r
+ <Name>WL_RS232_RX Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>WL_RS232_RX Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==42">\r
+ <Param type="u" size="1" valtype="WL_RS232_TX_Quattro">\r
+ <Name>WL_RS232_TX Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>WL_RS232_TX Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==43">\r
+ <Param type="u" size="1" valtype="JTAG_TCK_Quattro">\r
+ <Name>JTAG_TCK Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>JTAG_TCK Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==44">\r
+ <Param type="u" size="1" valtype="JTAG_TMS_Quattro">\r
+ <Name>JTAG_TMS Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>JTAG_TMS Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==45">\r
+ <Param type="u" size="1" valtype="JTAG_TDI_Quattro">\r
+ <Name>JTAG_TDI Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>JTAG_TDI Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==46">\r
+ <Param type="u" size="1" valtype="JTAG_TDO_Quattro">\r
+ <Name>JTAG_TDO Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>JTAG_TDO Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==47">\r
+ <Param type="u" size="1" valtype="GPS_UART_TX_Quattro">\r
+ <Name>GPS_UART_TX Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>GPS_UART_TX Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==48">\r
+ <Param type="u" size="1" valtype="GPS_UART_RX_Quattro">\r
+ <Name>GPS_UART_RX Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>GPS_UART_RX Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==49">\r
+ <Param type="u" size="1" valtype="GPS_SENS_I2C_SCL_Quattro">\r
+ <Name>GPS_SENS_I2C_SCL Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>GPS_SENS_I2C_SCL Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==50">\r
+ <Param type="u" size="1" valtype="GPS_SENS_I2C_SDA_Quattro">\r
+ <Name>GPS_SENS_I2C_SDA Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>GPS_SENS_I2C_SDA Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==51">\r
+ <Param type="u" size="1" valtype="TESTMODE_Quattro">\r
+ <Name>TESTMODE Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>TESTMODE Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==52">\r
+ <Param type="u" size="1" valtype="TCXO_CLK_REQ_Quattro">\r
+ <Name>TCXO_CLK_REQ Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>TCXO_CLK_REQ Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==53">\r
+ <Param type="u" size="1" valtype="GPS_IRQ_Quattro">\r
+ <Name>GPS_IRQ Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>GPS_IRQ Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==54">\r
+ <Param type="u" size="1" valtype="GPS_TIMESTAMP_Quattro">\r
+ <Name>GPS_TIMESTAMP Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>GPS_TIMESTAMP Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==55">\r
+ <Param type="u" size="1" valtype="GPS_PPS_OUT_Quattro">\r
+ <Name>GPS_PPS_OUT Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>GPS_PPS_OUT Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==56">\r
+ <Param type="u" size="1" valtype="GPS_I2C_UART_SELECT_Quattro">\r
+ <Name>GPS_I2C_UART_SELECT Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>GPS_I2C_UART_SELECT Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ \r
+ <Param cond="Pin_Name==57">\r
+ <Param type="u" size="1" valtype="GPS_EXT_LNA_EN_Quattro">\r
+ <Name>GPS_EXT_LNA_EN Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>GPS_EXT_LNA_EN Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==58">\r
+ <Param type="u" size="1" valtype="GPS_PA_EN_Quattro">\r
+ <Name>GPS_PA_EN Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>GPS_PA_EN Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==59">\r
+ <Param type="u" size="1" valtype="DC2DC_MODE_Quattro">\r
+ <Name>DC2DC_MODE Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>DC2DC_MODE Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==60">\r
+ <Param type="u" size="1" valtype="TCXO_SLI_OUT_Quattro">\r
+ <Name>TCXO_SLI_OUT Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>TCXO_SLI_OUT Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==61">\r
+ <Param type="u" size="1" valtype="WL_SPI_DIN_Quattro">\r
+ <Name>WL_SPI_DIN Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>WL_SPI_DIN Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==62">\r
+ <Param type="u" size="1" valtype="WL_SPI_DOUT_Quattro">\r
+ <Name>WL_SPI_DOUT Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>WL_SPI_DOUT Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==63">\r
+ <Param type="u" size="1" valtype="WL_SDIO_D1_Quattro">\r
+ <Name>WL_SDIO_D1 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>WL_SDIO_D1 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="Pin_Name==64">\r
+ <Param type="u" size="1" valtype="WL_SDIO_D2_Quattro">\r
+ <Name>WL_SDIO_D2 Pin mux</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>WL_SDIO_D2 Pin mux</Desc>\r
+ </Param>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="GCM_MUX_SIGNAL" type="cc">\r
+ <Cat>Spec 1.1</Cat>\r
+ \r
+ <Macro><![CDATA[\r
+ _gcm_signal_number = %1\r
+ _pin_id = %2\r
+\r
+ log "_gcm_signal_number %d", _gcm_signal_number\r
+ log "_pin_id %d", _pin_id\r
+ \r
+ # Select GCM signals\r
+ ############################ \r
+\r
+ \r
+ \r
+ # Write to TEST SELECT REGISTER: \r
+ # DRX is muxed out \r
+ \r
+ # Generate TEST_SELECT_Register\r
+ #value = _test_clk_mux_sel & 0xf\r
+ #value = ((_dtst_mux_sel & 0xf) << 4) ^ value\r
+ #value = ((_test_clock_invert & 0x1) << 8) ^ value\r
+ #value = ((_inter_sel & 0xf) << 9) ^ value\r
+ #value = ((_lsb_sel & 0x1) << 13) ^ value\r
+ #value = ((_shl_sel & 0x1f) << 14) ^ value\r
+ \r
+ #Send_HCI_VS_DRP_Write_Register 0xFD2A, 0x804, value\r
+ #Wait_HCI_Command_Complete_VS_DRP_Write_Register_Event 5000, any, HCI_VS_DRP_Write_Register, 0x00\r
+ \r
+ #debug bus enable\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E3002, 0x0004, 0x0004\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ #enable test bus clock in gcm\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E6010, 0x0020, 0x0020\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ If (_pin_id == 1) Then\r
+ #put selected signal on selected dbg pin\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E604c, _gcm_signal_number, 0x003f\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ #select dbg pin from gcm and not from soc\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E605e, 0x0001, 0x0001\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ End If\r
+\r
+ If (_pin_id == 2) Then\r
+ _gcm_signal_number_=_gcm_signal_number<<8\r
+ #put selected signal on selected dbg pin\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E604c, _gcm_signal_number_,0x3f00\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ #select dbg pin from gcm and not from soc\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E605e, 0x0002, 0x0002\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ End If\r
+ \r
+ If (_pin_id == 3) Then\r
+ #put selected signal on selected dbg pin\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E604e, _gcm_signal_number,0x003f\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ #select dbg pin from gcm and not from soc\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E605e, 0x0004, 0x0004\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ End If\r
+\r
+ If (_pin_id == 4) Then\r
+ _gcm_signal_number_=_gcm_signal_number<<8\r
+ #put selected signal on selected dbg pin\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E604e, _gcm_signal_number_,0x3f00\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ #select dbg pin from gcm and not from soc\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E605e, 0x0008, 0x0008\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ End If\r
+\r
+ If (_pin_id == 5) Then\r
+ #put selected signal on selected dbg pin\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E6050, _gcm_signal_number,0x003f\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ #select dbg pin from gcm and not from soc\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E605e, 0x0010, 0x0010\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ End If\r
+\r
+ If (_pin_id == 6) Then\r
+ _gcm_signal_number_=_gcm_signal_number<<8\r
+ #put selected signal on selected dbg pin\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E6050, _gcm_signal_number_,0x3f00\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ #select dbg pin from gcm and not from soc\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E605e, 0x0020, 0x0020\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ End If\r
+\r
+ If (_pin_id == 7) Then\r
+ #put selected signal on selected dbg pin\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E6052, _gcm_signal_number,0x003f\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ #select dbg pin from gcm and not from soc\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E605e, 0x0040, 0x0040\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ End If\r
+\r
+ If (_pin_id == 8) Then\r
+ _gcm_signal_number_=_gcm_signal_number<<8\r
+ #put selected signal on selected dbg pin\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E6052, _gcm_signal_number_,0x3f00\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ #select dbg pin from gcm and not from soc\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E605e, 0x0080, 0x0080\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ End If\r
+\r
+ If (_pin_id == 9) Then\r
+ #put selected signal on selected dbg pin\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E6054, _gcm_signal_number,0x003f\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ #select dbg pin from gcm and not from soc\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E605e, 0x0100, 0x0100\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ End If\r
+\r
+ If (_pin_id == 10) Then\r
+ _gcm_signal_number_=_gcm_signal_number<<8\r
+ #put selected signal on selected dbg pin\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E6054, _gcm_signal_number_,0x3f00\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ #select dbg pin from gcm and not from soc\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E605e, 0x0200, 0x0200\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ End If\r
+\r
+ \r
+\r
+ ]]></Macro>\r
+ \r
+ <Param type="u" size="1" valtype="GCMSignalList">\r
+ <Name>GCM signal select</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>1-Selects the output clock on test_clk output</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="SetTestMuxPinNumber">\r
+ <Name>DBG pin number</Name>\r
+ <Default>0x01</Default>\r
+ <Desc>Selects the outputs to be muxed on the test output</Desc>\r
+ </Param>\r
+</Command>\r
+\r
+<!-- ******************************************************* --> \r
+<!-- ******************************************************* --> \r
+<!-- DTST BT Muxing --> \r
+<!-- ******************************************************* --> \r
+<!-- ******************************************************* --> \r
+<Command name="DRP_BT_Mux_DTST" type="cc">\r
+ <Cat>Spec 1.1</Cat> \r
+ <Macro>\r
+ <![CDATA[ \r
+ _test_mux_Signal_sel= %1\r
+ _dtst_Module_sel = %2\r
+ _shift_select= %3\r
+ _test_clk_mux_sel = %4\r
+ _test_dtst_enable = %5\r
+ _test_mirror_enable = %6\r
+ _test_apll_clk_select = %7\r
+ _TestBusOverrideSelect = %8\r
+ _TestBusOverrideValue = %9\r
+ _test_pins_GPIO_0_Mux_Status = %10\r
+ _test_pins_GPIO_0_Mux_ChooseBit = %11\r
+ _test_pins_GPIO_1_Mux_Status = %12\r
+ _test_pins_GPIO_1_Mux_ChooseBit = %13\r
+ _test_pins_GPIO_2_Mux_Status = %14\r
+ _test_pins_GPIO_2_Mux_ChooseBit = %15\r
+\r
+ \r
+\r
+ \r
+ # Set debug module settings \r
+ ########################### \r
+ \r
+ # Write to TEST SELECT REGISTER: \r
+ # DRX is muxed out \r
+\r
+ # DBG <3..0>\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x200E300A, 0x0000\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00\r
+\r
+ # DBG<7..4>\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x200E300C, 0x0000\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00\r
+\r
+ # DBG<8..9> \r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x200E300E, 0x0000\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00\r
+\r
+ # DBG_CFG <2> DBG_BUS_EN\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x200E3002, 0x0000\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x0004\r
+\r
+ #**************************************************************************#\r
+ sleep 100\r
+ #**************************************************************************#\r
+ #BTIP AOD module (AOD_DEBUG_CTL_LOW) (GCM level) configuration <0..8> --> should be set to "0"\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x200E605C, 0x0000\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+ #**************************************************************************#\r
+ sleep 100\r
+ #**************************************************************************#\r
+ \r
+ #18XX Top level configuration (Output Connector Pins ) \r
+ # Debug Pins were choosen using the following link : \r
+ # http://mcsdocs/WLAN/index.php?dir=MCS_WLAN_Docs/ASIC/WiLink%20Products/WiLink%208/design/IO/&file=185x_spinner_xls_sheets.xml\r
+ \r
+ # Muxing All Top Configuration! accroding to Mode 8\r
+ for Addr = 0x200CE100 to 0x200CE124 step 0x2\r
+ \r
+ if( (Addr == 0x200CE10E | Addr == 0x200CE110 | Addr == 0x200CE112 | Addr == 0x200CE118 | Addr == 0x200CE122 ) == 0 ) then\r
+ \r
+ # log "Addr : %x \n", Addr\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, Addr, 0x0008, 0x001f\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00 \r
+ \r
+ end if\r
+\r
+ next\r
+ \r
+ \r
+ #******************* DRP DTST REG CONFIG *******************************************************#\r
+ #Clear dtst En \r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F206, 0x0000, 0x0010 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ # WRITE _dtst_Module_sel to DTST_CTRL Register\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F204, _dtst_Module_sel<<8, 0x0700 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ # WRITE test_mux_Signal_sel to DTST_CTRL Register\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F204, _test_mux_Signal_sel, 0x00FF \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ # WRITE _shift_select to DTST_CTRL Register\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F204, _shift_select<<12, 0xF000 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ # WRITE _test_clk_mux_sel to DTST_CTRL Register\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F206, _test_clk_mux_sel, 0x000F \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ # WRITE _test_mirror_enable to DTST_CTRL Register\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F206, _test_mirror_enable<<8, 0x0100 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ # WRITE _test_apll_clk_select to DTST_CTRL Register\r
+ [HCI]:Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F206, _test_apll_clk_select<<12, 0x1000 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+ #Mux GPIOs if wanted \r
+ \r
+ #Eable GPIOs\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F224, _test_pins_GPIO_0_Mux_Status | _test_pins_GPIO_1_Mux_Status<<1 | _test_pins_GPIO_2_Mux_Status<<2, 0x0007 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+ \r
+ #Choosing the muxing bit location\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F224, _test_pins_GPIO_0_Mux_ChooseBit<<8, 0x0F00 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F226, _test_pins_GPIO_1_Mux_ChooseBit, 0x000F \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F226, _test_pins_GPIO_2_Mux_ChooseBit<<8, 0x0F00 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+ \r
+ \r
+ # WRITE _test_dtst_enable to DTST_CTRL Register\r
+ log "test_dtst_enable %d", _test_dtst_enable\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F206, _test_dtst_enable<<4, 0x0010 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+ \r
+ # This is just a saftey write In last project we had a TDM option , in this project we dont have it but the reguster still exist\r
+ # we must make sure its "0" DRX_SPARE_REGISTER_1\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x20018260, 0x0000, 0x0001 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+ #******************* DRP DTST REG CONFIG END *******************************************************#\r
+ \r
+ #******************* DRP DTST Bus Override *******************************************************#\r
+ # WRITE TestBusOverrideSelect to Register\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x2001F222, _TestBusOverrideSelect\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+ # WRITE TestBusOverrideValue to Register\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x2001F220, _TestBusOverrideValue\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+ \r
+ # I DON'T KNOW WHY WE NEED THIS COMMAND BUT IT EXIST ON 65NM SO I KEEP IT HERE ALSO \r
+ \r
+ if _TestBusOverrideSelect > 0 then\r
+ # WRITE _test_mirror_enable to DTST_CTRL Register\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F206, 0x0100, 0x0100 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ end if\r
+\r
+ #******************* DRP DTST Bus Override End *******************************************************#\r
+ ]]> \r
+ </Macro>\r
+ <Param type="u" size="1">\r
+ <Name>Signal_sel</Name> \r
+ <Default>0x00</Default> \r
+ <Desc>1-Selects the signals to Mux </Desc> \r
+ </Param>\r
+ <Param type="u" size="1" bits="4" valtype="dtst_Module_sel">\r
+ <Name>Module_sel</Name> \r
+ <Default>0x00</Default> \r
+ <Desc>Selects the DRP Module </Desc> \r
+ </Param>\r
+ <Param type="u" size="1" bits="4" valtype="shift_select">\r
+ <Name>shift_select</Name> \r
+ <Default>0x00</Default> \r
+ <Desc>0 - Select Number of bits to mux </Desc> \r
+ </Param>\r
+ <Param type="u" size="1" bits="4" valtype="test_clk_mux_sel">\r
+ <Name>test_clk_mux_sel</Name> \r
+ <Default>0x00</Default> \r
+ <Desc>Selects the output clock on test_clk output</Desc> \r
+ </Param>\r
+ <Param type="u" size="1" bits="1" valtype="test_dtst_enable">\r
+ <Name>test_dtst_enable</Name> \r
+ <Default>1</Default> \r
+ <Desc>0 - Enable\Disable DTST</Desc> \r
+ </Param>\r
+ <Param type="u" size="1" bits="1" valtype="test_mirror_enable">\r
+ <Name>test_mirror_enable</Name> \r
+ <Default>0</Default> \r
+ <Desc>0 - Enable Mirror </Desc> \r
+ </Param>\r
+ <Param type="u" size="1" bits="1" valtype="test_apll_clk_select">\r
+ <Name>test_apll_clk_select</Name> \r
+ <Default>0</Default> \r
+ </Param>\r
+ <Param type="u" size="1" bits="2" valtype="TestBusOverrideSelect">\r
+ <Name>TestBusOverrideSelect</Name> \r
+ <Default>0</Default> \r
+ </Param>\r
+ <Values name="TestBusOverrideValue" type="enum">\r
+ </Values>\r
+ \r
+ <Param type="u" size="1">\r
+ <Name>TestBusOverrideValue</Name> \r
+ <Default>0x0000</Default> \r
+ <Desc>1-Enter TestBusOverrideValue </Desc> \r
+ </Param>\r
+ <Param type="u" size="1" bits="1" valtype="DTST_GPIO_x_Rec_Status">\r
+ <Name>DTST_GPIO_0_Mux_Status</Name> \r
+ <Default>0x0</Default> \r
+ <Desc>0 - Enable\Disable Mem</Desc> \r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>DTST_GPIO_0_Mux_ChooseBit</Name> \r
+ <Default>0</Default> \r
+ <Desc>Override the bit location on bus for GPIO 0 [0..15]</Desc> \r
+ </Param>\r
+ \r
+ <Param type="u" size="1" bits="1" valtype="DTST_GPIO_x_Rec_Status">\r
+ <Name>DTST_GPIO_1_Mux_Status</Name> \r
+ <Default>0x0</Default> \r
+ <Desc>0 - Enable\Disable Mem</Desc> \r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>DTST_GPIO_1_Mux_ChooseBit</Name> \r
+ <Default>0</Default> \r
+ <Desc>Override the bit location on bus for GPIO 1 [0..15]</Desc> \r
+ </Param>\r
+ <Param type="u" size="1" bits="1" valtype="DTST_GPIO_x_Rec_Status">\r
+ <Name>DTST_GPIO_2_Mux_Status</Name> \r
+ <Default>0x0</Default> \r
+ <Desc>0 - Enable\Disable Mem</Desc> \r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>DTST_GPIO_2_Mux_ChooseBit</Name> \r
+ <Default>0</Default> \r
+ <Desc>Override the bit location on bus for GPIO 2 [0..15]</Desc> \r
+ </Param>\r
+\r
+</Command>\r
+ \r
+\r
+<!-- ******************************************************* --> \r
+<!-- ******************************************************* --> \r
+<!-- Read DTST Memory --> \r
+<!-- ******************************************************* --> \r
+<!-- ******************************************************* --> \r
+<Command name="DRP_DTST_Memory_Read" type="cc">\r
+ <Cat>Spec 1.1</Cat> \r
+ <Macro>\r
+ <![CDATA[ \r
+\r
+ _DTST_Mem_Use = %1\r
+ _DTST_filename = %2\r
+ _DTST_Mem_Allocated_Size = %3\r
+ _Trx_on = %4\r
+ \r
+ if _Trx_on == 0 then \r
+ #Save Current DTST Status\r
+ \r
+ Send_HCI_VS_Read_Memory 0xFF02, 0x2001F204 ,4\r
+ Wait_HCI_Command_Complete_VS_Read_Memory_Event 5000, any, HCI_VS_Read_Memory, 0x00, &DtstCtrl \r
+ Send_HCI_VS_Read_Memory 0xFF02, 0x2001F210 ,4\r
+ Wait_HCI_Command_Complete_VS_Read_Memory_Event 5000, any, HCI_VS_Read_Memory, 0x00, &DtstMemCtrl\r
+ Send_HCI_VS_Read_Memory 0xFF02, 0x2001F218 ,4\r
+ Wait_HCI_Command_Complete_VS_Read_Memory_Event 5000, any, HCI_VS_Read_Memory, 0x00, &DtstParamL \r
+ Send_HCI_VS_Read_Memory 0xFF02, 0x2001F21C ,4\r
+ Wait_HCI_Command_Complete_VS_Read_Memory_Event 5000, any, HCI_VS_Read_Memory, 0x00, &DtstParamM\r
+ Send_HCI_VS_Read_Memory 0xFF02, 0x2001F220 ,4\r
+ Wait_HCI_Command_Complete_VS_Read_Memory_Event 5000, any, HCI_VS_Read_Memory, 0x00, &TestOverrideSel\r
+ Send_HCI_VS_Read_Memory 0xFF02, 0x2001F224 ,4\r
+ Wait_HCI_Command_Complete_VS_Read_Memory_Event 5000, any, HCI_VS_Read_Memory, 0x00, &GpioSelMux1\r
+ Send_HCI_VS_Read_Memory 0xFF02, 0x2001F228 ,4\r
+ Wait_HCI_Command_Complete_VS_Read_Memory_Event 5000, any, HCI_VS_Read_Memory, 0x00, &GpioSelMux2\r
+ Send_HCI_VS_Read_Memory 0xFF02, 0x2001F230 ,4\r
+ Wait_HCI_Command_Complete_VS_Read_Memory_Event 5000, any, HCI_VS_Read_Memory, 0x00, &SpecialRecordingEn \r
+ \r
+ # Configure memory for dump\r
+ #************************************************************************************************************# \r
+ #Make sure DTST Disabled\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F206, 0x0000, 0x0010 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+ FileName1 = _DTST_filename\r
+ \r
+ clk_select=0x0c\r
+ # WRITE _test_clk_mux_sel to DTST_CTRL Register\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F206, clk_select, 0x000F \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+ \r
+ # WRITE _test_clk_mux_sel to DTST_CTRL Register\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F206, 0XF, 0x000F \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+ \r
+ # WRITE _test_clk_mux_sel to DTST_CTRL Register\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F206, clk_select, 0x000F \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+ # config _DTST_Mem_Mode=2 \r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F210, 0x0008, 0x000C \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+ #Disable SCR memory clk -- iram_med_en , iram_high_en = 0\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x20014002, 0x0000, 0x0006 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ #Configure size of allocated memory\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F210, _DTST_Mem_Allocated_Size<<8, 0x0300 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+ \r
+ #Set Memory allocation in SCR_CTRL\r
+ \r
+ if(_DTST_Mem_Allocated_Size == 0) then\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x20014002, 0x0006, 0x0006 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ if(_DTST_Mem_Use > 0 ) then\r
+ pause " Mem use exceed allocated memory please Fix!"\r
+ exit\r
+ end if\r
+ elseif(_DTST_Mem_Allocated_Size == 1) then\r
+ # Set Mid to "1" and High to "0"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x20014002, 0x0004, 0x0006 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ if(_DTST_Mem_Use > 2 ) then\r
+ pause "Mem use exceed allocated memory please Fix!"\r
+ exit\r
+ end if\r
+ else\r
+ if(_DTST_Mem_Use > 16 ) then\r
+ pause " Mem use exceed allocated memory please Fix!"\r
+ exit\r
+ end if\r
+ # Set Mid to "0" and High to "0"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x20014002, 0x0000, 0x0006 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ end if\r
+\r
+ #Read Stop_Address\r
+ Send_HCI_VS_Read_Memory 0xFF02, 0x2001F22C ,2\r
+ Wait_HCI_Command_Complete_VS_Read_Memory_Event 5000, any, HCI_VS_Read_Memory, 0x00, &stp_addr\r
+ \r
+ \r
+ #log "stop adr = %d",stp_addr\r
+ #DTST_MEM_OCP_PARAMS - write start_address\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F216, stp_addr+1, 0x0FFF \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ # WRITE DTST Enable to DTST_CTRL Register\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F206, 0x0010, 0x0010 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ # config _DTST_Mem_Addr_Load =1 \r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F210, 0x0010, 0x0010 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ # config _DTST_Mem_Enable=1\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F210, 0x0001, 0x0001 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ sleep 10 \r
+ \r
+ \r
+\r
+ #save results to file\r
+ WriteFile FileName1, 0, ""\r
+\r
+ # read 1st block - from stp_addr+1 to buffer_end\r
+ block_size = ((_DTST_Mem_Use)*1024-(stp_addr)*4-4)\r
+ \r
+ log "Block Size = : " + block_size + "Stop Addr = " + stp_addr \r
+ While (block_size>0)\r
+ chunk_size = Min(block_size,200)\r
+ Send_HCI_VS_Read_Memory_Block_From_DTST 0xFD7F, 0x2001F200 , chunk_size\r
+ Wait_HCI_Command_Complete_VS_Read_Memory_Block_From_DTST_Event 5000, any, HCI_VS_Read_Memory_Block_From_DTST, 0x00, &mydata\r
+ WriteFile FileName1, 1, StrData(mydata) \r
+ WriteFile FileName1, 1, "\n"\r
+ block_size-=chunk_size\r
+ \r
+ Wend\r
+ \r
+ # Reset start address\r
+ \r
+ #Make sure DTST Disabled\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F206, 0x0000, 0x0010 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+ #DTST_MEM_OCP_PARAMS - write start_address\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F216, 0, 0x0FFF \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ # WRITE DTST Enable to DTST_CTRL Register\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F206, 0x0010, 0x0010 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ # config _DTST_Mem_Addr_Load =1 \r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F210, 0x0010, 0x0010 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ # read 2st block - from buffer_start to stp_addr\r
+ block_size = (stp_addr+1)*4\r
+ While (block_size>0)\r
+ chunk_size = Min(block_size,200)\r
+ Send_HCI_VS_Read_Memory_Block_From_DTST 0xFD7F, 0x2001F200 , chunk_size\r
+ Wait_HCI_Command_Complete_VS_Read_Memory_Block_From_DTST_Event 5000, any, HCI_VS_Read_Memory_Block_From_DTST, 0x00, &mydata\r
+ WriteFile FileName1, 1, StrData(mydata) \r
+ WriteFile FileName1, 1, "\n"\r
+ block_size-=chunk_size\r
+ Wend\r
+\r
+ \r
+ \r
+ \r
+ \r
+ #************************************# \r
+ #RESTORING ALL SAVED PARAMS\r
+ #************************************#\r
+ \r
+ \r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x2001F204, DtstCtrl\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x2001F210, DtstMemCtrl\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x2001F218, DtstParamL\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x2001F21C, DtstParamM\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x2001F220, TestOverrideSel\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x2001F224, GpioSelMux1\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x2001F228, GpioSelMux2\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x2001F230, SpecialRecordingEn\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+\r
+ else\r
+ Log "***** DTST_Memory_Read *****" \r
+ \r
+ # Configure memory for dump\r
+ #************************************************************************************************************# \r
+ #Make sure DTST Disabled\r
+ Send_NFC_TRX_Read_Modify_Write 0x2001F206, 0x0000, 0x0010 \r
+\r
+ FileName1 = _DTST_filename\r
+ \r
+ clk_select=0x0c\r
+ # WRITE _test_clk_mux_sel to DTST_CTRL Register\r
+ Send_NFC_TRX_Read_Modify_Write 0x2001F206, clk_select, 0x000F \r
+\r
+ \r
+ # WRITE _test_clk_mux_sel to DTST_CTRL Register\r
+ Send_NFC_TRX_Read_Modify_Write 0x2001F206, 0XF, 0x000F \r
+\r
+ \r
+ # WRITE _test_clk_mux_sel to DTST_CTRL Register\r
+ Send_NFC_TRX_Read_Modify_Write 0x2001F206, clk_select, 0x000F \r
+\r
+ # config _DTST_Mem_Mode=2 \r
+ Send_NFC_TRX_Read_Modify_Write 0x2001F210, 0x0008, 0x000C \r
+\r
+ #Disable SCR memory clk -- iram_med_en , iram_high_en = 0\r
+ Send_NFC_TRX_Read_Modify_Write 0x20014002, 0x0000, 0x0006 \r
+ #Configure size of allocated memory\r
+ Send_NFC_TRX_Read_Modify_Write 0x2001F210, _DTST_Mem_Allocated_Size<<8, 0x0300 \r
+\r
+ Log "***** DTST_Memory_Read: Set Memory allocation in SCR_CTRL *****" \r
+ #Set Memory allocation in SCR_CTRL\r
+ \r
+ if(_DTST_Mem_Allocated_Size == 0) then\r
+ Send_NFC_TRX_Read_Modify_Write 0x20014002, 0x0006, 0x0006 \r
+ if(_DTST_Mem_Use > 0 ) then\r
+ pause " Mem use exceed allocated memory please Fix!"\r
+ exit\r
+ end if\r
+ elseif(_DTST_Mem_Allocated_Size == 1) then\r
+ # Set Mid to "1" and High to "0"\r
+ Send_NFC_TRX_Read_Modify_Write 0x20014002, 0x0004, 0x0006 \r
+ if(_DTST_Mem_Use > 2 ) then\r
+ pause "Mem use exceed allocated memory please Fix!"\r
+ exit\r
+ end if\r
+ else\r
+ if(_DTST_Mem_Use > 16 ) then\r
+ pause " Mem use exceed allocated memory please Fix!"\r
+ exit\r
+ end if\r
+ # Set Mid to "0" and High to "0"\r
+ Send_NFC_TRX_Read_Modify_Write 0x20014002, 0x0000, 0x0006 \r
+ end if\r
+\r
+ Log "***** DTST_Memory_Read: Read Stop_Address *****"\r
+ #Read Stop_Address\r
+ Send_NFC_TRX_Read 0x2001F22C, "any"\r
+ stp_addr = NFC_TRX_RESULT\r
+ \r
+ log "stop adr = %d",stp_addr\r
+ #DTST_MEM_OCP_PARAMS - write start_address\r
+ Send_NFC_TRX_Read_Modify_Write 0x2001F216, stp_addr+1, 0x0FFF \r
+ Log "***** DTST_Memory_Read: DTST_CTRL Register *****"\r
+ # WRITE DTST Enable to DTST_CTRL Register\r
+ Send_NFC_TRX_Read_Modify_Write 0x2001F206, 0x0010, 0x0010 \r
+ Log "***** DTST_Memory_Read: DTST_Mem_Addr_Load *****"\r
+ # config _DTST_Mem_Addr_Load =1 \r
+ Send_NFC_TRX_Read_Modify_Write 0x2001F210, 0x0010, 0x0010 \r
+ Log "***** DTST_Memory_Read: DTST_Mem_Enable *****"\r
+ # config _DTST_Mem_Enable=1\r
+ Send_NFC_TRX_Read_Modify_Write 0x2001F210, 0x0001, 0x0001 \r
+ \r
+ sleep 10 \r
+ \r
+ Log "***** DTST_Memory_Read: save results to file *****" \r
+\r
+ #save results to file\r
+ WriteFile FileName1, 0, ""\r
+\r
+ # read 1st block - from stp_addr+1 to buffer_end\r
+ block_size = ((_DTST_Mem_Use)*1024-(stp_addr)*4-4)\r
+ \r
+ log "Block Size = : " + block_size + "Stop Addr = " + stp_addr \r
+ While (block_size>0)\r
+ chunk_size = Min(block_size,200)\r
+ Send_NFC_TRX_Read_Memory_Block_DTST 0x2001F200, chunk_size\r
+ mydata = NFC_TRX_RESULT\r
+ WriteFile FileName1, 1, StrData(mydata) \r
+ WriteFile FileName1, 1, "\n"\r
+ block_size-=chunk_size\r
+ \r
+ Wend\r
+ \r
+ # Reset start address\r
+ \r
+ #Make sure DTST Disabled\r
+ Send_NFC_TRX_Read_Modify_Write 0x2001F206, 0x0000, 0x0010 \r
+\r
+ #DTST_MEM_OCP_PARAMS - write start_address\r
+ Send_NFC_TRX_Read_Modify_Write 0x2001F216, 0, 0x0FFF \r
+ \r
+ # WRITE DTST Enable to DTST_CTRL Register\r
+ Send_NFC_TRX_Read_Modify_Write 0x2001F206, 0x0010, 0x0010 \r
+ \r
+ # config _DTST_Mem_Addr_Load =1 \r
+ Send_NFC_TRX_Read_Modify_Write 0x2001F210, 0x0010, 0x0010 \r
+ \r
+ # read 2st block - from buffer_start to stp_addr\r
+ block_size = (stp_addr+1)*4\r
+ While (block_size>0)\r
+ chunk_size = Min(block_size,200)\r
+ Send_NFC_TRX_Read_Memory_Block_DTST 0x2001F200, chunk_size\r
+ mydata = NFC_TRX_RESULT\r
+ WriteFile FileName1, 1, StrData(mydata) \r
+ WriteFile FileName1, 1, "\n"\r
+ block_size-=chunk_size\r
+ Wend\r
+\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ endif \r
+ Log "***** DTST_Memory_Read: End *****" \r
+ \r
+#************************************************************************************************************# \r
+ \r
+ ]]> \r
+ </Macro>\r
+ <Param type="u" size="1">\r
+ <Name>DTST_Mem_Use</Name> \r
+ <Default>0</Default> \r
+ <Desc>How Many Kbytes to Physical Read in the allocated memory max of 16kB and less than the allocated memory in kBytes</Desc> \r
+ </Param>\r
+ <!--<Param type="u" size="1" bits="2" valtype="DTST_Mem_Max_Use">\r
+ <Name>DTST_Mem_Max_Use</Name> \r
+ <Default>0x04</Default> \r
+ <Desc>Selects Memory Size </Desc> \r
+ </Param> -->\r
+ <Param type="u" size="1">\r
+ <Name>DTST_filename</Name> \r
+ <Default>"C:\Temp\DTST_results.txt"</Default> \r
+ <Desc> Chose the Path and filename </Desc> \r
+ </Param>\r
+ <Param type="u" size="1" bits="4" valtype="dtst_mem_allocated_size">\r
+ <Name>DTST_Mem_Allocated_Size</Name> \r
+ <Default>0x00</Default> \r
+ <Desc>Selects Allocated DTST Memory </Desc> \r
+ </Param>\r
+ \r
+ <Param type="u" size="1" bits="4" valtype="DisEn">\r
+ <Name>Trx_on</Name> \r
+ <Default>0x00</Default> \r
+ <Desc>Working with trx or not </Desc> \r
+ </Param>\r
+</Command>\r
+ \r
+\r
+<!-- ******************************************************* --> \r
+<!-- ******************************************************* --> \r
+<!-- DTST BT Fast Recording --> \r
+<!-- ******************************************************* --> \r
+<!-- ******************************************************* --> \r
+<Command name="DRP_BT_DTST_Memory_Configuration" type="cc">\r
+ <Cat>Spec 1.1</Cat> \r
+ <Macro>\r
+ <![CDATA[ \r
+\r
+ _DTST_Mem_Enable = %1\r
+ _DTST_Enable = %2\r
+ _DTST_Signal_sel = %3\r
+ _DTST_Module_sel = %4\r
+ _DTST_Clk_Sel = %5\r
+ _DTST_Mem_Use = %7\r
+ _DTST_Mem_Step_Size = %8\r
+ _DTST_Mem_Word_Select = %9\r
+ _DTST_Mem_Offset = %10\r
+ _DTST_Mem_Wrap_Enable = %11\r
+ _DTST_Sleep_Time = %12\r
+ _DTST_Mem_Allocated_Size = %6\r
+ _DTST_Special_Recording_En = %13\r
+ _DTST_GPIO_0_Rec_Status = %14\r
+ _DTST_GPIO_0_Rec_ChooseBit = %16\r
+ _DTST_GPIO_1_Rec_Status = %15\r
+ _DTST_GPIO_1_Rec_ChooseBit = %17\r
+ \r
+ \r
+ Send_HCI_VS_Read_Memory 0xFF02, 0x2001F204 ,4\r
+ Wait_HCI_Command_Complete_VS_Read_Memory_Event 5000, any, HCI_VS_Read_Memory, 0x00, &DtstCtrl \r
+ Send_HCI_VS_Read_Memory 0xFF02, 0x2001F210 ,4\r
+ Wait_HCI_Command_Complete_VS_Read_Memory_Event 5000, any, HCI_VS_Read_Memory, 0x00, &DtstMemCtrl\r
+ Send_HCI_VS_Read_Memory 0xFF02, 0x2001F218 ,4\r
+ Wait_HCI_Command_Complete_VS_Read_Memory_Event 5000, any, HCI_VS_Read_Memory, 0x00, &DtstParamL \r
+ Send_HCI_VS_Read_Memory 0xFF02, 0x2001F21C ,4\r
+ Wait_HCI_Command_Complete_VS_Read_Memory_Event 5000, any, HCI_VS_Read_Memory, 0x00, &DtstParamM\r
+ Send_HCI_VS_Read_Memory 0xFF02, 0x2001F220 ,4\r
+ Wait_HCI_Command_Complete_VS_Read_Memory_Event 5000, any, HCI_VS_Read_Memory, 0x00, &TestOverrideSel\r
+ Send_HCI_VS_Read_Memory 0xFF02, 0x2001F224 ,4\r
+ Wait_HCI_Command_Complete_VS_Read_Memory_Event 5000, any, HCI_VS_Read_Memory, 0x00, &GpioSelMux1\r
+ Send_HCI_VS_Read_Memory 0xFF02, 0x2001F228 ,4\r
+ Wait_HCI_Command_Complete_VS_Read_Memory_Event 5000, any, HCI_VS_Read_Memory, 0x00, &GpioSelMux2\r
+ Send_HCI_VS_Read_Memory 0xFF02, 0x2001F230 ,4\r
+ Wait_HCI_Command_Complete_VS_Read_Memory_Event 5000, any, HCI_VS_Read_Memory, 0x00, &SpecialRecordingEn\r
+\r
+ \r
+ #******************* DRP DTST REG CONFIG *******************************************************#\r
+ \r
+ #Dmem Flag Register=0\r
+ #Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x0019326E, 0x0\r
+ #Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+ \r
+ #Config DTST_CTRL\r
+ \r
+ #Config Module\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F204, _DTST_Module_sel<<8 , 0x0700 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ #Config deseried Signal\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F204, _DTST_Signal_sel, 0x00FF \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ #Select Clk\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F206, _DTST_Clk_Sel, 0x000F \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+ #Change Allocation of DTST Availble Memory\r
+ \r
+ #Disable SCR memory clk -- iram_med_en , iram_high_en = 0\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x20014002, 0x0000, 0x0006 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ #Make sure DTST Disabled\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F206, 0x0000, 0x0010 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ #Configure size of allocated memory\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F210, _DTST_Mem_Allocated_Size<<8, 0x0300 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ #Set Memory allocation in SCR_CTRL\r
+ \r
+ \r
+ if(_DTST_Mem_Allocated_Size == 0) then\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x20014002, 0x0006, 0x0006 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ if(_DTST_Mem_Use > 0 ) then\r
+ pause " Mem use exceed allocated memory please Fix!"\r
+ exit\r
+ end if\r
+ if(_DTST_Mem_Offset > 0 ) then\r
+ pause " Offset exceed allocated memory please Fix!"\r
+ exit\r
+ end if\r
+ elseif(_DTST_Mem_Allocated_Size == 1) then\r
+ # Set Mid to "0" and High to "1"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x20014002, 0x0004, 0x0006 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ if(_DTST_Mem_Use > 2 ) then\r
+ pause "Mem use exceed allocated memory please Fix!"\r
+ exit\r
+ end if\r
+ if(_DTST_Mem_Offset > 2 ) then\r
+ pause " Offset exceed allocated memory please Fix!"\r
+ exit\r
+ end if\r
+ else\r
+ if(_DTST_Mem_Use > 16 ) then\r
+ pause " Mem use exceed allocated memory please Fix!"\r
+ exit\r
+ end if\r
+ if(_DTST_Mem_Offset > 16 ) then\r
+ pause " Offset exceed allocated memory please Fix!"\r
+ exit\r
+ end if\r
+ # Set Mid to "0" and High to "0"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x20014002, 0x0000, 0x0006 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ end if\r
+ \r
+ mDTST_Mem_Max_Use=(_DTST_Mem_Use*1024)/4-1\r
+ #Trunc Number\r
+ mDTST_Mem_Max_Use /=1 \r
+ \r
+ #Configure Mem Max Use\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F218, mDTST_Mem_Max_Use, 0x0FFF \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ #Configure Step Size 2/4Bytes #Word Select 16Lsb | 16MSB\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F218, _DTST_Mem_Word_Select<<13 | _DTST_Mem_Step_Size<<12, 0x3000 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ #Select offset DTST_MEM_SIG_REC_PARAMS_1 dtst_mem_offset\r
+ mDTST_Mem_Offset = (_DTST_Mem_Offset*1024)-1\r
+ mDTST_Mem_Offset /= 1\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F21A, mDTST_Mem_Offset, 0x0FFF \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ #SET DTST Mem Mode to Recording \r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F210, 0x0000, 0x000C \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+ #SET special Recording En\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x2001F230, _Dtst_Special_Recording_En\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+ \r
+ #SET GP_IO_MUX_SEL2\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F228, DTST_GPIO_0_Rec_Status | DTST_GPIO_1_Rec_Status<<1 , 0x0003 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F228, DTST_GPIO_0_Rec_ChooseBit<<8, 0x1F00 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F22A, DTST_GPIO_1_Rec_ChooseBit, 0x001F \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+ #############\r
+ #DTST Enable#\r
+ #############\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F206, _DTST_Enable<<4, 0x0010 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+ #Configure WRAP En\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F21A, _DTST_Mem_Wrap_Enable<<12, 0x1000 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+ #Clear Memory saved stop address\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F22E, 0x0001, 0x0001 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+ #Enable DTST Memory Only When set to 1 recording starts!\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F210, _DTST_Mem_Enable, 0x0001 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+ #Only if recording starts then the stop recording enable according to user sleep time\r
+ if(_DTST_Mem_Enable == 1) then\r
+ # wait DTST_Sleep_Time micro-sec \r
+ sleep _DTST_Sleep_Time+5\r
+ \r
+ #Configure WRAP En\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F21A, 0, 0x1000 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ #w8 for full cycle of recording finish (max time is ~7 milisecond\r
+ sleep 1000\r
+ #Disable DTST Memory Only When set to 1 recording starts!\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F210,0, 0x0001 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ #DTST Disable\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F206,0, 0x0010 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ end if\r
+ \r
+ #Write Ready to record Bit dmem_dtst_recording_ind \r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200102AC,1, 0x0001 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ \r
+#************************************# \r
+RESTORING ALL SAVED PARAMS\r
+#************************************#\r
+ \r
+ \r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x2001F204, DtstCtrl\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x2001F210, DtstMemCtrl\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x2001F218, DtstParamL\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x2001F21C, DtstParamM\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x2001F220, TestOverrideSel\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x2001F224, GpioSelMux1\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x2001F228, GpioSelMux2\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x2001F230, SpecialRecordingEn\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+#************************************************************************************************************# \r
+ \r
+ ]]> \r
+ </Macro>\r
+ <Param type="u" size="1" bits="1" valtype="DTST_Mem_Enable">\r
+ <Name>DTST_Mem_Enable</Name> \r
+ <Default>1</Default> \r
+ <Desc>0 - Enable Disable Start Recording</Desc> \r
+ </Param>\r
+ \r
+ <Param type="u" size="1" bits="1" valtype="DTST_Enable">\r
+ <Name>DTST_Enable</Name> \r
+ <Default>1</Default> \r
+ <Desc>0 - Enable\Disable DTST Module</Desc> \r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>DTST_Signal_sel</Name> \r
+ <Default>0x00</Default> \r
+ <Desc>1-Selects the signals to Mux </Desc> \r
+ </Param>\r
+ <Param type="u" size="1" bits="4" valtype="dtst_Module_sel">\r
+ <Name>DTST_Module_sel</Name> \r
+ <Default>0x00</Default> \r
+ <Desc>Selects the DRP Module </Desc> \r
+ </Param>\r
+ \r
+ <Param type="u" size="1" bits="4" valtype="test_clk_mux_sel">\r
+ <Name>DTST_Clk_Sel</Name> \r
+ <Default>0x00</Default> \r
+ <Desc>Selects the output clock on test_clk output</Desc> \r
+ </Param>\r
+ <Param type="u" size="1" bits="4" valtype="dtst_mem_allocated_size">\r
+ <Name>DTST_Mem_Allocated_Size</Name> \r
+ <Default>0x00</Default> \r
+ <Desc>Selects Allocated DTST Memory </Desc> \r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>DTST_Mem_Use</Name> \r
+ <Default>0</Default> \r
+ <Desc>How Many Kbytes to Physical Record in allocated memory Max [4Kybets]</Desc> \r
+ </Param>\r
+ <Param type="u" size="1" bits="1" valtype="DTST_Mem_Step_Size">\r
+ <Name>DTST_Mem_Step_Size</Name> \r
+ <Default>0x00</Default> \r
+ <Desc>0 - Select Step Size in bytes </Desc> \r
+ </Param>\r
+ <Param type="u" size="1" bits="1" valtype="DTST_Mem_Word_Select">\r
+ <Name>DTST_Mem_Word_Select</Name> \r
+ <Default>0x00</Default> \r
+ <Desc>Selects DTST Mem Word MSB LSB</Desc> \r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>DTST_Mem_Offset</Name> \r
+ <Default>0</Default> \r
+ <Desc>1-Selects the DTST Mem Offset up to Allocated Memeory in KByte </Desc> \r
+ </Param>\r
+ <Param type="u" size="1" bits="1" valtype="DTST_Mem_Wrap_Enable">\r
+ <Name>DTST_Mem_Wrap_Enable</Name> \r
+ <Default>1</Default> \r
+ <Desc>0 - Enable\Disable Wrap</Desc> \r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>DTST_sleep_time</Name> \r
+ <Default>0x0000</Default> \r
+ <Desc>Selects how length of the recording procudure in us (sleep between redord enable/disable </Desc> \r
+ </Param>\r
+ <Param type="u" size="1" bits="4" valtype="dtst_Special_Recording_En">\r
+ <Name>DTST_Special_Recording_En</Name> \r
+ <Default>0x00</Default> \r
+ <Desc>Set Special Record Enable Register </Desc> \r
+ </Param>\r
+ \r
+ <Param type="u" size="1" bits="1" valtype="DTST_GPIO_x_Rec_Status">\r
+ <Name>DTST_GPIO_0_Rec_Status</Name> \r
+ <Default>0x0</Default> \r
+ <Desc>0 - Enable\Disable Mem</Desc> \r
+ </Param>\r
+ \r
+ <Param type="u" size="1" bits="1" valtype="DTST_GPIO_x_Rec_Status">\r
+ <Name>DTST_GPIO_1_Rec_Status</Name> \r
+ <Default>0x0</Default> \r
+ <Desc>0 - Enable\Disable Mem</Desc> \r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>DTST_GPIO_0_Rec_ChooseBit</Name> \r
+ <Default>0</Default> \r
+ <Desc>Write the reCorded bit location on bus for GPIO 0 [0..31]</Desc> \r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>DTST_GPIO_1_Rec_ChooseBit</Name> \r
+ <Default>0</Default> \r
+ <Desc>Write the reCorded bit location on bus for GPIO 1 [0..31]</Desc> \r
+ </Param>\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ \r
+</Command>\r
+ \r
+\r
+<!-- ******************************************************* --> \r
+<!-- ******************************************************* --> \r
+<!-- Stop DTST Fast Recording Without internal 'stop' --> \r
+<!-- ******************************************************* --> \r
+<!-- ******************************************************* --> \r
+<Command name="DRP_Stop_DTST_Memory_Conf" type="cc">\r
+ <Cat>Spec 1.1</Cat> \r
+ <Macro>\r
+ <![CDATA[ \r
+\r
+#************************************************end recording ************************************************************#\r
+ #Configure WRAP Disable\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F21A, 0, 0x1000 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ #w8 for full cycle of recording finish (max time is ~7 milisecond\r
+ sleep 1000\r
+ #Disable DTST Memory \r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F210,0, 0x0001 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ #DTST Disable\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x2001F206,0, 0x0010 \r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+\r
+#************************************************************************************************************# \r
+ \r
+ ]]> \r
+ </Macro>\r
+ \r
+</Command>\r
+ \r
+<!-- ******************************************************* --> \r
+<!-- ******************************************************* --> \r
+<!-- DRP Power Levels Setting --> \r
+<!-- ******************************************************* --> \r
+<!-- ******************************************************* --> \r
+<Command name="DRP_Power_Levels_Setting" type="cc">\r
+ <Cat>Spec 1.1</Cat> \r
+ <Macro>\r
+ <![CDATA[ \r
+\r
+ _GFSKPowerValue= %1\r
+ _GFSKDeltaPowerValue = %2\r
+ _EDR2PowerValue = %3\r
+ _EDR2DeltaPowerValue= %4\r
+ _EDR3PowerValue = %5\r
+ _EDR3DeltaPowerValue = %6\r
+ \r
+ \r
+ \r
+ #enter power levels here \r
+GFSKPowerValueT=_GFSKPowerValue\r
+GFSKDeltaPowerValueT=_GFSKDeltaPowerValue\r
+EDR2PowerValueT=_EDR2PowerValue\r
+EDR2DeltaPowerValueT=_EDR2DeltaPowerValue\r
+EDR3PowerValueT=_EDR3PowerValue\r
+EDR3DeltaPowerValueT=_EDR3DeltaPowerValue\r
+\r
+FileNameGFSK="C:\Temp\GFSKPowerSet.txt"\r
+FileNameEDR2="C:\Temp\EDR2PowerSet.txt"\r
+FileNameEDR3="C:\Temp\EDR3PowerSet.txt"\r
+\r
+LoopNom=15\r
+\r
+#GFSK LOOP\r
+WriteFile FileNameGFSK, 0,"GFSKPowerValue=\""\r
+for loop=0 to ( LoopNom )\r
+GFSKPowerValueT=GFSKPowerValueT-GFSKDeltaPowerValueT\r
+valLT = GFSKPowerValueT&0x00ff\r
+valHT = GFSKPowerValueT&0xff00\r
+valH = valHT >> 8 \r
+valL = valLT << 8 \r
+GFSKPowerValue=valL+valH\r
+WriteFile FileNameGFSK,1, "%x",GFSKPowerValue\r
+next\r
+WriteFile FileNameGFSK, 1, "\""\r
+\r
+#GFSK LOOP\r
+WriteFile FileNameEDR2, 0,"EDR2PowerValue=\""\r
+for loop=0 to ( LoopNom )\r
+EDR2PowerValueT=EDR2PowerValueT-EDR2DeltaPowerValueT\r
+valLT = EDR2PowerValueT&0x00ff\r
+valHT = EDR2PowerValueT&0xff00\r
+valH = valHT >> 8 \r
+valL = valLT << 8 \r
+EDR2PowerValue=valL+valH\r
+WriteFile FileNameEDR2,1, "%x",EDR2PowerValue\r
+next\r
+WriteFile FileNameEDR2, 1, "\""\r
+\r
+#EDR3 LOOP\r
+WriteFile FileNameEDR3, 0,"EDR3PowerValue=\""\r
+for loop=0 to ( LoopNom )\r
+EDR3PowerValueT=EDR3PowerValueT-EDR3DeltaPowerValueT\r
+valLT = EDR3PowerValueT&0x00ff\r
+valHT = EDR3PowerValueT&0xff00\r
+valH = valHT >> 8 \r
+valL = valLT << 8 \r
+EDR3PowerValue=valL+valH\r
+WriteFile FileNameEDR3,1, "%x",EDR3PowerValue\r
+next\r
+WriteFile FileNameEDR3, 1, "\""\r
+\r
+ callfile "C:\Temp\GFSKPowerSet.txt"\r
+ callfile "C:\Temp\EDR2PowerSet.txt"\r
+ callfile "C:\Temp\EDR3PowerSet.txt"\r
+ \r
+\r
+#write GFSK POWER values\r
+Send_HCI_VS_Write_Memory_Block 0xFF05, 0x193356, 32,GFSKPowerValue\r
+Wait_HCI_Command_Complete_VS_Write_Memory_Block_Event 5000, any, HCI_VS_Write_Memory_Block, 0x00\r
+\r
+#write EDR2 POWER values\r
+Send_HCI_VS_Write_Memory_Block 0xFF05, 0x193376, 32,EDR2PowerValue\r
+Wait_HCI_Command_Complete_VS_Write_Memory_Block_Event 5000, any, HCI_VS_Write_Memory_Block, 0x00\r
+\r
+#write EDR3 POWER values\r
+Send_HCI_VS_Write_Memory_Block 0xFF05, 0x193396, 32,EDR3PowerValue\r
+Wait_HCI_Command_Complete_VS_Write_Memory_Block_Event 5000, any, HCI_VS_Write_Memory_Block, 0x00\r
+ \r
+]]> \r
+ </Macro>\r
+ <Param type="u" size="1">\r
+ <Name>GFSKMaxPowerValue</Name> \r
+ <Default>0x0000</Default> \r
+ <Desc>1-Selects GFSK Max Power </Desc> \r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>GFSKDeltaPowerValue</Name> \r
+ <Default>0x0000</Default> \r
+ <Desc>1-Selects GFSK Delta Power </Desc> \r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>EDR2MaxPowerValue</Name> \r
+ <Default>0x0000</Default> \r
+ <Desc>1-Selects EDR2 Max Power </Desc> \r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>EDR2DeltaPowerValue</Name> \r
+ <Default>0x0000</Default> \r
+ <Desc>1-Selects EDR2 Delta Power </Desc> \r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>EDR3MaxPowerValue</Name> \r
+ <Default>0x0000</Default> \r
+ <Desc>1-Selects EDR3 Max Power </Desc> \r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>EDR3DeltaPowerValue</Name> \r
+ <Default>0x0000</Default> \r
+ <Desc>1-Selects EDR3 Delta Power </Desc> \r
+ </Param>\r
+</Command>\r
+\r
+<Command name="DRP_Mux_DTST_BT_IP" type="cc">\r
+ <Cat>Spec 1.1</Cat> \r
+ <Macro>\r
+ <![CDATA[ \r
+ _test_mux_Signal_sel= %1\r
+ _dtst_Module_sel = %2\r
+ _shift_select= %3\r
+ _test_clk_mux_sel = %4\r
+ _test_dtst_enable = %5\r
+ _test_mirror_enable = %6\r
+ _test_apll_clk_select = %7\r
+ _TestBusOverrideSelect = %8\r
+ _TestBusOverrideValue = %9\r
+\r
+ \r
+ # Dont Set config module settings\r
+ ############################ \r
+\r
+ #BTIP Configu module configuraton\r
+ #Send_HCIPP_Set_IO_Pin_Mux_BTIP 0x01, 0x07\r
+\r
+ \r
+ # Set debug module settings \r
+ ########################### \r
+ \r
+ # Write to TEST SELECT REGISTER: \r
+ # DRX is muxed out \r
+\r
+ # DBG(9:5)\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x200E300C, 0x0000\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00\r
+\r
+ # DBG(4:0)\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x200E300A, 0x0000\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00\r
+\r
+ # DBG(15:0) enable\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x200E3002, 0x0004\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, 0xFF01, 0x00\r
+\r
+ #**************************************************************************#\r
+ sleep 100\r
+ #**************************************************************************#\r
+ #BTIP AOD module (GCM level) configuration(10 lsb's the other 7 by pass this module )\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x001A605c, 0x0000\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+ #**************************************************************************#\r
+ sleep 100\r
+ #**************************************************************************#\r
+ \r
+ #quattro TOP related mux is done by \r
+ \r
+\r
+ \r
+\r
+ #******************* DRP DTST REG CONFIG *******************************************************#\r
+ \r
+ #Clear dtst En \r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, 0<<4, 0x0010\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ # WRITE test_mux_Signal_sel to DTST_CTRL Register\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190204, _test_mux_Signal_sel, 0x00ff\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ # WRITE _dtst_Module_sel to DTST_CTRL Register\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190204, _dtst_Module_sel<<8, 0x0700\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ # WRITE _shift_select to DTST_CTRL Register\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190204, _shift_select<<12, 0xf000\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ # WRITE _test_clk_mux_sel to DTST_CTRL Register\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, _test_clk_mux_sel, 0x000f\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ # WRITE _test_mirror_enable to DTST_CTRL Register\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, _test_mirror_enable<<8, 0x0100\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ # WRITE _test_apll_clk_select to DTST_CTRL Register\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, _test_apll_clk_select<<12, 0x1000\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+\r
+ \r
+ log "test_dtst_enable %d", _test_dtst_enable\r
+ if _test_dtst_enable > 0 then\r
+\r
+ # WRITE _test_dtst_enable to DTST_CTRL Register\r
+ # Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, 0x1B, 0x001f\r
+ # Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ # WRITE DTST Enable to DTST_CTRL Register\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, _test_dtst_enable<<4, 0x0010\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ # WRITE _test_apll_clk_select to DTST_CTRL Register\r
+ end if\r
+ \r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00191260,0, 0x0001\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ if _test_clk_mux_sel > 3 & _test_clk_mux_sel < 7 then \r
+ # WRITE _test_mirror_enable to DTST_CTRL Register\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00191260,1, 0x0001\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ else\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00191260,0, 0x0001\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ end if \r
+ log "test_dtst_enable %d", _test_dtst_enable\r
+ \r
+ #******************* DRP DTST REG CONFIG END *******************************************************#\r
+ \r
+ #******************* DRP DTST Bus Override *******************************************************#\r
+ # WRITE TestBusOverrideSelect to Register\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x0019021e, _TestBusOverrideSelect\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+\r
+ # WRITE TestBusOverrideValue to Register\r
+ Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x0019021c, _TestBusOverrideValue\r
+ Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00\r
+\r
+ if _TestBusOverrideSelect > 0 then\r
+ # WRITE _test_mirror_enable to DTST_CTRL Register\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190102, 1<<12, 0x1000\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ # WRITE _test_apll_clk_select to DTST_CTRL Register\r
+ end if\r
+ #******************* DRP DTST Bus Override End *******************************************************#\r
+ ]]> \r
+ </Macro>\r
+ <Param type="u" size="1">\r
+ <Name>Signal_sel</Name> \r
+ <Default>0x00</Default> \r
+ <Desc>1-Selects the signals to Mux </Desc> \r
+ </Param>\r
+ <Param type="u" size="1" bits="4" valtype="dtst_Module_sel">\r
+ <Name>Module_sel</Name> \r
+ <Default>0x00</Default> \r
+ <Desc>Selects the DRP Module </Desc> \r
+ </Param>\r
+ <Param type="u" size="1" bits="4" valtype="shift_select">\r
+ <Name>shift_select</Name> \r
+ <Default>0x00</Default> \r
+ <Desc>0 - Select Number of bits to mux </Desc> \r
+ </Param>\r
+ <Param type="u" size="1" bits="4" valtype="test_clk_mux_sel">\r
+ <Name>test_clk_mux_sel</Name> \r
+ <Default>0x00</Default> \r
+ <Desc>Selects the output clock on test_clk output</Desc> \r
+ </Param>\r
+ <Param type="u" size="1" bits="1" valtype="test_dtst_enable">\r
+ <Name>test_dtst_enable</Name> \r
+ <Default>1</Default> \r
+ <Desc>0 - Enable\Disable DTST</Desc> \r
+ </Param>\r
+ <Param type="u" size="1" bits="1" valtype="test_mirror_enable">\r
+ <Name>test_mirror_enable</Name> \r
+ <Default>0</Default> \r
+ <Desc>0 - Enable Mirrore </Desc> \r
+ </Param>\r
+ <Param type="u" size="1" bits="1" valtype="test_apll_clk_select">\r
+ <Name>test_apll_clk_select</Name> \r
+ <Default>0</Default> \r
+ </Param>\r
+ <Param type="u" size="1" bits="2" valtype="TestBusOverrideSelect">\r
+ <Name>TestBusOverrideSelect</Name> \r
+ <Default>0</Default> \r
+ </Param>\r
+ <Values name="TestBusOverrideValue" type="enum">\r
+ </Values>\r
+ \r
+ <Param type="u" size="1">\r
+ <Name>TestBusOverrideValue</Name> \r
+ <Default>0x0000</Default> \r
+ <Desc>1-Enter TestBusOverrideValue </Desc> \r
+ </Param>\r
+</Command>\r
+\r
+<Command name="Compare_Data2Str" type="sc">\r
+ <Cat>Spec 1.1</Cat>\r
+ <Macro><![CDATA[\r
+ \r
+ _DATA_ = %1\r
+ _STR_ = %2\r
+ \r
+ a = _STR_\r
+ b = _DATA_\r
+## Log "data: %X", b\r
+## Log "str: " +a\r
+ al = Len(_STR_)\r
+ bl = Size(_DATA_)\r
+\r
+ str_b = ""\r
+ For i = 0 To bl-1\r
+ m = Mid(b,i,1)\r
+ If (Val(m) < 0x10 ) Then\r
+ m_new = "0" + Hex(Val(m))\r
+ Else\r
+ m_new = Hex(Val(m))\r
+ End IF \r
+ str_b += m_new + ":"\r
+## Log "m %0X", m\r
+## Log "" +str_b \r
+ Next\r
+\r
+ str_bl = Len(str_b)\r
+ str_b_new = Mid(str_b,0,str_bl-1)\r
+## Log "str of dtat: " +str_b_new\r
+ \r
+ ## String compare, case Insensative\r
+ str_data_comp_tmp = StrComp(a, str_b_new,1)\r
+ If (str_data_comp_tmp != 0) Then\r
+ str_data_comp = 0\r
+ Else\r
+ str_data_comp = 1\r
+ End IF\r
+ \r
+ Log "str_data_comp: " +str_data_comp\r
+ \r
+ \r
+ ]]></Macro>\r
+ \r
+ <Param type="x" size="511" label="Input_Data">\r
+ <Name>Input Data</Name>\r
+ <Default>0x0</Default>\r
+ <Desc>Data to be compared</Desc>\r
+ </Param>\r
+ \r
+ <Param type="s" size="1000" label="Input_String">\r
+ <Name>Input String</Name>\r
+ <Default>"00"</Default>\r
+ <Desc>String to be compared</Desc>\r
+ </Param>\r
+ \r
+ <Param type="u" size="1">\r
+ <Name>CompRes</Name>\r
+ <Default>str_data_comp</Default>\r
+ <Desc>Compare Resoult between Data and String</Desc>\r
+ </Param>\r
+ \r
+</Command>\r
+\r
+<Command name="HCI_45nm_Debug_Muxing_macro" type="vc" >\r
+ <Cat>spec 1.1</Cat>\r
+ <Macro><![CDATA[\r
+ _setup = %1 \r
+ _physical_io = %2\r
+ _top_addr = (0x200CE100 + (_physical_io * 2)) \r
+ #**********Supports maximal number of 256 physical pins.************\r
+ \r
+ _layer_2_select = %3\r
+ \r
+ \r
+ #EXTRACT bit fields from layer 2\r
+ \r
+ \r
+ _layer_2_top_select = (_layer_2_select & 0x000000FF) \r
+ #************First 8 bits are for TOP layer value config **************\r
+ \r
+ \r
+ _layer_2_bt_select_value = ( _layer_2_select >> 8 ) & 0x0000000F \r
+ #******************Next 4 bits are for BT layer select value*********************\r
+ \r
+ \r
+ _layer_2_bt_select_address_offset = ( _layer_2_select >> 12) & 0x00FF \r
+ #******************Next 8 bits are for BT layer select address offset********************\r
+ \r
+ #residue and offset are set to write to the correct bits in the register\r
+ residue = _layer_2_bt_select_address_offset % 4\r
+ offset = (_layer_2_bt_select_address_offset - residue) / 2\r
+ \r
+ \r
+ func_conf_reg1_address = 0x200EF510 + offset\r
+ _layer_2_bt_select_value = _layer_2_bt_select_value << (residue*4)\r
+ mask = 0x000F << (residue*4)\r
+ \r
+ #bt_debug_x selection (incase "is bt_debug" field equals '1') \r
+ _layer_2_bt_debug_number = ( _layer_2_select >> 20 ) & 0x000F \r
+ \r
+ #"is bt_debug" field (eqauls '1' if layer 2 configures to bt_debug lines) \r
+ _layer_2_is_bt_debug_exist = ( _layer_2_select >> 24 ) & 0x000F \r
+ \r
+ if(_layer_2_is_bt_debug_exist != 0) then\r
+ _debug_module_select = %4\r
+ _signal_in_module_select = %5\r
+ else\r
+ _debug_module_select = 0x11\r
+ _signal_in_module_select = 0x00\r
+ end if\r
+ \r
+ #"is bt_func" field (eqauls 'x' (= 1-9) if layer 2 configures through bt_func 'x' OR configured to '10' for TOP functional or else '0') \r
+ _layer_2_bt_func_x = ( _layer_2_select >> 28 ) & 0x000F\r
+ log "_layer_2_bt_func_x %d", _layer_2_bt_func_x\r
+ \r
+ #Confiugre top spinner (physical pin)\r
+ \r
+ log "Top configuration:"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, _top_addr, _layer_2_top_select, 0x001F\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ log "TOP has been configured"\r
+ \r
+ if(_debug_module_select != 0x10) then\r
+ if(_layer_2_bt_func_x != 0) then\r
+ \r
+ #Confiugre BTFUNC in bt_config\r
+ log "BT_FUNC in bt_config Configuration:"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, func_conf_reg1_address, _layer_2_bt_select_value , mask\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ if(_layer_2_bt_func_x > 0 && _layer_2_bt_func_x < 10) then\r
+ if(_layer_2_is_bt_debug_exist == 1) then\r
+ if(_layer_2_bt_debug_number < 10) then\r
+ # *****************AOD_DEBUG_CTL_HIGH CONFIGURE to '0'***************************\r
+ _aod_debug_mask = 0x1 << (_layer_2_bt_func_x - 1)\r
+ log "AOD GCM DEBUG_CTL_HIGH configures to '0':"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E605E, 0x0000, _aod_debug_mask\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ log "_layer_2_bt_func_x %d", _layer_2_bt_func_x\r
+ log "_aod_debug_mask %d", _aod_debug_mask\r
+ end if\r
+ end if\r
+ end if\r
+ else\r
+ #Top functionals or bt_debug (direct) signals\r
+ if(_layer_2_is_bt_debug_exist == 1)then\r
+ if(_layer_2_bt_debug_number<10) then\r
+ #************ AOD_DEBUG_CTL_LOW CONFIGURE***************\r
+ _aod_debug_mask = 0x1 << _layer_2_bt_debug_number\r
+ log "AOD GCM DEBUG_CTL_LOW configures to '0':" \r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E605C, 0x0000, _aod_debug_mask\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ end if\r
+ end if\r
+ end if \r
+ \r
+ \r
+ #*************************SETTING ARMIO TO OUTPUT***********************************\r
+ \r
+ if(_setup == 0) then\r
+ armio_lock = 0x0\r
+ armio_number = 0x0\r
+ if(_layer_2_select == 0xA0000100 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 0x0\r
+ end if\r
+ if((_layer_2_select == 0x3000B001) ||(_layer_2_select == 0x3000B004) || (_layer_2_select == 0x3000B000)) then\r
+ armio_lock = 0x1\r
+ armio_number = 0x3\r
+ end if\r
+ if(_layer_2_select == 0x4000C000 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 0x4\r
+ end if\r
+ if(_layer_2_select == 0x5000D000 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 0x5\r
+ end if\r
+ if(_layer_2_select == 0x6000E000 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 0x6\r
+ end if\r
+ if(_layer_2_select == 0x7000F000 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 0x7\r
+ end if\r
+ if(_layer_2_select == 0x2020A000 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 0x2\r
+ end if\r
+ if((_layer_2_select == 0x10009000 )||(_layer_2_select == 0xA0001100)) then\r
+ armio_lock = 0x1\r
+ armio_number = 0x1\r
+ end if\r
+ if(_layer_2_select == 0xA0005100 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 0xC\r
+ end if\r
+ if(_layer_2_select == 0xA0006100 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 0xD\r
+ end if\r
+ if(_layer_2_select == 0xA0007100 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 0xE\r
+ end if\r
+ if(_layer_2_select == 0xA0008100 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 0xF\r
+ end if\r
+ if(_layer_2_select == 0xA0002100 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 0x10\r
+ end if\r
+ if(_layer_2_select == 0xA0003100 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 0x11\r
+ end if\r
+ if(armio_lock == 0x1) then\r
+ log "ARMIO set as output:"\r
+ Send_HCI_VS_Configure_ARMIO 0xFF1A, armio_number, 0x0\r
+ Wait_HCI_Command_Complete_VS_Configure_ARMIO_Event 5000, any, HCI_VS_Configure_ARMIO, 0x00\r
+ end if\r
+ else\r
+ armio_lock = 0x0\r
+ armio_number = 0x0\r
+ \r
+ if(_layer_2_select == 0xA0000100 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 0x0\r
+ end if\r
+ if((_layer_2_select == 0x10009000) || (_layer_2_select == 0xA0001100) ) then\r
+ armio_lock = 0x1\r
+ armio_number = 0x1\r
+ end if\r
+ if((_layer_2_select == 0x2000A008) || (_layer_2_select == 0x2000A000)) then\r
+ armio_lock = 0x1\r
+ armio_number = 0x2\r
+ end if\r
+ if((_layer_2_select == 0x3000B008) || (_layer_2_select == 0x3000B001) || (_layer_2_select == 0x3000B000) ) then\r
+ armio_lock = 0x1\r
+ armio_number = 0x3\r
+ end if\r
+ if(_layer_2_select == 0x4000C008 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 0x4\r
+ end if\r
+ if(_layer_2_select == 0x5000D008 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 0x5\r
+ end if\r
+ if((_layer_2_select == 0x1000E008) || (_layer_2_select == 0x6000E008) || (_layer_2_select == 0x6000E000) ) then\r
+ armio_lock = 0x1\r
+ armio_number = 0x6\r
+ end if\r
+ if((_layer_2_select == 0x7000F008) || (_layer_2_select == 0x7000F000) ) then\r
+ armio_lock = 0x1\r
+ armio_number = 0x7\r
+ end if\r
+ if(_layer_2_select == 0x80010008 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 0x8\r
+ end if\r
+ if(_layer_2_select == 0x90011008 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 0x9\r
+ end if\r
+ if(_layer_2_select == 0xA0005100 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 12\r
+ end if\r
+ if(_layer_2_select == 0xA0006100 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 13\r
+ end if\r
+ if(_layer_2_select == 0xA0007100 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 14\r
+ end if\r
+ if(_layer_2_select == 0xA0008100 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 15\r
+ end if\r
+ if(_layer_2_select == 0xA0002100 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 16\r
+ end if\r
+ if(_layer_2_select == 0xA0003100 ) then\r
+ armio_lock = 0x1\r
+ armio_number = 17\r
+ end if\r
+ if(armio_lock == 0x1) then\r
+ log "ARMIO set as output:"\r
+ Send_HCI_VS_Configure_ARMIO 0xFF1A, armio_number, 0x0\r
+ Wait_HCI_Command_Complete_VS_Configure_ARMIO_Event 5000, any, HCI_VS_Configure_ARMIO, 0x00\r
+ end if\r
+ end if \r
+ end if \r
+ log "LAYER 2 has been configured"\r
+ \r
+ #**************************************LAYER 3 - BT: Debug Module Configure***********************************\r
+ if(_layer_2_is_bt_debug_exist == 1 || _debug_module_select == 0x10) then\r
+ \r
+ if(_debug_module_select != 0x10) then\r
+ # Enable Debug signals bus output\r
+ log "Enable Debug signals bus output:"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E3002, 0x0004, 0x0004\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ # Debug Bus supports signals from bt_debug_0 - bt_debug_9\r
+ if(_layer_2_bt_debug_number<10) then\r
+ \r
+ _bt_debug_residue_of_4 = _layer_2_bt_debug_number % 4\r
+ _debug_select_register_address = 0x200E300A + ((_layer_2_bt_debug_number -_bt_debug_residue_of_4) / 2)\r
+ _debug_module_select_value = _debug_module_select << (_bt_debug_residue_of_4*4)\r
+ _debug_module_select_mask = 0x000F << (_bt_debug_residue_of_4*4)\r
+ log "Debug module configuration:"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, _debug_select_register_address, _debug_module_select_value , _debug_module_select_mask\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ end if\r
+ log "LAYER 3 has been configured"\r
+ else\r
+ log "Configure the GPIOs from the top:"\r
+ if(_layer_2_bt_func_x>0 && _layer_2_bt_func_x<10) then\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, func_conf_reg1_address, _layer_2_bt_select_value , mask\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ end if \r
+ end if\r
+ #**************************************LAYER 4 - Configure a signal in the chosen Module***********************************\r
+ log "Enable the clock signal from GCM test bus"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E6010, 0x0020, 0x0020\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ \r
+ #case PCMI\r
+ if (_debug_module_select == 0x08) then\r
+ if (_layer_2_bt_debug_number<10) then\r
+ _bt_debug_residue_of_2 = _layer_2_bt_debug_number % 2\r
+ log "bt_debug_2_residue %d", _bt_debug_residue_of_2\r
+ pcmi_base_address = 0x200E5064 + (_layer_2_bt_debug_number - _bt_debug_residue_of_2) \r
+ layer4_signal_value = _signal_in_module_select << (_bt_debug_residue_of_2 * 6)\r
+ mask_layer4 = 0x3F << (_bt_debug_residue_of_2 * 6)\r
+ log "Configure signal in PCMI module:"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, pcmi_base_address, layer4_signal_value , mask_layer4\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ end if \r
+ elseif (_debug_module_select == 0x01) then\r
+ #case MCU\r
+ if (_layer_2_bt_debug_number<10) then\r
+ _bt_debug_residue_of_2 = _layer_2_bt_debug_number % 2\r
+ log "bt_debug_2_residue %d", _bt_debug_residue_of_2\r
+ mcu_base_address = 0x200B8004 + (_layer_2_bt_debug_number - _bt_debug_residue_of_2) \r
+ layer4_signal_value = _signal_in_module_select << (_bt_debug_residue_of_2 * 8)\r
+ mask_layer4 = 0x7F << (_bt_debug_residue_of_2 * 8)\r
+ log "Configure signal in MCU module:"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, mcu_base_address, layer4_signal_value , mask_layer4\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ end if \r
+ elseif(_debug_module_select == 0x02) then\r
+ #case SDIO\r
+ if (_layer_2_bt_debug_number<10) then\r
+ sdio_base_address = 0x200E2018 + ((_layer_2_bt_debug_number - _bt_debug_residue_of_4) /2 )\r
+ layer4_signal_value = _signal_in_module_select << (_bt_debug_residue_of_4 * 4)\r
+ mask_layer4 = 0x07 << (_bt_debug_residue_of_4 * 4)\r
+ log "Configure signal in SDIO module:"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, sdio_base_address, layer4_signal_value , mask_layer4\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ end if\r
+ elseif(_debug_module_select == 0x03) then\r
+ #case HCI DMA\r
+ if (_layer_2_bt_debug_number<10) then\r
+ hci_dma_base_address = 0x200EF12A + ((_layer_2_bt_debug_number - _bt_debug_residue_of_4) /2 )\r
+ layer4_signal_value = _signal_in_module_select << (_bt_debug_residue_of_4 * 4)\r
+ mask_layer4 = 0x0F << (_bt_debug_residue_of_4 * 4)\r
+ log "Configure signal in HCI DMA module:"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, hci_dma_base_address, layer4_signal_value , mask_layer4\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ end if \r
+ elseif(_debug_module_select == 0x04) then\r
+ #case OCP_IC\r
+ if (_layer_2_bt_debug_number<10) then\r
+ _bt_debug_residue_of_2 = _layer_2_bt_debug_number % 2\r
+ ocp_ic_base_address = 0x200EF616 + (_layer_2_bt_debug_number - _bt_debug_residue_of_2) \r
+ layer4_signal_value = _signal_in_module_select << (_bt_debug_residue_of_2 * 8)\r
+ mask_layer4 = 0x7F << (_bt_debug_residue_of_2 * 8)\r
+ log "Configure signal in OCP_IC module:"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, ocp_ic_base_address, layer4_signal_value , mask_layer4\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ end if\r
+ elseif(_debug_module_select == 0x10) then \r
+ #case AOD GCM\r
+ if(_layer_2_bt_func_x > 0 & _layer_2_bt_func_x < 10) then\r
+ # *****************AOD_DEBUG_CTL_HIGH CONFIGURE to '1'***************************\r
+ _aod_debug_mask = 0x1 << (_layer_2_bt_func_x - 1)\r
+ _aod_debug_value = 0x1 << (_layer_2_bt_func_x - 1)\r
+ log "Allow signal from AOD GCM (Debug_ctl_high) module:"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E605E, _aod_debug_value, _aod_debug_mask\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ _bt_func_residue_of_2 = (_layer_2_bt_func_x - 1) % 2\r
+ aod_gcm_base_address = 0x200E604C + ((_layer_2_bt_func_x - 1) - _bt_func_residue_of_2) \r
+ layer4_signal_value = _signal_in_module_select << (_bt_func_residue_of_2 * 8)\r
+ mask_layer4 = 0x3F << (_bt_func_residue_of_2 * 8)\r
+ else\r
+ #************ AOD_DEBUG_CTL_LOW CONFIGURE***************\r
+ _aod_debug_mask = 0x1 << _layer_2_bt_debug_number\r
+ _aod_debug_value = 0x1 << _layer_2_bt_debug_number \r
+ log "Allow signal from AOD GCM (Debug_ctl_low) module:" \r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x200E605C, _aod_debug_value, _aod_debug_mask\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ \r
+ _bt_debug_residue_of_2 = _layer_2_bt_debug_number % 2\r
+ aod_gcm_base_address = 0x200E604C + (_layer_2_bt_debug_number - _bt_debug_residue_of_2) \r
+ layer4_signal_value = _signal_in_module_select << (_bt_debug_residue_of_2 * 8)\r
+ mask_layer4 = 0x3F << (_bt_debug_residue_of_2 * 8)\r
+ end if\r
+ log "Configure signal in AOD GCM module:"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, aod_gcm_base_address, layer4_signal_value , mask_layer4\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ elseif(_debug_module_select == 0x07) then\r
+ #case BLUETOOTH\r
+ if (_layer_2_bt_debug_number<10) then\r
+ _bt_debug_residue_of_2 = _layer_2_bt_debug_number % 2\r
+ bluetooth_base_address = 0x200E0F00 + (_layer_2_bt_debug_number - _bt_debug_residue_of_2) \r
+ layer4_signal_value = _signal_in_module_select << (_bt_debug_residue_of_2 * 7)\r
+ mask_layer4 = 0x7F << (_bt_debug_residue_of_2 * 7)\r
+ log "Configure signal in BLUETOOTH module:"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, bluetooth_base_address, layer4_signal_value , mask_layer4\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ end if\r
+ elseif(_debug_module_select == 0x05) then\r
+ #case UART\r
+ if (_layer_2_bt_debug_number<10) then\r
+ uart_base_address = 0x200E1020 + ((_layer_2_bt_debug_number - _bt_debug_residue_of_4) /2 )\r
+ layer4_signal_value = _signal_in_module_select << (_bt_debug_residue_of_4 * 4)\r
+ mask_layer4 = 0x0F << (_bt_debug_residue_of_4 * 4)\r
+ log "Configure signal in UART module:"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, uart_base_address, layer4_signal_value , mask_layer4\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ end if\r
+ elseif(_debug_module_select == 0x0C) then\r
+ #case BLE DMA\r
+ if (_layer_2_bt_debug_number<10) then\r
+ ble_dma_base_address = 0x200EF32A + ((_layer_2_bt_debug_number - _bt_debug_residue_of_4) /2 )\r
+ layer4_signal_value = _signal_in_module_select << (_bt_debug_residue_of_4 * 4)\r
+ mask_layer4 = 0x0F << (_bt_debug_residue_of_4 * 4)\r
+ log "Configure signal in BLE DMA module:"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, ble_dma_base_address, layer4_signal_value , mask_layer4\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ end if \r
+ elseif(_debug_module_select == 0x0D) then\r
+ #case AVPR DMA\r
+ if (_layer_2_bt_debug_number<10) then\r
+ avpr_dma_base_address = 0x200EF42A + ((_layer_2_bt_debug_number - _bt_debug_residue_of_4) /2 )\r
+ layer4_signal_value = _signal_in_module_select << (_bt_debug_residue_of_4 * 4)\r
+ mask_layer4 = 0x0F << (_bt_debug_residue_of_4 * 4)\r
+ log "Configure signal in AVPR DMA module:"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, avpr_dma_base_address, layer4_signal_value , mask_layer4\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ end if \r
+ elseif(_debug_module_select == 0x0F) then\r
+ #case NFC DMA\r
+ if (_layer_2_bt_debug_number<10) then\r
+ nfc_dma_base_address = 0x200EF22A + ((_layer_2_bt_debug_number - _bt_debug_residue_of_4) /2 )\r
+ layer4_signal_value = _signal_in_module_select << (_bt_debug_residue_of_4 * 4)\r
+ mask_layer4 = 0x0F << (_bt_debug_residue_of_4 * 4)\r
+ log "Configure signal in NFC DMA module:"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, nfc_dma_base_address, layer4_signal_value , mask_layer4\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ end if \r
+ elseif(_debug_module_select == 0x09) then \r
+ #case SOC GCM\r
+ if (_layer_2_bt_debug_number<10) then\r
+ _bt_debug_residue_of_2 = _layer_2_bt_debug_number % 2\r
+ soc_gcm_base_address = 0x200E604C + (_layer_2_bt_debug_number - _bt_debug_residue_of_2) \r
+ layer4_signal_value = _signal_in_module_select << (_bt_debug_residue_of_2 * 8)\r
+ mask_layer4 = 0x3F << (_bt_debug_residue_of_2 * 8)\r
+ log "Configure signal in SOC GCM module:"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, soc_gcm_base_address, layer4_signal_value , mask_layer4\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ end if\r
+ elseif(_debug_module_select == 0x0A) then\r
+ #case AES\r
+ if (_layer_2_bt_debug_number<10) then\r
+ _bt_debug_residue_of_2 = _layer_2_bt_debug_number % 2\r
+ aes_base_address = 0x2002F00E + (_layer_2_bt_debug_number - _bt_debug_residue_of_2) \r
+ layer4_signal_value = _signal_in_module_select << (_bt_debug_residue_of_2 * 8)\r
+ mask_layer4 = 0x1F << (_bt_debug_residue_of_2 * 8)\r
+ log "Configure signal in AES module:"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, aes_base_address, layer4_signal_value , mask_layer4\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ end if\r
+ elseif(_debug_module_select == 0x0B) then\r
+ #case BLE PHYIF\r
+ if (_layer_2_bt_debug_number<10) then\r
+ _bt_debug_residue_of_2 = _layer_2_bt_debug_number % 2\r
+ phyif_base_address = 0x2002E072 + (_layer_2_bt_debug_number - _bt_debug_residue_of_2) \r
+ layer4_signal_value = _signal_in_module_select << (_bt_debug_residue_of_2 * 8)\r
+ mask_layer4 = 0xFF << (_bt_debug_residue_of_2 * 8)\r
+ log "Configure signal in BLE PHYIF module:"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, phyif_base_address, layer4_signal_value , mask_layer4\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ end if\r
+ elseif(_debug_module_select == 0x0E) then\r
+ #case AVPR Processor \r
+ if (_layer_2_bt_debug_number<10) then\r
+ _bt_debug_residue_of_2 = _layer_2_bt_debug_number % 2\r
+ avpr_base_address = 0x2007A004 + (_layer_2_bt_debug_number - _bt_debug_residue_of_2) \r
+ layer4_signal_value = _signal_in_module_select << (_bt_debug_residue_of_2 * 8)\r
+ mask_layer4 = 0x7F << (_bt_debug_residue_of_2 * 8)\r
+ log "Configure signal in AVPR PROCESSOR module:"\r
+ Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, avpr_base_address, layer4_signal_value , mask_layer4\r
+ Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00\r
+ end if \r
+ end if \r
+ log "LAYER 4 has been configured"\r
+ \r
+ #*************************************End of layer 3 **********************************************\r
+ end if\r
+ \r
+]]></Macro>\r
+ \r
+ <Param type="u" size="1" valtype="setup_select" label="setup_label">\r
+ <Name>Setup select</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>Select the setup (wl8/wl9)</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="setup_label == 0">\r
+ <Param type="u" size="1" valtype="physical_io_select" label="physical_io_label">\r
+ <Name>Physical IO select</Name>\r
+ <Default>0x0C</Default>\r
+ <Desc>Select the physical IO on which you would like to connect the probe</Desc>\r
+ </Param>\r
+ \r
+ \r
+ <Param cond="physical_io_label == 0">\r
+ <Param type="u" size="4" valtype="spi_clk_select" label="spi_clk_label">\r
+ <Name>spi clk Select</Name>\r
+ <Value>0x00000008</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 1"> \r
+ <Param type="u" size="4" label="spi_din_label" valtype="spi_din_select">\r
+ <Name>spi din Select</Name>\r
+ <Default>0x01000008</Default> \r
+ </Param>\r
+ \r
+ <Param cond="(spi_din_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 2">\r
+ <Param type="u" size="4" valtype="spi_dout_select" label="spi_dout_label">\r
+ <Name>spi dout Select</Name>\r
+ <Default>0x01200008</Default> \r
+ </Param>\r
+ <Param cond="(spi_dout_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 3">\r
+ <Param type="u" size="4" valtype="spi_csx_select" label="spi_csx_label">\r
+ <Name>spi csx Select</Name>\r
+ <Default>0x01300008</Default> \r
+ </Param>\r
+ <Param cond="(spi_csx_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 4">\r
+ <Param type="u" size="4" valtype="sdio_d1_select" label="sdio_d1_label">\r
+ <Name>sdio d1 Select</Name>\r
+ <Default>0x01400008</Default> \r
+ </Param>\r
+ \r
+ <Param cond="(sdio_d1_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ \r
+ <Param cond="physical_io_label == 5">\r
+ <Param type="u" size="4" valtype="sdio_d2_select" label="sdio_d2_label">\r
+ <Name>sdio d2 select</Name>\r
+ <Default>0x01500008</Default> \r
+ </Param>\r
+ <Param cond="(sdio_d2_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 6">\r
+ <Param type="u" size="4" valtype="sdio_irq_select" label="sdio_irq_label">\r
+ <Name>sdio irq select</Name>\r
+ <Default>0x01600008</Default> \r
+ </Param>\r
+ \r
+ <Param cond="(sdio_irq_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 7">\r
+ <Param type="u" size="4" valtype="wlan_sw_3v_select" label="wlan_sw_3v_label">\r
+ <Name>wlan sw 3v select</Name>\r
+ <Default>0x3000B001</Default> \r
+ </Param>\r
+ \r
+ <Param cond="(wlan_sw_3v_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 8">\r
+ <Param type="u" size="4" valtype="bt_hci_uart_tx_select" label="bt_hci_uart_tx_label">\r
+ <Name>bt hci uart tx select</Name>\r
+ <Default>0xA0005100</Default> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 9">\r
+ <Param type="u" size="4" valtype="bt_hci_uart_rx_select" label="bt_hci_uart_rx_label">\r
+ <Name>bt hci uart rx select</Name>\r
+ <Default>0xA0006100</Default> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 10">\r
+ <Param type="u" size="4" valtype="bt_hci_uart_cts_select" label="bt_hci_uart_cts_label">\r
+ <Name>bt hci uart cts select</Name>\r
+ <Default>0xA0007100</Default> \r
+ </Param>\r
+ \r
+ <Param cond="(bt_hci_uart_cts_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 11">\r
+ <Param type="u" size="4" valtype="bt_hci_uart_rts_select" label="bt_hci_uart_rts_label">\r
+ <Name>bt hci uart rts select</Name>\r
+ <Default>0xA0008100</Default> \r
+ </Param>\r
+ \r
+ <Param cond="(bt_hci_uart_rts_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 12">\r
+ <Param type="u" size="4" valtype="bt_host_wakeup_select" label="bt_host_wakeup_label">\r
+ <Name>bt host wakeup select</Name>\r
+ <Default>0x01000008</Default> \r
+ </Param>\r
+ \r
+ <Param cond="(bt_host_wakeup_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 13">\r
+ <Param type="u" size="4" valtype="bt_wakeup_select" label="bt_wakeup_label">\r
+ <Name>bt wakeup select</Name>\r
+ <Default>0x2020A000</Default> \r
+ </Param>\r
+ <Param cond="(bt_wakeup_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 14">\r
+ <Param type="u" size="4" valtype="debug_uart_tx_select" label="debug_uart_tx_label">\r
+ <Name>debug uart tx select (bt_func 3)</Name>\r
+ <Default>0x3000B000</Default> \r
+ </Param>\r
+ <Param cond="(debug_uart_tx_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 15">\r
+ <Param type="u" size="4" valtype="btfunc4_select" label="btfunc4_label">\r
+ <Name>BTFUNC4 Select</Name>\r
+ <Default>0x4000C000</Default> \r
+ </Param>\r
+ \r
+ <Param cond="(btfunc4_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 16">\r
+ <Param type="u" size="4" valtype="btfunc5_select" label="btfunc5_label">\r
+ <Name>btfunc5 select</Name>\r
+ <Default>0x5000D000</Default> \r
+ </Param>\r
+ <Param cond="(btfunc5_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 17">\r
+ <Param type="u" size="4" valtype="btfunc6_select" label="btfunc6_label">\r
+ <Name>btfunc6 select</Name>\r
+ <Default>0x6000E000</Default> \r
+ </Param>\r
+ <Param cond="(btfunc6_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 18">\r
+ <Param type="u" size="4" valtype="btfunc7_select" label="btfunc7_label">\r
+ <Name>btfunc7 select</Name>\r
+ <Default>0x7000F000</Default> \r
+ </Param>\r
+ <Param cond="(btfunc7_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 19">\r
+ <Param type="u" size="4" valtype="aud_clk_select" label="aud_clk_label">\r
+ <Name>aud clk select</Name>\r
+ <Default>0x01A00008</Default> \r
+ </Param>\r
+ <Param cond="(aud_clk_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 20">\r
+ <Param type="u" size="4" valtype="aud_fsync_select" label="aud_fsync_label">\r
+ <Name>aud fsync select</Name>\r
+ <Default>0x01B00008</Default> \r
+ </Param>\r
+ <Param cond="(aud_fsync_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 21">\r
+ <Param type="u" size="4" valtype="aud_in_select" label="aud_in_label">\r
+ <Name>aud in select</Name>\r
+ <Default>0x01C00008</Default> \r
+ </Param>\r
+ <Param cond="(aud_in_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 22">\r
+ <Param type="u" size="4" valtype="aud_out_select" label="aud_out_label">\r
+ <Name>aud out select</Name>\r
+ <Default>0x3000B004</Default> \r
+ </Param>\r
+ \r
+ <Param cond="(aud_out_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 23">\r
+ <Param type="u" size="4" valtype="fm_i2s_clk_select" label="fm_i2s_clk_label">\r
+ <Name>fm i2s clk select</Name>\r
+ <Default>0x00000008</Default> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 24">\r
+ <Param type="u" size="4" valtype="fm_i2s_fsync_select" label="fm_i2s_fsync_label">\r
+ <Name>fm i2s fsync select</Name>\r
+ <Default>0x01000008</Default> \r
+ </Param>\r
+ <Param cond="(fm_i2s_fsync_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 25">\r
+ <Param type="u" size="4" valtype="fm_i2s_di_select" label="fm_i2s_di_label">\r
+ <Name>fm i2s di select</Name>\r
+ <Default>0x01200008</Default> \r
+ </Param>\r
+ <Param cond="(fm_i2s_di_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label == 26">\r
+ <Param type="u" size="4" valtype="fm_i2s_do_select" label="fm_i2s_do_label">\r
+ <Name>fm i2s do select</Name>\r
+ <Default>0x01300008</Default> \r
+ </Param>\r
+ <Param cond="(fm_i2s_do_label & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="setup_label == 1">\r
+ <Param type="u" size="1" valtype="physical_io_select_wl9" label="physical_io_label_wl9">\r
+ <Name>Physical IO select_wl9</Name>\r
+ <Default>0x0C</Default>\r
+ <Desc>Select the physical IO on which you would like to connect the probe</Desc>\r
+ </Param>\r
+ \r
+ \r
+ <Param cond="physical_io_label_wl9 == 0">\r
+ <Param type="u" size="4" valtype="sdio_clk_select_wl9" label="sdio_clk_label_wl9">\r
+ <Name>sdio clk Select</Name>\r
+ <Default>0x1000E008</Default> \r
+ </Param>\r
+ \r
+ <Param cond="(sdio_clk_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 1"> \r
+ <Param type="u" size="4" label="sdio_cmd_label_wl9" valtype="sdio_cmd_select_wl9">\r
+ <Name>sdio cmd Select</Name>\r
+ <Default>0x2000A008</Default> \r
+ </Param>\r
+ \r
+ <Param cond="(sdio_cmd_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 2">\r
+ <Param type="u" size="4" valtype="sdio_D0_select_wl9" label="sdio_D0_label_wl9">\r
+ <Name>sdio D0 select</Name>\r
+ <Default>0x3000B008</Default> \r
+ </Param>\r
+ <Param cond="(sdio_D0_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 3">\r
+ <Param type="u" size="4" valtype="sdio_D3_select_wl9" label="sdio_D3_label_wl9">\r
+ <Name>sdio D3 Select</Name>\r
+ <Default>0x4000C008</Default> \r
+ </Param>\r
+ <Param cond="(sdio_D3_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 4">\r
+ <Param type="u" size="4" valtype="sdio_D1_select_wl9" label="sdio_D1_label_wl9">\r
+ <Name>sdio d1 Select</Name>\r
+ <Default>0x5000D008</Default> \r
+ </Param>\r
+ \r
+ <Param cond="(sdio_D1_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ \r
+ <Param cond="physical_io_label_wl9 == 5">\r
+ <Param type="u" size="4" valtype="sdio_D2_select_wl9" label="sdio_D2_label_wl9">\r
+ <Name>sdio D2 select</Name>\r
+ <Default>0x6000E008</Default> \r
+ </Param>\r
+ <Param cond="(sdio_D2_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 6">\r
+ <Param type="u" size="4" valtype="wlan_irq_select_wl9" label="wlan_irq_label_wl9">\r
+ <Name>wlan irq select</Name>\r
+ <Default>0x7000F008</Default> \r
+ </Param>\r
+ \r
+ <Param cond="(wlan_irq_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 8">\r
+ <Param type="u" size="4" valtype="bt_hci_uart_tx_select_wl9" label="bt_hci_uart_tx_label_wl9">\r
+ <Name>bt hci uart tx select</Name>\r
+ <Default>0xA0005100</Default> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 9">\r
+ <Param type="u" size="4" valtype="bt_hci_uart_rx_select_wl9" label="bt_hci_uart_rx_label_wl9">\r
+ <Name>bt hci uart rx select</Name>\r
+ <Default>0xA0006100</Default> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 10">\r
+ <Param type="u" size="4" valtype="bt_hci_uart_cts_select_wl9" label="bt_hci_uart_cts_label_wl9">\r
+ <Name>bt hci uart cts select</Name>\r
+ <Default>0xA0007100</Default> \r
+ </Param>\r
+ \r
+ <Param cond="(bt_hci_uart_cts_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 11">\r
+ <Param type="u" size="4" valtype="bt_hci_uart_rts_select_wl9" label="bt_hci_uart_rts_label_wl9">\r
+ <Name>bt hci uart rts select</Name>\r
+ <Default>0x90011008</Default> \r
+ </Param>\r
+ \r
+ <Param cond="(bt_hci_uart_rts_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 12">\r
+ <Param type="u" size="4" valtype="bt_host_wakeup_select_wl9" label="bt_host_wakeup_label_wl9">\r
+ <Name>bt host wakeup select</Name>\r
+ <Default>0x10009000</Default> \r
+ </Param>\r
+ \r
+ <Param cond="(bt_host_wakeup_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 13">\r
+ <Param type="u" size="4" valtype="bt_wakeup_select_wl9" label="bt_wakeup_label_wl9">\r
+ <Name>bt wakeup select</Name>\r
+ <Default>0x2000A000</Default> \r
+ </Param>\r
+ \r
+ <Param cond="(bt_wakeup_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 14">\r
+ <Param type="u" size="4" valtype="bt_uart_debug_select_wl9" label="bt_uart_debug_label_wl9">\r
+ <Name>bt uart debug select</Name>\r
+ <Default>0x3000B000</Default> \r
+ </Param>\r
+ \r
+ <Param cond="(bt_uart_debug_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ \r
+ \r
+ <Param cond="physical_io_label_wl9 == 15">\r
+ <Param type="u" size="4" valtype="gpio_1_select_wl9" label="gpio_1_label_wl9">\r
+ <Name>gpio_1 select</Name>\r
+ <Default>0x4000C008</Default> \r
+ </Param>\r
+ \r
+ <Param cond="(gpio_1_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 16">\r
+ <Param type="u" size="4" valtype="gpio_2_select_wl9" label="gpio_2_label_wl9">\r
+ <Name>gpio_2 select</Name>\r
+ <Default>0x5000D008</Default> \r
+ </Param>\r
+ <Param cond="(gpio_2_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 17">\r
+ <Param type="u" size="4" valtype="gpio_3_select_wl9" label="gpio_3_label_wl9">\r
+ <Name>gpio_3 select</Name>\r
+ <Default>0x6000E000</Default> \r
+ </Param>\r
+ <Param cond="(gpio_3_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 18">\r
+ <Param type="u" size="4" valtype="gpio_4_select_wl9" label="gpio_4_label_wl9">\r
+ <Name>gpio_4 select</Name>\r
+ <Default>0x7000F000</Default> \r
+ </Param>\r
+ <Param cond="(gpio_4_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 19">\r
+ <Param type="u" size="4" valtype="bt_aud_clk_select_wl9" label="bt_aud_clk_label_wl9">\r
+ <Name>bt aud clk select</Name>\r
+ <Default>0x3000B008</Default> \r
+ </Param>\r
+ \r
+ <Param cond="(bt_aud_clk_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 20">\r
+ <Param type="u" size="4" valtype="bt_aud_fsync_select_wl9" label="bt_aud_fsync_label_wl9">\r
+ <Name>bt aud fsync select</Name>\r
+ <Default>0x90011008</Default> \r
+ </Param>\r
+ <Param cond="(bt_aud_fsync_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 21">\r
+ <Param type="u" size="4" valtype="bt_aud_in_select_wl9" label="bt_aud_in_label_wl9">\r
+ <Name>bt aud in select</Name>\r
+ <Default>0xA0000100</Default> \r
+ </Param>\r
+ <Param cond="(bt_aud_in_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 22">\r
+ <Param type="u" size="4" valtype="bt_aud_out_select_wl9" label="bt_aud_out_label_wl9">\r
+ <Name>bt aud out select</Name>\r
+ <Default>0xA0001100</Default> \r
+ </Param>\r
+ <Param cond="(bt_aud_out_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 31">\r
+ <Param type="u" size="4" valtype="uart_lte_rx_select_wl9" label="uart_lte_rx_label_wl9">\r
+ <Name>uart lte rx select</Name>\r
+ <Default>0x0000000A</Default> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 63">\r
+ <Param type="u" size="4" valtype="wlan_uart_debug_select_wl9" label="wlan_uart_debug_label_wl9">\r
+ <Name>wlan uart debug select</Name>\r
+ <Default>0x3000B001</Default> \r
+ </Param>\r
+ <Param cond="(wlan_uart_debug_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 70">\r
+ <Param type="u" size="4" valtype="wlan_rs232_tx_select_wl9" label="wlan_rs232_tx_label_wl9">\r
+ <Name>wlan rs232 tx select</Name>\r
+ <Default>0x4000C008</Default> \r
+ </Param>\r
+ <Param cond="(wlan_rs232_tx_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 71">\r
+ <Param type="u" size="4" valtype="wlan_rs232_rx_select_wl9" label="wlan_rs232_rx_label_wl9">\r
+ <Name>wlan rs232 rx select</Name>\r
+ <Default>0x5000D008</Default> \r
+ </Param>\r
+ <Param cond="(wlan_rs232_rx_label_wl9 & 0x0F000000) == 0x01000000">\r
+ <Param type="u" size="1" valtype="debug_module_select" label="debug_module_label">\r
+ <Name>Debug_module_select</Name>\r
+ <Default>0x07</Default>\r
+ <Desc>Select the BT:Debug Module</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x01">\r
+ <Param type="u" size="1" valtype="mcu_module_select">\r
+ <Name>MCU module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x02">\r
+ <Param type="u" size="1" valtype="sdio_module_select">\r
+ <Name>SDIO module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x03">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>HCI DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x04">\r
+ <Param type="u" size="1" valtype="ocp_ic_module_select">\r
+ <Name>OCP IC module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x05">\r
+ <Param type="u" size="1" valtype="uart_module_select">\r
+ <Name>UART module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x07">\r
+ <Param type="u" size="1" valtype="bluetooth_module_select">\r
+ <Name>BLUETOOTH module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x08">\r
+ <Param type="u" size="1" valtype="pcmi_module_select">\r
+ <Name>PCMI module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x09">\r
+ <Param type="u" size="1" valtype="soc_gcm_module_select">\r
+ <Name>SOC GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0A">\r
+ <Param type="u" size="1" valtype="aes_module_select">\r
+ <Name>AES module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0B">\r
+ <Param type="u" size="1" valtype="ble_phyif_module_select">\r
+ <Name>BLE_PHYIF module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ <Param cond="debug_module_label == 0x0C">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>BLE DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0D">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>AVPR DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0E">\r
+ <Param type="u" size="1" valtype="avpr_module_select">\r
+ <Name>AVPR Processor module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x0F">\r
+ <Param type="u" size="1" valtype="dma_module_select">\r
+ <Name>NFC DMA module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="debug_module_label == 0x10">\r
+ <Param type="u" size="1" valtype="aod_gcm_module_select">\r
+ <Name>AOD GCM module select</Name>\r
+ <Value>0x00</Value> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 264">\r
+ <Param type="u" size="4" valtype="aux_coex_gpio_0_select_wl9" label="aux_coex_gpio_0_label_wl9">\r
+ <Name>aux coex gpio 0 select</Name>\r
+ <Default>0x0000000A</Default> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 265">\r
+ <Param type="u" size="4" valtype="aux_coex_gpio_1_select_wl9" label="aux_coex_gpio_1_label_wl9">\r
+ <Name>aux coex gpio 1 select</Name>\r
+ <Default>0x0000000A</Default> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 266">\r
+ <Param type="u" size="4" valtype="aux_coex_gpio_2_select_wl9" label="aux_coex_gpio_2_label_wl9">\r
+ <Name>aux coex gpio 2 select</Name>\r
+ <Default>0x0000000A</Default> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ <Param cond="physical_io_label_wl9 == 267">\r
+ <Param type="u" size="4" valtype="aux_coex_gpio_3_select_wl9" label="aux_coex_gpio_3_label_wl9">\r
+ <Name>aux coex gpio 3 select</Name>\r
+ <Default>0x0000000A</Default> \r
+ </Param>\r
+ \r
+ </Param>\r
+ \r
+ \r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_Remote_OOB_Extended_Data_Request_Reply" type="sc" opcode="0xFF27">\r
+ <Cat>Lisbon</Cat>\r
+ <Param type="b" size="6">\r
+ <Name>BD Address</Name>\r
+ <Default>Bd_Addr</Default>\r
+ <Desc />\r
+ </Param>\r
+ <Param type="x" size="16" prop="r">\r
+ <Name>C_P192</Name>\r
+ <Default>"00000000000000000000000000000002"</Default>\r
+ <Desc>Simple pairing hash C</Desc>\r
+ </Param>\r
+ <Param type="x" size="16" prop="r">\r
+ <Name>R_P192</Name>\r
+ <Default>"00000000000000000000000000000001"</Default>\r
+ <Desc>Simple pairing Randomizer R</Desc>\r
+ </Param>\r
+ <Param type="x" size="16" prop="r">\r
+ <Name>C_P256</Name>\r
+ <Default>"00000000000000000000000000000002"</Default>\r
+ <Desc>Simple pairing hash C</Desc>\r
+ </Param>\r
+ <Param type="x" size="16" prop="r">\r
+ <Name>R_P256</Name>\r
+ <Default>"00000000000000000000000000000001"</Default>\r
+ <Desc>Simple pairing Randomizer R</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="Status">\r
+ <Name>Status</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>Status</Desc>\r
+ </Param>\r
+ <Param type="b" size="6">\r
+ <Name>BD Address</Name>\r
+ <Default>BD_ADDR</Default>\r
+ <Desc>BD Address of the Remote involved in simple pairing process</Desc>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Read_Local_OOB_Extended_Data" type="sc" opcode="0xFF28">\r
+ <Cat>Lisbon</Cat>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="Status">\r
+ <Name>Status</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>Status</Desc>\r
+ </Param>\r
+ <Param type="x" size="16" prop="r">\r
+ <Name>C_P192</Name>\r
+ <Default>"00000000000000000000000000000000"</Default>\r
+ <Desc>Simple pairing hash C P192</Desc>\r
+ </Param>\r
+ <Param type="x" size="16" prop="r">\r
+ <Name>R_P192</Name>\r
+ <Default>"00000000000000000000000000000000"</Default>\r
+ <Desc>Simple pairing Randomizer R P192</Desc>\r
+ </Param>\r
+ <Param type="x" size="16" prop="r">\r
+ <Name>C_P256</Name>\r
+ <Default>"00000000000000000000000000000000"</Default>\r
+ <Desc>Simple pairing hash C P256</Desc>\r
+ </Param>\r
+ <Param type="x" size="16" prop="r">\r
+ <Name>R_P256</Name>\r
+ <Default>"00000000000000000000000000000000"</Default>\r
+ <Desc>Simple pairing Randomizer R P256</Desc>\r
+ </Param>\r
+</Command>\r
+<!-- ================================================================== -->\r
+<Command name="New Commands" type="gb" />\r
+<!-- ================================================================== -->\r
+\r
+<Command name="HCI_VS_Enable_BT_secure_connection" type="vc" opcode="0xFDEB">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name> \r
+ <Default>0xFDEB</Default> \r
+ <Desc>This command enables BT secure connection mode</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="secure_connection_command_operation" label="SC_command_operation">\r
+ <Name>command_operation</Name>\r
+ <Default>00</Default>\r
+ <Desc>Defines the purpose of the command. The command can (1) set SC to enable/disable with fixed keys or (2) set general configuration.</Desc>\r
+ </Param>\r
+ <Param cond="SC_command_operation == 0">\r
+ <Param type="u" size="1" valtype="AES_mode">\r
+ <Name>secure_mode</Name>\r
+ <Default>00</Default>\r
+ <Desc>0x0 - BT secure connection is disabled, 0x01 - BT secure connection encryption is enabled, 0x02 - BT secure connection decryption is enabled,0xFF - Don\92t Change</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>handle</Name>\r
+ <Default>00</Default>\r
+ <Desc>Handle of the connection to be encrypted, 0-7 for specific handle, 0xff for not changing the handle</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Set encryption key</Name>\r
+ <Default>00</Default>\r
+ <Desc>Copy encryption key to link manager as it was generated from SSP. 0x0-don't copy, 0x1-Copy key to link manager</Desc>\r
+ </Param>\r
+ <Param type="x" size="16">\r
+ <Name>Encryption Key</Name>\r
+ <Default>"4C68384139F574D836BCF34E9DFB01BF"</Default>\r
+ <Desc>Key to be used by AES encryption</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="b0_b1_mode">\r
+ <Name>Set b0 mode</Name>\r
+ <Default>00</Default>\r
+ <Desc>0x0-AES mechanism will manage it automatically, 0x1-copy b0 initial value and handle it in AES mechanism, 0x2-fixed b0</Desc>\r
+ </Param>\r
+ <Param type="x" size="16">\r
+ <Name>b0 vector</Name>\r
+ <Default>"4C68384139F574D836BCF34E9DFB01BF"</Default>\r
+ <Desc>B0 to be used by AES encryption</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="b0_b1_mode">\r
+ <Name>Set b1 mode</Name>\r
+ <Default>00</Default>\r
+ <Desc>0x0-AES mechanism will manage it automatically, 0x1-copy b1 initial value and handle it in AES mechanism, 0x2-fixed b1</Desc>\r
+ </Param>\r
+ <Param type="x" size="16">\r
+ <Name>b1 vector</Name>\r
+ <Default>"4C68384139F574D836BCF34E9DFB01BF"</Default>\r
+ <Desc>B1 to be used by AES encryption</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="SC_command_operation == 1">\r
+ <Param type="u" size="1" valtype="mic_mode">\r
+ <Name>MIC_enable</Name>\r
+ <Default>00</Default>\r
+ <Desc>0x0 - disable MIC, 0x01 - Enable MIC and include MIC in payload length (debug mode), 0x02 - Enable MIC and exclude MIC in payload length (SPEC definition), 0xFF - don't change</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Override CRC</Name>\r
+ <Default>00</Default>\r
+ <Desc>Determine whether MIC effects CRC scheme. 0x00-MIC failure will not effect CRC, 0xFF - don't change, Other-MIC failure will cause to bad CRC</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Disconnection MIC threshold</Name>\r
+ <Default>03</Default>\r
+ <Desc>Determine how many MIC failure resulting in disconnection. 0xFF-don't change.</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>fake MIC</Name>\r
+ <Default>00</Default>\r
+ <Desc>Number of times to fake MIC. 0xFF-don't change.</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="SC_command_operation == 2">\r
+ <Param type="u" size="1" valtype="BT_SECURE_CONNECTION_B0_CONFIGURATION_MASK">\r
+ <Name>b0 configuration</Name>\r
+ <Default>00</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="BT_SECURE_CONNECTION_B1_CONFIGURATION_MASK">\r
+ <Name>b1 configuration</Name>\r
+ <Default>00</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Payload Counter Enable</Name>\r
+ <Default>00</Default>\r
+ <Desc>enable payload counters</Desc>\r
+ </Param>\r
+ <Param type="x" size="5">\r
+ <Name>Payload Counter init value</Name>\r
+ <Default>"00000"</Default>\r
+ <Desc>Set init value of the payload counters</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="SC_command_operation == 3">\r
+ <Param type="u" size="1">\r
+ <Name>Start of packet offset</Name>\r
+ <Default>00</Default>\r
+ <Desc>Represent the offset from packet timer 0 in which AES mechanism will be triggered. The formula is: time of wakeup=PT0-Start of packet offset</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Slave tx slot offset</Name>\r
+ <Default>00</Default>\r
+ <Desc>Represent the offset from Tx slot of a slave in which Tx AES handling will be triggered. The formula is: time of wakeup=Tx slave slot-Slave tx slot offset</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>End of packet margin</Name>\r
+ <Default>00</Default>\r
+ <Desc>Margin from end of packet triggering.</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="SC_command_operation == 4">\r
+ <Param type="u" size="1">\r
+ <Name>Hybrid mode enable</Name>\r
+ <Default>00</Default>\r
+ <Desc>If enabled then SC pairing will be used for E0 encryption. 0xFF for don't change.</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+</Command>\r
+\r
+\r
+<Command name="HCI_VS_Config_Multiple_Slaves" type="vc" opcode="0xFDEC">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name> \r
+ <Default>0xFDEC</Default> \r
+ <Desc>This command Configures Bt Multiple Slaves (More than 2) operating mode.</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype='EnableDisable'>\r
+ <Name>Enable Inquiry Scan with max slaves</Name>\r
+ <Default>0</Default>\r
+ <Desc>Should the device be discoverable with max slaves in connection?</Desc>\r
+ </Param>\r
+ \r
+ <Param type="u" size="1">\r
+ <Name>Max slave count</Name>\r
+ <Default>2</Default>\r
+ <Desc>Define the maximum amount of concurrent slaves (2 - 4) </Desc>\r
+ </Param>\r
+ \r
+ \r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+</Command>\r
+\r
+\r
+<Command name="HCI_VS_Configure_MWS_Pins" type="vc" opcode="0xFE07">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name> \r
+ <Default>0xFE07</Default> \r
+ <Desc>This command configures MWS coex pins</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="MWS_Coex_Pin" label="MWS_Coex_Pin_Condition">\r
+ <Name>pin_select</Name>\r
+ <Default>0xFF</Default>\r
+ <Desc>select pin to configure</Desc>\r
+ </Param>\r
+ \r
+ <Param cond="MWS_Coex_Pin_Condition==0">\r
+ <Param type="u" size="1" valtype="MWS_Coex_RT_UART_TXD_pin_select">\r
+ <Name>pad_select</Name>\r
+ <Default>0xFF</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="MWS_Coex_Pin_Condition==1">\r
+ <Param type="u" size="1" valtype="MWS_Coex_RT_UART_RXD_pin_select">\r
+ <Name>pad_select</Name>\r
+ <Default>0xFF</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="MWS_Coex_Pin_Condition==2">\r
+ <Param type="u" size="1" valtype="MWS_Coex_Frame_Sync_input_pad">\r
+ <Name>pad_select</Name>\r
+ <Default>0xFF</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="MWS_Coex_Pin_Condition==3">\r
+ <Param type="u" size="1" valtype="MWS_TX_pin_select">\r
+ <Name>pad_select</Name>\r
+ <Default>0xFF</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="MWS_Coex_Pin_Condition==4">\r
+ <Param type="u" size="1" valtype="MWS_ACTIVE_pin_select">\r
+ <Name>pad_select</Name>\r
+ <Default>0xFF</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="MWS_Coex_Pin_Condition==5">\r
+ <Param type="u" size="1" valtype="MWS_SLEEP_pin_select">\r
+ <Name>pad_select</Name>\r
+ <Default>0xFF</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="MWS_Coex_Pin_Condition==6">\r
+ <Param type="u" size="1" valtype="BT_TX_pin_select">\r
+ <Name>pad_select</Name>\r
+ <Default>0xFF</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="MWS_Coex_Pin_Condition==7">\r
+ <Param type="u" size="1" valtype="BT_RX_PRIORITY_pin_select">\r
+ <Name>pad_select</Name>\r
+ <Default>0xFF</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="MWS_Coex_Pin_Condition==8">\r
+ <Param type="u" size="1" valtype="BT_SLEEP_pin_select">\r
+ <Name>pad_select</Name>\r
+ <Default>0xFF</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param cond="MWS_Coex_Pin_Condition==2">\r
+ <Param type="u" size="1" valtype="MWS_Coex_Frame_Sync_input_polarity" >\r
+ <Name>polarity</Name>\r
+ <Default>0xFF</Default>\r
+ <Desc> 1 - rising edge is refernce point, 0 - falling edge is refernce point</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param cond="MWS_Coex_Pin_Condition!=2">\r
+ <Param type="u" size="1" valtype="MWS_Coex_activity_polarity" >\r
+ <Name>polarity</Name>\r
+ <Default>0xFF</Default>\r
+ <Desc> 1 - rising edge is refernce point, 0 - falling edge is refernce point</Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+ <Param type="u" size="1" >\r
+ <Name>RTF select</Name>\r
+ <Default>0</Default>\r
+ <Desc>RTF (0-5)</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" >\r
+ <Name>RT MSG mask</Name>\r
+ <Default>0x0</Default>\r
+ <Desc>RT MSG mask - (SIG 3 bit opcode)</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" >\r
+ <Name>RT MSG value</Name>\r
+ <Default>0x0</Default>\r
+ <Desc>RT MSG value - (SIG 3 bit opcode)</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" >\r
+ <Name>RT MSG bit location</Name>\r
+ <Default>3</Default>\r
+ <Desc>bit location in RT MSG value</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="MWS_Coex_INT_routing_selector">\r
+ <Name>INT handler routing</Name>\r
+ <Default>2</Default>\r
+ <Desc>0 none, 1high priority, 2-low priority</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+</Command>\r
+\r
+\r
+<Command name="HCI_VS_Set_Local_Clock_Dragging_Params" type="vc" opcode="0xFDF2">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name> \r
+ <Default>0xFDF2</Default> \r
+ <Desc>This command controls manual shifting of local clock when master</Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>enable</Name>\r
+ <Default>0</Default>\r
+ <Desc>0x0 - no not shift clock, other - shift enables </Desc>\r
+ </Param>\r
+ <Param type="d" size="2">\r
+ <Name>step_size_in_uS</Name>\r
+ <Default>4</Default>\r
+ <Desc> INT16 steps size in uS </Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>PT_for_shift</Name>\r
+ <Default>50</Default>\r
+ <Desc> UINT16 value of PT for which to target the shift </Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+</Command>\r
+\r
+\r
+<Command name="HCI_VS_Set_MWS_Coex_Configuration" type="vc" opcode="0xFDF4">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name> \r
+ <Default>0xFDF4</Default> \r
+ <Desc>This command controls MWS coex configuration</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" valtype="MWS_Coex_enable_Bitmap">\r
+ <Name>enable_bitmask</Name>\r
+ <Default>0</Default>\r
+ <Desc>bit by bit enables\r
+ 0xFFFF means don't change\r
+ </Desc>\r
+ </Param>\r
+ <Param type="u" size="2" valtype="MWS_Coex_AFH_debug_enable_Bitmap">\r
+ <Name>afh_config_mask</Name>\r
+ <Default>0</Default>\r
+ <Desc> AFH enable mask \r
+ 0xFFFF means don't change\r
+ </Desc>\r
+ </Param>\r
+ \r
+ <Param type="d" size="1">\r
+ <Name>golden_range_high_rssi</Name>\r
+ <Default>-30</Default>\r
+ <Desc>golden range high rssi when MWS is on\r
+ -128 means don't change\r
+ </Desc>\r
+ </Param>\r
+ <Param type="d" size="1">\r
+ <Name>golden_range_low_rssi</Name>\r
+ <Default>-50</Default>\r
+ <Desc>golden range low rssi when MWS is on\r
+ -128 means don't change\r
+ </Desc>\r
+ </Param>\r
+ \r
+ <Param type="d" size="1">\r
+ <Name>mws_fdd_tx_noise_interferer_th</Name>\r
+ <Default>-95</Default>\r
+ <Desc> the min level MWS TX noise reaches ISM band that is considered an interferer\r
+ -128 means don't change\r
+ </Desc>\r
+ </Param>\r
+ \r
+ <Param type="d" size="1">\r
+ <Name>mws_tdd_tx_noise_interferer_th</Name>\r
+ <Default>-105</Default>\r
+ <Desc> the min level MWS TX noise reaches ISM band that is considered an interferer\r
+ -128 means don't change\r
+ </Desc>\r
+ </Param>\r
+ \r
+ <Param type="u" size="1">\r
+ <Name>afh_max_num_of_mws_removed_ch</Name>\r
+ <Default>20</Default>\r
+ <Desc> maximal channels AFH may remove due to MWS\r
+ 0xFF means don't change\r
+ </Desc>\r
+ </Param>\r
+ \r
+ <Param type="u" size="1">\r
+ <Name>afh_remove_N_channels_by_IM</Name>\r
+ <Default>0</Default>\r
+ <Desc> Remove N BT channels from each side of \r
+ the center_freq (include) due to Inter Modulation\r
+ (limited by afh_max_num_of_mws_removed_ch)</Desc>\r
+ </Param>\r
+ \r
+ <Param type="u" size="1">\r
+ <Name>max_power_allowed (dBm)</Name>\r
+ <Default>1 *2</Default>\r
+ <Desc> uses afh_remove_N_channels_by_IM parameter to apply max power on N TX channels\r
+ from each side of the center (included).\r
+ Insert max_power multiple in two.</Desc>\r
+ </Param>\r
+\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_Set_MWS_Channel_Params" type="sc" opcode="0x0C6E">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name> \r
+ <Default>0x0C6E</Default> \r
+ <Desc>This command notifies BT of MWS channel</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="MWS_Channel_Enable">\r
+ <Name>MWS Channel Enable</Name>\r
+ <Default>0</Default>\r
+ <Desc>Enable or disable the MWS channel</Desc>\r
+ </Param>\r
+ <Param type="d" size="2">\r
+ <Name>MWS RX Center Frequency</Name>\r
+ <Default>2510</Default>\r
+ <Desc>Indicate the center frequency of the MWS device\92s and downlink (RX) channels (in MHz)</Desc>\r
+ </Param>\r
+ <Param type="d" size="2">\r
+ <Name>MWS TX Center Frequency</Name>\r
+ <Default>2510</Default>\r
+ <Desc>Indicate the center frequency of the MWS device\92s and uplink (TX) channels (in MHz)</Desc>\r
+ </Param>\r
+ <Param type="u" size="2" >\r
+ <Name>MWS RX Channel Bandwidth</Name>\r
+ <Default>1400</Default>\r
+ <Desc>channel BW in KHz units </Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>MWS TX Channel Bandwidth</Name>\r
+ <Default>1400</Default>\r
+ <Desc>channel BW in KHz units </Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="MWS_Coex_channel_type">\r
+ <Name>MWS channel type</Name>\r
+ <Default>0</Default>\r
+ <Desc>LTE-WiMAX-TDD-FDD</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+</Command> \r
+\r
+<Command name="HCI_Set_External_Frame_Configuration" type="sc" opcode="0x0C6F">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name> \r
+ <Default>0x0C6F</Default> \r
+ <Desc>allows the Host to specify a frame configuration \r
+ for an external collocated system.</Desc>\r
+ </Param>\r
+ <Param type="u" size="2" >\r
+ <Name>EXT frame duration</Name>\r
+ <Default>10000</Default>\r
+ <Desc>External frame duration in microseconds</Desc>\r
+ </Param>\r
+ <Param type="d" size="2" >\r
+ <Name>EXT frame sync offset</Name>\r
+ <Default>0</Default>\r
+ <Desc>the time (in microseconds) from the start of the next MWS\r
+ frame to the FRAME_SYNC signal.</Desc>\r
+ </Param>\r
+ <Param type="u" size="2" >\r
+ <Name>EXT frame sync jitter</Name>\r
+ <Default>0</Default>\r
+ <Desc></Desc>\r
+ </Param>\r
+ <Param type="u" size="1" label="ext_num_periods">\r
+ <Name>EXT num periods</Name>\r
+ <Default>0x01</Default>\r
+ <Desc>The sum of all uplink,downlink and guardband periods in a frame</Desc>\r
+ </Param>\r
+ <Param array="ext_num_periods">\r
+ <Param type="u" size="2">\r
+ <Name>Period Duration</Name>\r
+ <Default>0</Default>\r
+ <Desc>The duration o each period</Desc>\r
+ </Param>\r
+ </Param> \r
+ <Param array="ext_num_periods">\r
+ <Param type="u" size="1" valtype="period_type">\r
+ <Name>Period Type</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>Indicates if the specified period is:\r
+ Uplink, Downlink, Bi-Directional or Guard period</Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+</Command> \r
+\r
+\r
+<Command name="Set_MWS_Transport_Layer" type="sc" opcode="0x0C71">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name> \r
+ <Default>0x0C71</Default> \r
+ <Desc>This command configures the realtime UART for MWS coex</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="MWS_Coex_RT_UART_mode">\r
+ <Name>Trabnsport_Layer </Name>\r
+ <Default>2</Default>\r
+ <Desc>Mode selector: 0-off, 1-one wire, 2-two wire</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" >\r
+ <Name>To_MWS_Baud_Rate</Name>\r
+ <Default>115200</Default>\r
+ <Desc>in mode 1 - RX rate, in mode 2 - both RX and TX rate</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" >\r
+ <Name>From_MWS_Baud_Rate</Name>\r
+ <Default>115200</Default>\r
+ <Desc>in mode 1 - TX rate, in mode 2 - unused</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+</Command>\r
+\r
+\r
+<Command name="HCI_Get_MWS_Transport_Layer_Configuration" type="sc" opcode="0x0C0C">\r
+ <Cat>Spec 4.1</Cat>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="Status">\r
+ <Name>Status</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>Status</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" label="num_supported_transports">\r
+ <Name>Number Of Supported Transports</Name>\r
+ <Default>0x01</Default>\r
+ <Desc>Number Of Supported Transports by controller</Desc>\r
+ </Param>\r
+ <Param array="num_supported_transports">\r
+ <Param type="u" size="1" valtype="MWS_Coex_RT_UART_mode">\r
+ <Name>Transport Layer</Name>\r
+ <Default>0x2</Default>\r
+ <Desc />\r
+ </Param>\r
+ </Param>\r
+ <Param array="num_supported_transports">\r
+ <Param type="u" size="1" label="num_baud_rates">\r
+ <Name>Number of Baud rates for each Transport</Name>\r
+ <Default>0x6</Default>\r
+ <Desc />\r
+ </Param>\r
+ </Param>\r
+ <Param array="6">\r
+ <Param type="u" size="4" >\r
+ <Name>Baud rates supported (controller->host)</Name>\r
+ <Default />\r
+ <Desc>Number of Baud rates for each Transport </Desc>\r
+ </Param>\r
+ </Param>\r
+ <Param array="6">\r
+ <Param type="u" size="4" >\r
+ <Name>Baud rates supported (host->controller)</Name>\r
+ <Default />\r
+ <Desc>Number of Baud rates for each Transport </Desc>\r
+ </Param>\r
+ </Param>\r
+ \r
+</Command>\r
+\r
+<Command name="HCI_VS_Set_MWS_TX_Mask_Params" type="vc" opcode="0xFDF5">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name> \r
+ <Default>0xFDF5</Default> \r
+ <Desc>This command notifies BT of MWS TX mask shape</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>MWS_emission_mask_0Mhz</Name>\r
+ <Default>0</Default>\r
+ <Desc>MWS emission at 0Mhz from MWS signal edge</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>MWS_emission_mask_8Mhz</Name>\r
+ <Default>0</Default>\r
+ <Desc>MWS emission at 8Mhz from MWS signal edge</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>MWS_emission_mask_16Mhz</Name>\r
+ <Default>0</Default>\r
+ <Desc>MWS emission at 16Mhz from MWS signal edge</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>MWS_emission_mask_24Mhz</Name>\r
+ <Default>0</Default>\r
+ <Desc>MWS emission at 24Mhz from MWS signal edge</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>MWS_emission_mask_32Mhz</Name>\r
+ <Default>0</Default>\r
+ <Desc>MWS emission at 32Mhz from MWS signal edge</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>MWS_emission_mask_40Mhz</Name>\r
+ <Default>0</Default>\r
+ <Desc>MWS emission at 40Mhz from MWS signal edge</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>MWS_emission_mask_48Mhz</Name>\r
+ <Default>0</Default>\r
+ <Desc>MWS emission at 48Mhz from MWS signal edge</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>MWS_emission_mask_56Mhz</Name>\r
+ <Default>0</Default>\r
+ <Desc>MWS emission at 56Mhz from MWS signal edge</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>MWS_emission_mask_64Mhz</Name>\r
+ <Default>0</Default>\r
+ <Desc>MWS emission at 64Mhz from MWS signal edge</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>MWS_emission_mask_72Mhz</Name>\r
+ <Default>0</Default>\r
+ <Desc>MWS emission at 72Mhz from MWS signal edge</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>MWS_emission_mask_80Mhz</Name>\r
+ <Default>0</Default>\r
+ <Desc>MWS emission at 80Mhz from MWS signal edge</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+</Command>\r
+\r
+\r
+<Command name="HCI_VS_Set_MWS_TX_Filter" type="vc" opcode="0xFDF6">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name> \r
+ <Default>0xFDF6</Default> \r
+ <Desc>This command notifies BT of MWS TX filter shape</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>MWS_TX_filter_at_2402Mhz</Name>\r
+ <Default>0</Default>\r
+ <Desc>MWS MWS TX filter at 2402Mhz</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>MWS_TX_filter_at_2410Mhz</Name>\r
+ <Default>0</Default>\r
+ <Desc>MWS MWS TX filter at 2410Mhz</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>MWS_TX_filter_at_2418Mhz</Name>\r
+ <Default>0</Default>\r
+ <Desc>MWS MWS TX filter at 2418Mhz</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>MWS_TX_filter_at_2426Mhz</Name>\r
+ <Default>0</Default>\r
+ <Desc>MWS MWS TX filter at 2426Mhz</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>MWS_TX_filter_at_2434Mhz</Name>\r
+ <Default>0</Default>\r
+ <Desc>MWS MWS TX filter at 2434Mhz</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>MWS_TX_filter_at_2442Mhz</Name>\r
+ <Default>0</Default>\r
+ <Desc>MWS MWS TX filter at 2442Mhz</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>MWS_TX_filter_at_2450Mhz</Name>\r
+ <Default>0</Default>\r
+ <Desc>MWS MWS TX filter at 2450Mhz</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>MWS_TX_filter_at_2458Mhz</Name>\r
+ <Default>0</Default>\r
+ <Desc>MWS MWS TX filter at 2458Mhz</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>MWS_TX_filter_at_2466Mhz</Name>\r
+ <Default>0</Default>\r
+ <Desc>MWS MWS TX filter at 2466Mhz</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>MWS_TX_filter_at_2474Mhz</Name>\r
+ <Default>0</Default>\r
+ <Desc>MWS MWS TX filter at 2474Mhz</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>MWS_TX_filter_at_2482Mhz</Name>\r
+ <Default>0</Default>\r
+ <Desc>MWS MWS TX filter at 2482Mhz</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+</Command>\r
+\r
+\r
+<Command name="HCI_VS_Set_MWS_ANT_Isolation" type="vc" opcode="0xFDED">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name> \r
+ <Default>0xFDED</Default> \r
+ <Desc>This command notifies BT of MWS ANT isolation</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" >\r
+ <Name>num_of_ANT</Name>\r
+ <Default>1</Default>\r
+ <Desc>Number of ANTENNAS</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>ANT_1_isolation</Name>\r
+ <Default>0</Default>\r
+ <Desc>Islolation between MWS and BT ANT 1</Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>ANT_2_isolation</Name>\r
+ <Default>0</Default>\r
+ <Desc>Islolation between MWS and BT ANT 2,\r
+ when ANT 2 is not used must be 127\r
+ </Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>ANT_3_isolation</Name>\r
+ <Default>0</Default>\r
+ <Desc>Islolation between MWS and BT ANT 3,\r
+ when ANT 3 is not used must be 127\r
+ </Desc>\r
+ </Param>\r
+ <Param type="d" size="1" >\r
+ <Name>ANT_4_isolation</Name>\r
+ <Default>0</Default>\r
+ <Desc>Islolation between MWS and BT ANT 4,\r
+ when ANT 4 is not used must be 127\r
+ </Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+</Command>\r
+\r
+\r
+<Command name="HCI_VS_Send_Message_On_MWS_Coex_Uart" type="vc" opcode="0xFE0B">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name> \r
+ <Default>0xFE0B</Default> \r
+ <Desc>This command sends a message on MWS coex realtime UART</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="MWS_UART_msg_types">\r
+ <Name>MWS_UART_msg_types</Name>\r
+ <Default>0</Default>\r
+ <Desc>message type: reflected to 3 bit OPCODE</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" >\r
+ <Name>data_value</Name>\r
+ <Default>0</Default>\r
+ <Desc>payload data</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" >\r
+ <Name>data_length</Name>\r
+ <Default>1</Default>\r
+ <Desc>number of octets(1-4)</Desc>\r
+ </Param>\r
+ <Param type="u" size="2" >\r
+ <Name>data_periodicity</Name>\r
+ <Default>0</Default>\r
+ <Desc>if value not 0, message will be repeated every data_periodicity frames</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+</Command>\r
+\r
+\r
+<Command name="HCI_VS_Read_byte_from_MWS_Coex_Uart" type="vc" opcode="0xFE0C">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFE0C</Default>\r
+ <Desc> </Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="Status">\r
+ <Name>Status</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>Status</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>data_value</Name>\r
+ <Default>any</Default>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>timestamp</Name>\r
+ <Default>any</Default>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>pending_data_length</Name>\r
+ <Default>any</Default>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_AFH_class_additional_params" type="sc" opcode="0xfda0">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xfda0</Default>\r
+ <Desc>HCI_VS__AFH_class_additional_params</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Accumulated_grade_removal_TH in sco</Name>\r
+ <Default>6</Default>\r
+ <Desc>if accumulated grade > TH channel is bad used in sco con</Desc>\r
+ </Param>\r
+ <Param type="u" size="2">\r
+ <Name>grades_value_ACL</Name>\r
+ <Default>0x5430</Default>\r
+ <Desc>PHY grades translation from C_I in ACL connection</Desc>\r
+ </Param> \r
+ <Param type="u" size="2">\r
+ <Name>grades_value_SCO</Name>\r
+ <Default>0x5430</Default>\r
+ <Desc>PHY grades translation from C_I in SCO connection</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>Grade_Vale_For_ETSI</Name>\r
+ <Default>1</Default>\r
+ <Desc>the grade value given too interferer above rssi_value_for_etsi (-65dBm), 0-disable RTSI requirement, 1- default grade \r
+ </Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>RSSI_VALUE-for_ETSI</Name>\r
+ <Default>65</Default>\r
+ <Desc>the minimum interferer level to garde as interference - ETSI requirements</Desc>\r
+ </Param>\r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Config_A2DP_Role_Recognition" type="vc" opcode="0xFDEF">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name> \r
+ <Default>0xFDEF</Default> \r
+ <Desc>Update the A2DP recognition on a connection handle and run Max Slot optimization acorrding requested parms\r
+ Note: The Max Slot optimization update will run only if we have at least 1 VOICE channel</Desc> \r
+ </Param>\r
+ <Param type="h" size="2">\r
+ <Name>Connection Handle</Name> \r
+ <Default>Handle</Default> \r
+ <Desc>HCI Connection Handle</Desc> \r
+ </Param> \r
+ <Param type="u" size="1" valtype="A2DP_RECOGNITION_ROLE">\r
+ <Name>A2DP Role</Name>\r
+ <Default>0xFF</Default>\r
+ <Desc>Configure the A2DP role detection according to the Connection Handle</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" valtype="RUN_MAX_SLOT_ADJUSTMENT">\r
+ <Name>Run Max Slot adjustment </Name> \r
+ <Default>0x01</Default> \r
+ <Desc>Run\Dont Run Max Slot adjustment after applying the A2DP detection acorrding to the connection handle.\r
+ Note: Will run only if we have at least 1 VOICE channel</Desc> \r
+ </Param>\r
+ \r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name> \r
+ <Default /> \r
+ <Desc />\r
+ </Param>\r
+ \r
+</Command>\r
+\r
+<Command name="HCI_VS_DUAL_ANTENNA_POWER_INDEX_LIMIT" type="vc" opcode="0xfe1d">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xfe1d</Default>\r
+ <Desc>HCI_VS_dual_antenna_power_index_limit</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>dual_antenna_gfsk_power_index</Name>\r
+ <Default>7</Default>\r
+ <Desc> maximum power index allowed in 2.4 dual antenna mode for GFSK modulation</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>dual_antenna_edr2_power_index</Name>\r
+ <Default>7</Default>\r
+ <Desc>maximum power index allowed in 2.4 dual antenna mode for EDR2 modulation</Desc>\r
+ </Param> \r
+ <Param type="u" size="1">\r
+ <Name>dual_antenna_edr3_power_index</Name>\r
+ <Default>7</Default>\r
+ <Desc>maximum power index allowed in 2.4 dual antenna mode for EDR3 modulation</Desc>\r
+ </Param>\r
+ <Param type="u" size="1">\r
+ <Name>dual_antenna_ble_ant_power_index</Name>\r
+ <Default>7</Default>\r
+ <Desc>maximum power index allowed in 2.4 dual antenna mode for ANT and BLE connections</Desc>\r
+ </Param>\r
+ \r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_AVPR_A3DP_ROLE" type="vc" opcode="0xFD98">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFD98</Default>\r
+ <Desc>HCI_VS_AVPR_A3DP_ROLE</Desc>\r
+ </Param>\r
+ <Param type="u" size="1" label="a3dp_role" valtype="avpr_a3dp_role">\r
+ <Name>A3DP Role </Name>\r
+ <Default>0x01</Default>\r
+ <Desc> </Desc>\r
+ </Param>\r
+ \r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_AVPR_MASKED_TRACES" type="vc" opcode="0xFDBB">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name>\r
+ <Default>0xFDBB</Default>\r
+ <Desc>Set the AVPR masked traces debug configuration</Desc>\r
+ </Param>\r
+ <Param type="u" size="4" valtype="avpr_masked_traces">\r
+ <Name>AVPR masked traces</Name>\r
+ <Default>0x00000000</Default>\r
+ <Desc>The bit mask enabling AVPR traces</Desc>\r
+ </Param>\r
+ \r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name>\r
+ <Default />\r
+ <Desc />\r
+ </Param>\r
+</Command>\r
+\r
+<Command name="HCI_VS_Config_Acl_Data_Check" type="vc" opcode="0xfdbd">\r
+ <Param type="o" size="2">\r
+ <Name>Opcode</Name> \r
+ <Default>0xfdbd</Default> \r
+ <Desc>Clear an ACL data check acorrding to the Handle provided</Desc> \r
+ </Param>\r
+ <Param type="h" size="2">\r
+ <Name>Connection Handle</Name> \r
+ <Default>Handle</Default> \r
+ <Desc>HCI Connection Handle</Desc> \r
+ </Param> \r
+ <Param type="u" size="1" valtype="CLEAR_ACL_DATA_CHECK">\r
+ <Name>Clear Data</Name>\r
+ <Default>0x00</Default>\r
+ <Desc>Clear the Rx\TX data acorrding to handle</Desc>\r
+ </Param> \r
+ <Param type="R">\r
+ <Name>HCI_Command_Complete_Event</Name> \r
+ <Default /> \r
+ <Desc />\r
+ </Param> \r
+ <Param type="u" size="1" valtype="Status">\r
+ <Name>Status</Name>\r
+ <Default>0</Default>\r
+ <Desc>0 - Success</Desc>\r
+ </Param>\r
+ <Param type="h" size="2">\r
+ <Name>Connection Handle</Name>\r
+ <Default>Handle</Default>\r
+ <Desc />\r
+ </Param> \r
+ <Param type="u" size="4">\r
+ <Name>Total TX Byte Count</Name>\r
+ <Default>0</Default>\r
+ <Desc>Total TX Byte Count since starting to send data</Desc> \r
+ </Param>\r
+ <Param type="u" size="4">\r
+ <Name>Total RX Byte Count</Name>\r
+ <Default>0</Default>\r
+ <Desc>Total TX Byte Count since starting to receive data</Desc> \r
+ </Param> \r
+</Command>\r
+\r
</HCILib>\r