author | Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com> | |
Tue, 18 Aug 2015 23:40:30 +0000 (00:40 +0100) | ||
committer | Alex Shi <alex.shi@linaro.org> | |
Mon, 18 Apr 2016 07:12:36 +0000 (15:12 +0800) | ||
commit | 336a8e3903b10018f57d1e5b93ee837e1dfa8af3 | |
tree | f3a95b1291d10e51bd2f1ebe3226baafa874a7b1 | tree | snapshot (tar.xz tar.gz zip) |
parent | f43316d579b88b19baf9c404b2fc03ecd94519bf | commit | diff |
iommu/arm-smmu: ThunderX mis-extends 64bit registers
The SMMU architecture defines two different behaviors when 64-bit
registers are written with 32-bit writes. The first behavior causes
zero extension into the upper 32-bits. The second behavior splits a
64-bit register into "normal" 32-bit register pairs.
On some buggy implementations, registers incorrectly zero extended
when they should instead behave as normal 32-bit register pairs.
Signed-off-by: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com>
[will: removed redundant macro parameters]
Signed-off-by: Will Deacon <will.deacon@arm.com>
(cherry picked from commit 668b4ada1cdf406dac9f72503fa2f69f31bed0c5)
Signed-off-by: Alex Shi <alex.shi@linaro.org>
The SMMU architecture defines two different behaviors when 64-bit
registers are written with 32-bit writes. The first behavior causes
zero extension into the upper 32-bits. The second behavior splits a
64-bit register into "normal" 32-bit register pairs.
On some buggy implementations, registers incorrectly zero extended
when they should instead behave as normal 32-bit register pairs.
Signed-off-by: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com>
[will: removed redundant macro parameters]
Signed-off-by: Will Deacon <will.deacon@arm.com>
(cherry picked from commit 668b4ada1cdf406dac9f72503fa2f69f31bed0c5)
Signed-off-by: Alex Shi <alex.shi@linaro.org>
drivers/iommu/arm-smmu.c | diff | blob | history |