4 years agoMerge branch 'ti-linux-4.19.y-for-next' of git://git.ti.com/linux-phy/kishons-ti... ti-linux-4.19.y-next-20190605
Merge branch 'ti-linux-4.19.y-for-next' of git://git.ti.com/linux-phy/kishons-ti-linux-kernel into ti-linux-4.19.y-next
TI-Feature: kishon_next
TI-Tree: git://git.ti.com/linux-phy/kishons-ti-linux-kernel.git
TI-Branch: ti-linux-4.19.y-for-next
* 'ti-linux-4.19.y-for-next' of git://git.ti.com/linux-phy/kishons-ti-linux-kernel:
ARM: dts: k2e-evm: enable PCIe on port 1
ARM: dts: keystone-k2e: Use the updated binding to describe PCIe in k2e
ARM: keystone: dts: add PCI serdes driver bindings
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: kishon_next
TI-Tree: git://git.ti.com/linux-phy/kishons-ti-linux-kernel.git
TI-Branch: ti-linux-4.19.y-for-next
* 'ti-linux-4.19.y-for-next' of git://git.ti.com/linux-phy/kishons-ti-linux-kernel:
ARM: dts: k2e-evm: enable PCIe on port 1
ARM: dts: keystone-k2e: Use the updated binding to describe PCIe in k2e
ARM: keystone: dts: add PCI serdes driver bindings
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
Merge branch 'rpmsg-ti-linux-4.19.y-next' of git://git.ti.com/rpmsg/rpmsg into ti-linux-4.19.y-next
TI-Feature: rpmsg_next
TI-Tree: git://git.ti.com/rpmsg/rpmsg.git
TI-Branch: rpmsg-ti-linux-4.19.y-next
* 'rpmsg-ti-linux-4.19.y-next' of git://git.ti.com/rpmsg/rpmsg:
remoteproc: Add a sysfs interface for name
soc: ti: pruss: update pruss_get() to retrieve a PRUSS id
soc: ti: pruss: store the pruss instance id
TST: arm64: dts: ti: k3-j721e-common-proc-board: Add a mailbox test node
TST: arm64: dts: ti: k3-j721e-main: Add mailbox loopback devices for testing
TST: arm64: dts: ti: k3-am654-base-board: Add a mailbox test node
TST: arm64: dts: ti: k3-am65-main: Add a mailbox loopback device for testing
TEST: mailbox/omap: add a stand-alone test module for loopback devices
arm64: dts: ti: k3-j721e-main: Add IPC sub-mailbox nodes for all R5Fs & DSPs
arm64: dts: ti: k3-j721e-main: Add mailbox cluster nodes
dt-bindings: mailbox: omap: Update binding for J721E SoCs
TST: arm64: dts: ti: k3-j721e-common-proc-board: Add a hwspinlock test node
TST: arm64: dts: ti: k3-am654-base-board: Add a hwspinlock test node
TEST: hwspinlock/omap: Add a stand-alone unit-test module
arm64: dts: ti: k3-j721e-main: Add hwspinlock node
dt-bindings: hwlock: Update OMAP HwSpinlock binding for J721E SoCs
mailbox/omap: Simplify mbox_msg_t usage
net: ethernet: ti: prueth: Stop building prueth on K3 platforms
arm64: dts: ti: k3-am65-main: Move mailbox nodes to main_navss interconnect
arm64: dts: ti: k3-am65-main: Move hwspinlock node to main_navss interconnect
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: rpmsg_next
TI-Tree: git://git.ti.com/rpmsg/rpmsg.git
TI-Branch: rpmsg-ti-linux-4.19.y-next
* 'rpmsg-ti-linux-4.19.y-next' of git://git.ti.com/rpmsg/rpmsg:
remoteproc: Add a sysfs interface for name
soc: ti: pruss: update pruss_get() to retrieve a PRUSS id
soc: ti: pruss: store the pruss instance id
TST: arm64: dts: ti: k3-j721e-common-proc-board: Add a mailbox test node
TST: arm64: dts: ti: k3-j721e-main: Add mailbox loopback devices for testing
TST: arm64: dts: ti: k3-am654-base-board: Add a mailbox test node
TST: arm64: dts: ti: k3-am65-main: Add a mailbox loopback device for testing
TEST: mailbox/omap: add a stand-alone test module for loopback devices
arm64: dts: ti: k3-j721e-main: Add IPC sub-mailbox nodes for all R5Fs & DSPs
arm64: dts: ti: k3-j721e-main: Add mailbox cluster nodes
dt-bindings: mailbox: omap: Update binding for J721E SoCs
TST: arm64: dts: ti: k3-j721e-common-proc-board: Add a hwspinlock test node
TST: arm64: dts: ti: k3-am654-base-board: Add a hwspinlock test node
TEST: hwspinlock/omap: Add a stand-alone unit-test module
arm64: dts: ti: k3-j721e-main: Add hwspinlock node
dt-bindings: hwlock: Update OMAP HwSpinlock binding for J721E SoCs
mailbox/omap: Simplify mbox_msg_t usage
net: ethernet: ti: prueth: Stop building prueth on K3 platforms
arm64: dts: ti: k3-am65-main: Move mailbox nodes to main_navss interconnect
arm64: dts: ti: k3-am65-main: Move hwspinlock node to main_navss interconnect
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
Merge branch 'connectivity-next' of git://git.ti.com/~nsekhar/ti-linux-kernel/nsekhar-ti-linux-kernel into ti-linux-4.19.y-next
TI-Feature: connectivity_next
TI-Tree: git://git.ti.com/~nsekhar/ti-linux-kernel/nsekhar-ti-linux-kernel.git
TI-Branch: connectivity-next
* 'connectivity-next' of git://git.ti.com/~nsekhar/ti-linux-kernel/nsekhar-ti-linux-kernel: (23 commits)
mmc: sdhci_am654: Fix DLL trim and driver strength configuration
mmc: sdhci_am654: Fix SLOTTYPE write
mmc: sdhci_am654: Print error message if the DLL fails to lock
mmc: sdhci_am654: Improve line wrapping with regmap_*() calls
ti_config_fragments: connectivity.cfg: Enable Cadence USB3 drivers
usb: cdns3: Implement Idle state for Type-C
usb: cdns3: make dynamic role switching work
usb: cdns3: use phy power on/off
usb: cdns3: Add TI specific wrapper driver
dt-bindings: usb: Add binding for the TI wrapper for Cadence USB3 controller
usb: cdns3: drd: print error on xhci/dev ready timeout
usb: cdns3: drd: don't call drd_update_mode in drd_init()
usb: cdns3: support separate IRQs for otg/xhci/dev
usb:cdns3 Fix for stuck packets in on-chip OUT buffer.
usb:cdns3 Add Cadence USB3 DRD Driver
usb:common Simplify usb_decode_get_set_descriptor function.
usb:common Patch simplify usb_decode_set_clear_feature function.
usb:common Separated decoding functions from dwc3 driver.
dt-bindings: add binding for USBSS-DRD controller.
usb: dwc3: debug: purge usage of strcat
...
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: connectivity_next
TI-Tree: git://git.ti.com/~nsekhar/ti-linux-kernel/nsekhar-ti-linux-kernel.git
TI-Branch: connectivity-next
* 'connectivity-next' of git://git.ti.com/~nsekhar/ti-linux-kernel/nsekhar-ti-linux-kernel: (23 commits)
mmc: sdhci_am654: Fix DLL trim and driver strength configuration
mmc: sdhci_am654: Fix SLOTTYPE write
mmc: sdhci_am654: Print error message if the DLL fails to lock
mmc: sdhci_am654: Improve line wrapping with regmap_*() calls
ti_config_fragments: connectivity.cfg: Enable Cadence USB3 drivers
usb: cdns3: Implement Idle state for Type-C
usb: cdns3: make dynamic role switching work
usb: cdns3: use phy power on/off
usb: cdns3: Add TI specific wrapper driver
dt-bindings: usb: Add binding for the TI wrapper for Cadence USB3 controller
usb: cdns3: drd: print error on xhci/dev ready timeout
usb: cdns3: drd: don't call drd_update_mode in drd_init()
usb: cdns3: support separate IRQs for otg/xhci/dev
usb:cdns3 Fix for stuck packets in on-chip OUT buffer.
usb:cdns3 Add Cadence USB3 DRD Driver
usb:common Simplify usb_decode_get_set_descriptor function.
usb:common Patch simplify usb_decode_set_clear_feature function.
usb:common Separated decoding functions from dwc3 driver.
dt-bindings: add binding for USBSS-DRD controller.
usb: dwc3: debug: purge usage of strcat
...
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
Merge branch 'platform-ti-linux-4.19.y-next' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree into ti-linux-4.19.y-next
TI-Feature: platform_next
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y-next
* 'platform-ti-linux-4.19.y-next' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree:
dmaengine: ti: k3-udma: Make slave TR mode operational with PDMAs
dmaengine: ti: k3-udma: Fix kernel crash when _prep* callback fails
dmaengine: ti: k3-udma: new workaround for packet mode rx
dmaengine: ti: k3-udma: Use define for the default ring size
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: platform_next
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y-next
* 'platform-ti-linux-4.19.y-next' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree:
dmaengine: ti: k3-udma: Make slave TR mode operational with PDMAs
dmaengine: ti: k3-udma: Fix kernel crash when _prep* callback fails
dmaengine: ti: k3-udma: new workaround for packet mode rx
dmaengine: ti: k3-udma: Use define for the default ring size
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
remoteproc: Add a sysfs interface for name
This patch adds a sysfs interface that provides the name of the
remote processor to userspace. This allows the userspace to identify
a remote processor as the remoteproc devices themselves are created
based on probe order and can change from one boot to another or
at runtime.
The name is made available in debugfs originally, and is being
retained for now. This can be cleaned up after couple of releases
once users get familiar with the new interface.
Signed-off-by: Suman Anna <s-anna@ti.com>
This patch adds a sysfs interface that provides the name of the
remote processor to userspace. This allows the userspace to identify
a remote processor as the remoteproc devices themselves are created
based on probe order and can change from one boot to another or
at runtime.
The name is made available in debugfs originally, and is being
retained for now. This can be cleaned up after couple of releases
once users get familiar with the new interface.
Signed-off-by: Suman Anna <s-anna@ti.com>
soc: ti: pruss: update pruss_get() to retrieve a PRUSS id
Update the pruss_get() function to take in an additional integer
pointer argument in which the PRUSS instance id is filled in and
provided back to the callers. This allows the drivers to add some
instance-specific logic/customization in their code, as the PRUSS
handle is not useful to build this logic.
The already existing usage within both the regular PRU Ethernet
and the ICSSG PRU Ethernet drivers have also been updated accordingly,
and this will cater to its need for supporting switching between
different Ethernet protocols dynamically per instance.
Signed-off-by: Suman Anna <s-anna@ti.com>
Update the pruss_get() function to take in an additional integer
pointer argument in which the PRUSS instance id is filled in and
provided back to the callers. This allows the drivers to add some
instance-specific logic/customization in their code, as the PRUSS
handle is not useful to build this logic.
The already existing usage within both the regular PRU Ethernet
and the ICSSG PRU Ethernet drivers have also been updated accordingly,
and this will cater to its need for supporting switching between
different Ethernet protocols dynamically per instance.
Signed-off-by: Suman Anna <s-anna@ti.com>
soc: ti: pruss: store the pruss instance id
Add logic to the PRUSS platform driver to store the instance id
of a PRUSS instance. This is being added to enable support for
the PRU Ethernet driver to be able to switch between different
Ethernet protocols dynamically per instance.
The values for instance ids are not always zero-indexed on all
SoCs, they were chosen to match the numbering used in the TRMs.
The instance ids are computed assigned using the PRUSS memory
region base address lookup table. The base address matching
logic is not robust for long-term for newer SoCs, but is okay
for currently supported SoCs as all the addresses are unique.
This is done this way to retain the current usage of minimal
static data and to avoid having to introduce the instance
specific static data just for the instance id data.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add logic to the PRUSS platform driver to store the instance id
of a PRUSS instance. This is being added to enable support for
the PRU Ethernet driver to be able to switch between different
Ethernet protocols dynamically per instance.
The values for instance ids are not always zero-indexed on all
SoCs, they were chosen to match the numbering used in the TRMs.
The instance ids are computed assigned using the PRUSS memory
region base address lookup table. The base address matching
logic is not robust for long-term for newer SoCs, but is okay
for currently supported SoCs as all the addresses are unique.
This is done this way to retain the current usage of minimal
static data and to avoid having to introduce the instance
specific static data just for the instance id data.
Signed-off-by: Suman Anna <s-anna@ti.com>
TST: arm64: dts: ti: k3-j721e-common-proc-board: Add a mailbox test node
Add mbox_test node to the K3 J721E common processor board upon which the
mailbox can be tested. The node can be used to test any of the loopback
sub-mailbox nodes on each of the enabled Mailbox Clusters 0 through 4,
one at a time.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add mbox_test node to the K3 J721E common processor board upon which the
mailbox can be tested. The node can be used to test any of the loopback
sub-mailbox nodes on each of the enabled Mailbox Clusters 0 through 4,
one at a time.
Signed-off-by: Suman Anna <s-anna@ti.com>
TST: arm64: dts: ti: k3-j721e-main: Add mailbox loopback devices for testing
Add some loopback sub-mailbox devices within each of the Mailbox Clusters
0 through 4 on the J721E SoCs for testing. The loopback device uses the
same mailbox fifo for sending and receiving messages on the MPU itself,
facilitating a unit-test. The last FIFO within each cluster is chosen for
the loopback to not conflict with the actual FIFOs at the beginning that
will be used to communicate with the remote processors.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add some loopback sub-mailbox devices within each of the Mailbox Clusters
0 through 4 on the J721E SoCs for testing. The loopback device uses the
same mailbox fifo for sending and receiving messages on the MPU itself,
facilitating a unit-test. The last FIFO within each cluster is chosen for
the loopback to not conflict with the actual FIFOs at the beginning that
will be used to communicate with the remote processors.
Signed-off-by: Suman Anna <s-anna@ti.com>
TST: arm64: dts: ti: k3-am654-base-board: Add a mailbox test node
Add a mbox_test node to the AM654 base board which allows the
mailbox to be tested on any of the derivative boards. The node
can be used to test any of the loopback sub-mailbox nodes on each
of the enabled Mailbox Clusters 0 or 1, one at a time.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add a mbox_test node to the AM654 base board which allows the
mailbox to be tested on any of the derivative boards. The node
can be used to test any of the loopback sub-mailbox nodes on each
of the enabled Mailbox Clusters 0 or 1, one at a time.
Signed-off-by: Suman Anna <s-anna@ti.com>
TST: arm64: dts: ti: k3-am65-main: Add a mailbox loopback device for testing
Add a loopback sub-mailbox device within Mailbox clusters 1 and 2 on the
AM65x SoCs for testing. The loopback device uses the same mailbox fifo
for sending and receiving messages on the MPU itself, facilitating a
unit-test. The last FIFO within the IP is chosen for the loopback to
not conflict with the actual FIFOs at the beginning that will be used
to communicate with the remote processors.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add a loopback sub-mailbox device within Mailbox clusters 1 and 2 on the
AM65x SoCs for testing. The loopback device uses the same mailbox fifo
for sending and receiving messages on the MPU itself, facilitating a
unit-test. The last FIFO within the IP is chosen for the loopback to
not conflict with the actual FIFOs at the beginning that will be used
to communicate with the remote processors.
Signed-off-by: Suman Anna <s-anna@ti.com>
TEST: mailbox/omap: add a stand-alone test module for loopback devices
Add a preliminary unit-test module for the OMAP Mailbox driver. The test
uses the API provided by the Mailbox framework and performs a loop-back
test (send and receive on the same OMAP Mailbox FIFO on the Linux host
processor). The test module requires specific sub-mailbox loop-back child
device(s) to be added to the desired OMAP Mailbox nodes, and a test node
referencing the added sub-mailbox nodes.
Two module parameters, 'count' (default = 16) and 'mbox_id' (default = 0),
are provided to dictate the number of messages to be exchanged and the
index of the sub-mailbox device in the test node's mboxes property. The
test status and number of messages received are printed upon the module's
removal.
NOTE:
The module needs to be installed and uninstalled with specific mbox_id
parameter to test the corresponding loopback sub-device if the test node
has multiple sub-devices to test.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add a preliminary unit-test module for the OMAP Mailbox driver. The test
uses the API provided by the Mailbox framework and performs a loop-back
test (send and receive on the same OMAP Mailbox FIFO on the Linux host
processor). The test module requires specific sub-mailbox loop-back child
device(s) to be added to the desired OMAP Mailbox nodes, and a test node
referencing the added sub-mailbox nodes.
Two module parameters, 'count' (default = 16) and 'mbox_id' (default = 0),
are provided to dictate the number of messages to be exchanged and the
index of the sub-mailbox device in the test node's mboxes property. The
test status and number of messages received are printed upon the module's
removal.
NOTE:
The module needs to be installed and uninstalled with specific mbox_id
parameter to test the corresponding loopback sub-device if the test node
has multiple sub-devices to test.
Signed-off-by: Suman Anna <s-anna@ti.com>
arm64: dts: ti: k3-j721e-main: Add IPC sub-mailbox nodes for all R5Fs & DSPs
Add the sub-mailbox nodes that are used to communicate between MPU and
various remote processors present in the J721E SoCs. These include the
R5F remote processors in the dual-R5F cluster (MCU_R5FSS0) in the MCU
domain and the two dual-R5F clusters (MAIN_R5FSS0 & MAIN_R5FSS1) in the
MAIN domain; the two C66x DSP remote processors and the single C71x DSP
remote processor in the MAIN domain. The parent mailbox cluster nodes
are also enabled.
The sub-mailbox nodes utilize the System Mailbox clusters 0 through 4.
These sub-mailbox nodes are added to match the hard-coded mailbox
configuration used within the TI RTOS IPC software packages. The R5F
processor sub-systems are assumed to be running in Split mode, so a
sub-mailbox node is used by each of the R5F cores. The sub-mailbox node
for the first R5F core in each cluster is used in case of Lockstep mode.
NOTE:
The GIC_SPI interrupts to be used are dynamically allocated and managed
by the System Firmware through the ti-sci-irqchip driver. So, only valid
interrupts (each cluster's User 0 IRQ output) that are used by the
sub-mailbox devices are enabled. This is done to minimize the number
of NavSS Interrupt Router outputs utilized.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add the sub-mailbox nodes that are used to communicate between MPU and
various remote processors present in the J721E SoCs. These include the
R5F remote processors in the dual-R5F cluster (MCU_R5FSS0) in the MCU
domain and the two dual-R5F clusters (MAIN_R5FSS0 & MAIN_R5FSS1) in the
MAIN domain; the two C66x DSP remote processors and the single C71x DSP
remote processor in the MAIN domain. The parent mailbox cluster nodes
are also enabled.
The sub-mailbox nodes utilize the System Mailbox clusters 0 through 4.
These sub-mailbox nodes are added to match the hard-coded mailbox
configuration used within the TI RTOS IPC software packages. The R5F
processor sub-systems are assumed to be running in Split mode, so a
sub-mailbox node is used by each of the R5F cores. The sub-mailbox node
for the first R5F core in each cluster is used in case of Lockstep mode.
NOTE:
The GIC_SPI interrupts to be used are dynamically allocated and managed
by the System Firmware through the ti-sci-irqchip driver. So, only valid
interrupts (each cluster's User 0 IRQ output) that are used by the
sub-mailbox devices are enabled. This is done to minimize the number
of NavSS Interrupt Router outputs utilized.
Signed-off-by: Suman Anna <s-anna@ti.com>
arm64: dts: ti: k3-j721e-main: Add mailbox cluster nodes
The J721E Main NavSS block contains a Mailbox IP instance with
multiple clusters. Each cluster is equivalent to an Mailbox IP
instance on OMAP platforms.
Add all the Mailbox clusters as their own nodes under the MAIN
NavSS cbass_main_navss interconnect node instead of creating an
almost empty parent node for the new K3 mailbox IP and the clusters
as its child nodes. All these nodes are marked as disabled, and
they need to be enabled along with the appropriate child nodes
on a need basis.
NOTE:
The NavSS only has a limited number of interrupts, so all the
interrupts generated by a Mailbox IP are not added by default.
Only the needed interrupts that are targeted towards the A72
GIC will need to be be added later on when some sub-mailbox
child nodes are added.
Signed-off-by: Suman Anna <s-anna@ti.com>
The J721E Main NavSS block contains a Mailbox IP instance with
multiple clusters. Each cluster is equivalent to an Mailbox IP
instance on OMAP platforms.
Add all the Mailbox clusters as their own nodes under the MAIN
NavSS cbass_main_navss interconnect node instead of creating an
almost empty parent node for the new K3 mailbox IP and the clusters
as its child nodes. All these nodes are marked as disabled, and
they need to be enabled along with the appropriate child nodes
on a need basis.
NOTE:
The NavSS only has a limited number of interrupts, so all the
interrupts generated by a Mailbox IP are not added by default.
Only the needed interrupts that are targeted towards the A72
GIC will need to be be added later on when some sub-mailbox
child nodes are added.
Signed-off-by: Suman Anna <s-anna@ti.com>
dt-bindings: mailbox: omap: Update binding for J721E SoCs
Update the existing OMAP Mailbox binding to include the info
for J721E SoCs. The same compatible from AM65x SoCs is reused
for J721E SoCs as well.
The overall binding has also been updated to add additional
details, fix up various typos and update the AM65x example
to reflect the latest usage.
Signed-off-by: Suman Anna <s-anna@ti.com>
Update the existing OMAP Mailbox binding to include the info
for J721E SoCs. The same compatible from AM65x SoCs is reused
for J721E SoCs as well.
The overall binding has also been updated to add additional
details, fix up various typos and update the AM65x example
to reflect the latest usage.
Signed-off-by: Suman Anna <s-anna@ti.com>
TST: arm64: dts: ti: k3-j721e-common-proc-board: Add a hwspinlock test node
Add hwspin_test node to the K3 J721E common processor board upon which the
hwspinlock DT client usage can be tested.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add hwspin_test node to the K3 J721E common processor board upon which the
hwspinlock DT client usage can be tested.
Signed-off-by: Suman Anna <s-anna@ti.com>
TST: arm64: dts: ti: k3-am654-base-board: Add a hwspinlock test node
Add hwspin_test node to the K3 AM654 base board upon which the
hwspinlock DT client usage can be tested.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add hwspin_test node to the K3 AM654 base board upon which the
hwspinlock DT client usage can be tested.
Signed-off-by: Suman Anna <s-anna@ti.com>
TEST: hwspinlock/omap: Add a stand-alone unit-test module
Add an unit-test module to test all the possible hwspinlocks supported
on a bank using the regular hwspinlock request API. The module also
tests DT client usage optionally (based on presence of a test-node)
using the appropriate OF request API of_hwspin_get_lock_id() request
API.
The test module is re-implemented as a regular module instead of a
platform driver so that it can be run even without the presence of any
test nodes. The module uses some SoC data for figuring out the maximum
number of locks on a SoC.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add an unit-test module to test all the possible hwspinlocks supported
on a bank using the regular hwspinlock request API. The module also
tests DT client usage optionally (based on presence of a test-node)
using the appropriate OF request API of_hwspin_get_lock_id() request
API.
The test module is re-implemented as a regular module instead of a
platform driver so that it can be run even without the presence of any
test nodes. The module uses some SoC data for figuring out the maximum
number of locks on a SoC.
Signed-off-by: Suman Anna <s-anna@ti.com>
arm64: dts: ti: k3-j721e-main: Add hwspinlock node
The Main NavSS block on J721E SoCs contains a HwSpinlock IP instance that
is same as the IP on AM65x SoCs and similar to the IP on some OMAP SoCs.
Add the DT node for this on J721E SoCs. The node is present within the
Main NavSS block, and is added as a child node under the cbass_main_navss
interconnect node.
Signed-off-by: Suman Anna <s-anna@ti.com>
The Main NavSS block on J721E SoCs contains a HwSpinlock IP instance that
is same as the IP on AM65x SoCs and similar to the IP on some OMAP SoCs.
Add the DT node for this on J721E SoCs. The node is present within the
Main NavSS block, and is added as a child node under the cbass_main_navss
interconnect node.
Signed-off-by: Suman Anna <s-anna@ti.com>
dt-bindings: hwlock: Update OMAP HwSpinlock binding for J721E SoCs
Update the existing OMAP HwSpinlock binding to also include the
info for J721E SoCs. The same compatible from AM65x SoCs is
reused for J721E SoCs as well. The AM65x example is also updated
to reflect the new interconnect location.
Signed-off-by: Suman Anna <s-anna@ti.com>
Update the existing OMAP HwSpinlock binding to also include the
info for J721E SoCs. The same compatible from AM65x SoCs is
reused for J721E SoCs as well. The AM65x example is also updated
to reflect the new interconnect location.
Signed-off-by: Suman Anna <s-anna@ti.com>
Merge branch 'mailbox-linux-4.19.y' into rpmsg-ti-linux-4.19.y-next
* mailbox-linux-4.19.y:
mailbox/omap: Simplify mbox_msg_t usage
Signed-off-by: Suman Anna <s-anna@ti.com>
* mailbox-linux-4.19.y:
mailbox/omap: Simplify mbox_msg_t usage
Signed-off-by: Suman Anna <s-anna@ti.com>
mailbox/omap: Simplify mbox_msg_t usage
Simplify the mbox_msg_t type definition and the to_omap_mbox_msg
macro to use the uintptr_t type that can scale better to both
32-bit and 64-bit platforms.
Signed-off-by: Suman Anna <s-anna@ti.com>
Simplify the mbox_msg_t type definition and the to_omap_mbox_msg
macro to use the uintptr_t type that can scale better to both
32-bit and 64-bit platforms.
Signed-off-by: Suman Anna <s-anna@ti.com>
Merge branch 'mailbox-linux-4.19.y' of git://git.ti.com/rpmsg/mailbox into rpmsg-ti-linux-4.19.y-next
* 'mailbox-linux-4.19.y' of git://git.ti.com/rpmsg/mailbox:
arm64: dts: ti: k3-am65-main: Move mailbox nodes to main_navss interconnect
Signed-off-by: Suman Anna <s-anna@ti.com>
* 'mailbox-linux-4.19.y' of git://git.ti.com/rpmsg/mailbox:
arm64: dts: ti: k3-am65-main: Move mailbox nodes to main_navss interconnect
Signed-off-by: Suman Anna <s-anna@ti.com>
Merge branch 'rpmsg-ti-linux-4.19.y' into rpmsg-ti-linux-4.19.y-next
* rpmsg-ti-linux-4.19.y:
arm64: dts: ti: k3-am65-main: Move hwspinlock node to main_navss interconnect
Signed-off-by: Suman Anna <s-anna@ti.com>
* rpmsg-ti-linux-4.19.y:
arm64: dts: ti: k3-am65-main: Move hwspinlock node to main_navss interconnect
Signed-off-by: Suman Anna <s-anna@ti.com>
net: ethernet: ti: prueth: Stop building prueth on K3 platforms
The PRU Ethernet driver is only applicable for SoCs containing a
PRUSS subsystem, and there is a separate equivalent driver for
SoCs containing the next generation ICSSG subsystem. The driver
currently depends on PRU_REMOTEPROC which is also enabled for TI
K3 family of SoCs, and therefore is getting built for TI K3 platforms
as well. Add an additional Kconfig dependency so that the driver
is not built for K3 platforms.
Signed-off-by: Suman Anna <s-anna@ti.com>
The PRU Ethernet driver is only applicable for SoCs containing a
PRUSS subsystem, and there is a separate equivalent driver for
SoCs containing the next generation ICSSG subsystem. The driver
currently depends on PRU_REMOTEPROC which is also enabled for TI
K3 family of SoCs, and therefore is getting built for TI K3 platforms
as well. Add an additional Kconfig dependency so that the driver
is not built for K3 platforms.
Signed-off-by: Suman Anna <s-anna@ti.com>
Merge branch 'audio_display-ti-linux-4.19.y' of git.ti.com:~jyrisarha/ti-linux-kernel/jyrisarhas-audio-video-linux-feature-tree into ti-linux-4.19.y
TI-Feature: audio-display
TI-Tree: git@git.ti.com:~jyrisarha/ti-linux-kernel/jyrisarhas-audio-video-linux-feature-tree.git
TI-Branch: audio_display-ti-linux-4.19.y
* 'audio_display-ti-linux-4.19.y' of git.ti.com:~jyrisarha/ti-linux-kernel/jyrisarhas-audio-video-linux-feature-tree:
ASoC: pcm3168a: Implement set_tdm_slot callback
ASoC: pcm3168a: Enable TDM support for DSP_A/B modes
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: audio-display
TI-Tree: git@git.ti.com:~jyrisarha/ti-linux-kernel/jyrisarhas-audio-video-linux-feature-tree.git
TI-Branch: audio_display-ti-linux-4.19.y
* 'audio_display-ti-linux-4.19.y' of git.ti.com:~jyrisarha/ti-linux-kernel/jyrisarhas-audio-video-linux-feature-tree:
ASoC: pcm3168a: Implement set_tdm_slot callback
ASoC: pcm3168a: Enable TDM support for DSP_A/B modes
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
Merge branch 'peter/ti-linux-4.19.y/topic/audio' of https://github.com/omap-audio/linux-audio into audio_display-ti-linux-4.19.y
2019.02 - pcm3168a fixes needed for j721e
* 'peter/ti-linux-4.19.y/topic/audio' of https://github.com/omap-audio/linux-audio:
ASoC: pcm3168a: Implement set_tdm_slot callback
ASoC: pcm3168a: Enable TDM support for DSP_A/B modes
2019.02 - pcm3168a fixes needed for j721e
* 'peter/ti-linux-4.19.y/topic/audio' of https://github.com/omap-audio/linux-audio:
ASoC: pcm3168a: Implement set_tdm_slot callback
ASoC: pcm3168a: Enable TDM support for DSP_A/B modes
ASoC: pcm3168a: Implement set_tdm_slot callback
Initially we only going to care about the slot_width as for example
DSP_A/B needs 32 bclk per slots and to be able to use TDM mode the codec
(and CPU) needs to use DSP_A/B modes.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Initially we only going to care about the slot_width as for example
DSP_A/B needs 32 bclk per slots and to be able to use TDM mode the codec
(and CPU) needs to use DSP_A/B modes.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
ASoC: pcm3168a: Enable TDM support for DSP_A/B modes
The 24-bit TDM mode also applies to DSP_A and DSP_B modes.
Most dais on the SoC side can not interpret I2S/Left_j with other than 2
channels of audio.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
The 24-bit TDM mode also applies to DSP_A and DSP_B modes.
Most dais on the SoC side can not interpret I2S/Left_j with other than 2
channels of audio.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
dmaengine: ti: k3-udma: Make slave TR mode operational with PDMAs
If we use TR mode for peripherals (serviced by PDMA) which is not a
streaming type (cyclic) then PDMA will not return all the data it has
received from the remote end causing the RX operation to stall.
However telling PDMA to close the packet and flush it's FIFO makes the TR
slave mode operational with the same limitation as with packet mode.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
If we use TR mode for peripherals (serviced by PDMA) which is not a
streaming type (cyclic) then PDMA will not return all the data it has
received from the remote end causing the RX operation to stall.
However telling PDMA to close the packet and flush it's FIFO makes the TR
slave mode operational with the same limitation as with packet mode.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
dmaengine: ti: k3-udma: Fix kernel crash when _prep* callback fails
Since the descriptor is not yet prepared, the vd->tx.chan is not yet valid
and when trying to free up the memory we will hit NULL pointer dereference.
Change the udma_free_hwdesc() parameters to fix this.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Since the descriptor is not yet prepared, the vd->tx.chan is not yet valid
and when trying to free up the memory we will hit NULL pointer dereference.
Change the udma_free_hwdesc() parameters to fix this.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
dmaengine: ti: k3-udma: new workaround for packet mode rx
Instead of creating a temporary continuous buffer to do the transfer and
when it is finished copy the received data back to the client's sgl:
Create host buffer descriptors for each sg section and push them to fdr and
let UDMA to fill them and return the packet.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Instead of creating a temporary continuous buffer to do the transfer and
when it is finished copy the received data back to the client's sgl:
Create host buffer descriptors for each sg section and push them to fdr and
let UDMA to fill them and return the packet.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
dmaengine: ti: k3-udma: Use define for the default ring size
In case we might need to adjust the ring size it is going to be easier if
there is only one place to touch.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
In case we might need to adjust the ring size it is going to be easier if
there is only one place to touch.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Merge branch 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree into ti-linux-4.19.y
TI-Feature: platform_base
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree:
dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721E
arm64: dts: ti: k3-j721e: Update the power domain cells
arm64: dts: ti: k3-j721e-main: Add Main NavSS Interrupt controller node
Revert "soc: ti: am6: Enable interrupt controller drivers"
Revert "soc: ti: Add TI_MESSAGE_MANAGER to default K3 AM65x SoC options"
arm64: arch_k3: Enable interrupt controller drivers
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: platform_base
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree:
dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721E
arm64: dts: ti: k3-j721e: Update the power domain cells
arm64: dts: ti: k3-j721e-main: Add Main NavSS Interrupt controller node
Revert "soc: ti: am6: Enable interrupt controller drivers"
Revert "soc: ti: Add TI_MESSAGE_MANAGER to default K3 AM65x SoC options"
arm64: arch_k3: Enable interrupt controller drivers
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
Merge branch 'hwspinlock-linux-4.19.y' of git://git.ti.com/rpmsg/hwspinlock into rpmsg-ti-linux-4.19.y
Pull in the hwspinlock feature tree that moves the AM65x HwSpinlock DT
node from cbass_main interconnect node to the more accurate main_navss
interconnect node.
* 'hwspinlock-linux-4.19.y' of git://git.ti.com/rpmsg/hwspinlock:
arm64: dts: ti: k3-am65-main: Move hwspinlock node to main_navss interconnect
Signed-off-by: Suman Anna <s-anna@ti.com>
Pull in the hwspinlock feature tree that moves the AM65x HwSpinlock DT
node from cbass_main interconnect node to the more accurate main_navss
interconnect node.
* 'hwspinlock-linux-4.19.y' of git://git.ti.com/rpmsg/hwspinlock:
arm64: dts: ti: k3-am65-main: Move hwspinlock node to main_navss interconnect
Signed-off-by: Suman Anna <s-anna@ti.com>
mmc: sdhci_am654: Fix DLL trim and driver strength configuration
DLL trim and driver strength are one-time configurations which don't
need to be redone every time the DLL frequency is changed. Move this
configuration to the sdhci_am654_init() call.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
DLL trim and driver strength are one-time configurations which don't
need to be redone every time the DLL frequency is changed. Move this
configuration to the sdhci_am654_init() call.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
mmc: sdhci_am654: Fix SLOTTYPE write
In the call to regmap_update_bits() for SLOTTYPE, the mask and value
fields are exchanged. Fix this. This didn't have any affect on behaviour
because this was a NOP and it was taking the correct value from the
bootloader.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
In the call to regmap_update_bits() for SLOTTYPE, the mask and value
fields are exchanged. Fix this. This didn't have any affect on behaviour
because this was a NOP and it was taking the correct value from the
bootloader.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
mmc: sdhci_am654: Print error message if the DLL fails to lock
Print an error message and return if DLL fails to lock.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Print an error message and return if DLL fails to lock.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
mmc: sdhci_am654: Improve line wrapping with regmap_*() calls
Line wrapping with the regmap_*() functions is way more conservative
than required by the 80 character rule. Expand the function calls out to
use less number of lines.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Line wrapping with the regmap_*() functions is way more conservative
than required by the 80 character rule. Expand the function calls out to
use less number of lines.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
ti_config_fragments: connectivity.cfg: Enable Cadence USB3 drivers
This is required for USB support on J721e.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This is required for USB support on J721e.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
usb: cdns3: Implement Idle state for Type-C
For Type-C we need to have clear indication of
cable detached state so that we can keep Host and
Gadget controllers in idle state and program
the Lane swap feature during the next cable attach,
before starting Host/Gadget controllers.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
For Type-C we need to have clear indication of
cable detached state so that we can keep Host and
Gadget controllers in idle state and program
the Lane swap feature during the next cable attach,
before starting Host/Gadget controllers.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
usb: cdns3: make dynamic role switching work
We need to the flow as in "Figure 14. Software OTG Control"
in user guide.
This meens we need to request for HOST_BUS_REQ/DEV_BUS_REQ
while starting host/device role respectively.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
We need to the flow as in "Figure 14. Software OTG Control"
in user guide.
This meens we need to request for HOST_BUS_REQ/DEV_BUS_REQ
while starting host/device role respectively.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
usb: cdns3: use phy power on/off
PHY needs to be powered on.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
PHY needs to be powered on.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
usb: cdns3: Add TI specific wrapper driver
The J721e platform comes with 2 Cadence USB3 controller
instances. This driver supports the TI specific wrapper
on this platform.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The J721e platform comes with 2 Cadence USB3 controller
instances. This driver supports the TI specific wrapper
on this platform.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
dt-bindings: usb: Add binding for the TI wrapper for Cadence USB3 controller
TI platforms have a wrapper module around the Cadence USB3
controller. Add binding information for that.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
TI platforms have a wrapper module around the Cadence USB3
controller. Add binding information for that.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
usb: cdns3: drd: print error on xhci/dev ready timeout
Print an error message if XHCI_READY or DEV_READY times out.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Print an error message if XHCI_READY or DEV_READY times out.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
usb: cdns3: drd: don't call drd_update_mode in drd_init()
At drd_init(), 'desired_dr_mode' is not yet correctly set
based on enabled drivers and dr_mode in DT. So don't call
drd_update_mode() from here.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
At drd_init(), 'desired_dr_mode' is not yet correctly set
based on enabled drivers and dr_mode in DT. So don't call
drd_update_mode() from here.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
usb: cdns3: support separate IRQs for otg/xhci/dev
Some platforms (e.g. TI J721e) have separate interrupt lines
for OTG, XHCI and Device controllers. Provide for that.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Some platforms (e.g. TI J721e) have separate interrupt lines
for OTG, XHCI and Device controllers. Provide for that.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
usb:cdns3 Fix for stuck packets in on-chip OUT buffer.
Controller for OUT endpoints has shared on-chip buffers for all incoming
packets, including ep0out. It's FIFO buffer, so packets must be handled
by DMA in correct order. If the first packet in the buffer will not be
handled, then the following packets directed for other endpoints and
functions will be blocked.
Additionally the packets directed to one endpoint can block entire on-chip
buffers. In this case transfer to other endpoints also will blocked.
To resolve this issue after raising the descriptor missing interrupt
driver prepares internal usb_request object and use it to arm DMA
transfer.
The problematic situation was observed in case when endpoint has
been enabled but no usb_request were queued. Driver try detects
such endpoints and will use this workaround only for these endpoint.
Driver use limited number of buffer. This number can be set by macro
CDNS_WA2_NUM_BUFFERS.
Such blocking situation was observed on ACM gadget. For this function
host send OUT data packet but ACM function is not prepared for
this packet. It's cause that buffer placed in on chip memory block
transfer to other endpoints.
Issue has been fixed for DEV_VER_V2 version of controller.
Signed-off-by: Pawel Laszczak <pawell@cadence.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Controller for OUT endpoints has shared on-chip buffers for all incoming
packets, including ep0out. It's FIFO buffer, so packets must be handled
by DMA in correct order. If the first packet in the buffer will not be
handled, then the following packets directed for other endpoints and
functions will be blocked.
Additionally the packets directed to one endpoint can block entire on-chip
buffers. In this case transfer to other endpoints also will blocked.
To resolve this issue after raising the descriptor missing interrupt
driver prepares internal usb_request object and use it to arm DMA
transfer.
The problematic situation was observed in case when endpoint has
been enabled but no usb_request were queued. Driver try detects
such endpoints and will use this workaround only for these endpoint.
Driver use limited number of buffer. This number can be set by macro
CDNS_WA2_NUM_BUFFERS.
Such blocking situation was observed on ACM gadget. For this function
host send OUT data packet but ACM function is not prepared for
this packet. It's cause that buffer placed in on chip memory block
transfer to other endpoints.
Issue has been fixed for DEV_VER_V2 version of controller.
Signed-off-by: Pawel Laszczak <pawell@cadence.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
usb:cdns3 Add Cadence USB3 DRD Driver
This patch introduce new Cadence USBSS DRD driver to Linux kernel.
The Cadence USBSS DRD Driver is a highly configurable IP Core which
can be instantiated as Dual-Role Device (DRD), Peripheral Only and
Host Only (XHCI)configurations.
The current driver has been validated with FPGA platform. We have
support for PCIe bus, which is used on FPGA prototyping.
The host side of USBSS-DRD controller is compliant with XHCI
specification, so it works with standard XHCI Linux driver.
Signed-off-by: Pawel Laszczak <pawell@cadence.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This patch introduce new Cadence USBSS DRD driver to Linux kernel.
The Cadence USBSS DRD Driver is a highly configurable IP Core which
can be instantiated as Dual-Role Device (DRD), Peripheral Only and
Host Only (XHCI)configurations.
The current driver has been validated with FPGA platform. We have
support for PCIe bus, which is used on FPGA prototyping.
The host side of USBSS-DRD controller is compliant with XHCI
specification, so it works with standard XHCI Linux driver.
Signed-off-by: Pawel Laszczak <pawell@cadence.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721E
Add pinctrl macros for J721E SoC. These macro definitions are
similar to that of AM6, but adding new definitions to avoid
any naming confusions in the soc dts files.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add pinctrl macros for J721E SoC. These macro definitions are
similar to that of AM6, but adding new definitions to avoid
any naming confusions in the soc dts files.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
arm64: dts: ti: k3-j721e: Update the power domain cells
Update the power-domain cells to 2 and mark all devices as
exclusive.
Signed-off-by: Subhajit Paul <subhajit_paul@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Update the power-domain cells to 2 and mark all devices as
exclusive.
Signed-off-by: Subhajit Paul <subhajit_paul@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
arm64: dts: ti: k3-j721e-main: Add Main NavSS Interrupt controller node
Add the Interrupt controller node for the Interrupt Router present within
the Main NavSS module. This Interrupt Router can route 192 interrupts to
the GIC_SPI in 3 sets of 64 interrupts each. Note that the last set is
reserved for the host ID A72_3 for hypervisor usecases, so the node is
added only with 2 sets for the Linux kernel context (host id A72_2). This
is specified through the ti,sci-rm-range-girq property, and matches the
RM board config in the system-firmware-image-gen repo.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add the Interrupt controller node for the Interrupt Router present within
the Main NavSS module. This Interrupt Router can route 192 interrupts to
the GIC_SPI in 3 sets of 64 interrupts each. Note that the last set is
reserved for the host ID A72_3 for hypervisor usecases, so the node is
added only with 2 sets for the Linux kernel context (host id A72_2). This
is specified through the ti,sci-rm-range-girq property, and matches the
RM board config in the system-firmware-image-gen repo.
Signed-off-by: Suman Anna <s-anna@ti.com>
Revert "soc: ti: am6: Enable interrupt controller drivers"
This reverts commit 4c94b81b8891374830c3140943cea92b55bc57bd.
The TI_SCI_PROTOCOL and the K3 irqchip driver symbols TI_SCI_INTR_IRQCHIP
and TI_SCI_INTA_IRQCHIP are common to all existing K3 SoCs, and so are
selected properly under the ARCH_K3 Kconfig symbol. These Kconfig symbols
therefore need not be selected under the SoC-specific ARCH_K3_AM6_SOC
Kconfig symbol, so drop these.
Signed-off-by: Suman Anna <s-anna@ti.com>
This reverts commit 4c94b81b8891374830c3140943cea92b55bc57bd.
The TI_SCI_PROTOCOL and the K3 irqchip driver symbols TI_SCI_INTR_IRQCHIP
and TI_SCI_INTA_IRQCHIP are common to all existing K3 SoCs, and so are
selected properly under the ARCH_K3 Kconfig symbol. These Kconfig symbols
therefore need not be selected under the SoC-specific ARCH_K3_AM6_SOC
Kconfig symbol, so drop these.
Signed-off-by: Suman Anna <s-anna@ti.com>
Revert "soc: ti: Add TI_MESSAGE_MANAGER to default K3 AM65x SoC options"
This reverts commit 6d30136ffe31b55673c210e67af72a1c3864bb14.
The TI_SCI_PROTOCOL and TI_MESSAGE_MANAGER Kconfig options are essential
for all existing K3 SoCs, and so are selected properly under the ARCH_K3
Kconfig symbol. The TI_MESSAGE_MANAGER Kconfig therefore need not be
selected under the SoC-specific ARCH_K3_AM6_SOC Kconfig symbol, so drop
this.
Signed-off-by: Suman Anna <s-anna@ti.com>
This reverts commit 6d30136ffe31b55673c210e67af72a1c3864bb14.
The TI_SCI_PROTOCOL and TI_MESSAGE_MANAGER Kconfig options are essential
for all existing K3 SoCs, and so are selected properly under the ARCH_K3
Kconfig symbol. The TI_MESSAGE_MANAGER Kconfig therefore need not be
selected under the SoC-specific ARCH_K3_AM6_SOC Kconfig symbol, so drop
this.
Signed-off-by: Suman Anna <s-anna@ti.com>
arm64: arch_k3: Enable interrupt controller drivers
commit 009669e7481361470f7667c96a96893c8ba5f461 upstream.
Select the TISCI Interrupt Router, Aggregator drivers and all its
dependencies for TI's SoCs based on K3 architecture.
Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
[s-anna@ti.com: cherry-pick commit '009669e74813' from v5.2]
Signed-off-by: Suman Anna <s-anna@ti.com>
commit 009669e7481361470f7667c96a96893c8ba5f461 upstream.
Select the TISCI Interrupt Router, Aggregator drivers and all its
dependencies for TI's SoCs based on K3 architecture.
Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
[s-anna@ti.com: cherry-pick commit '009669e74813' from v5.2]
Signed-off-by: Suman Anna <s-anna@ti.com>
arm64: dts: ti: k3-am65-main: Move mailbox nodes to main_navss interconnect
All the Mailbox cluster nodes were currently added directly under the
cbass_main interconnect node, even though the Mailbox IP is present within
the Main NavSS sub-module and is accessible from the MPU through the Main
NavSS local interconnect. The Main NavSS interconnect is represented as
its own interconnect node, so move all these nodes under the main_navss
interconnect node.
Signed-off-by: Suman Anna <s-anna@ti.com>
All the Mailbox cluster nodes were currently added directly under the
cbass_main interconnect node, even though the Mailbox IP is present within
the Main NavSS sub-module and is accessible from the MPU through the Main
NavSS local interconnect. The Main NavSS interconnect is represented as
its own interconnect node, so move all these nodes under the main_navss
interconnect node.
Signed-off-by: Suman Anna <s-anna@ti.com>
arm64: dts: ti: k3-am65-main: Move hwspinlock node to main_navss interconnect
The commit c18a938bdbac ("arm64: dts: ti: k3-am65-main: Add hwspinlock
node") had previously added the HwSpinlock node directly under the
cbass_main interconnect node even though it is connected on the Main
NavSS local interconnect. The Main NavSS interconnect is represented
as its own interconnect node, so move this node under the main_navss
interconnect node.
Signed-off-by: Suman Anna <s-anna@ti.com>
The commit c18a938bdbac ("arm64: dts: ti: k3-am65-main: Add hwspinlock
node") had previously added the HwSpinlock node directly under the
cbass_main interconnect node even though it is connected on the Main
NavSS local interconnect. The Main NavSS interconnect is represented
as its own interconnect node, so move this node under the main_navss
interconnect node.
Signed-off-by: Suman Anna <s-anna@ti.com>
usb:common Simplify usb_decode_get_set_descriptor function.
Patch moves switch responsible for decoding descriptor type
outside snprintf. It improves code readability a little.
Signed-off-by: Pawel Laszczak <pawell@cadence.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Patch moves switch responsible for decoding descriptor type
outside snprintf. It improves code readability a little.
Signed-off-by: Pawel Laszczak <pawell@cadence.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
usb:common Patch simplify usb_decode_set_clear_feature function.
Patch adds usb_decode_test_mode and usb_decode_device_feature functions,
which allow to make more readable and simplify the
usb_decode_set_clear_feature function.
Signed-off-by: Pawel Laszczak <pawell@cadence.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Patch adds usb_decode_test_mode and usb_decode_device_feature functions,
which allow to make more readable and simplify the
usb_decode_set_clear_feature function.
Signed-off-by: Pawel Laszczak <pawell@cadence.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
usb:common Separated decoding functions from dwc3 driver.
Patch moves some decoding functions from driver/usb/dwc3/debug.h driver
to driver/usb/common/debug.c file. These moved functions include:
dwc3_decode_get_status
dwc3_decode_set_clear_feature
dwc3_decode_set_address
dwc3_decode_get_set_descriptor
dwc3_decode_get_configuration
dwc3_decode_set_configuration
dwc3_decode_get_intf
dwc3_decode_set_intf
dwc3_decode_synch_frame
dwc3_decode_set_sel
dwc3_decode_set_isoch_delay
dwc3_decode_ctrl
These functions are used also in inroduced cdns3 driver.
All functions prefixes were changed from dwc3 to usb.
Also, function's parameters has been extended according to the name
of fields in standard SETUP packet.
Additionally, patch adds usb_decode_ctrl function to
include/linux/usb/ch9.h file.
Signed-off-by: Pawel Laszczak <pawell@cadence.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Patch moves some decoding functions from driver/usb/dwc3/debug.h driver
to driver/usb/common/debug.c file. These moved functions include:
dwc3_decode_get_status
dwc3_decode_set_clear_feature
dwc3_decode_set_address
dwc3_decode_get_set_descriptor
dwc3_decode_get_configuration
dwc3_decode_set_configuration
dwc3_decode_get_intf
dwc3_decode_set_intf
dwc3_decode_synch_frame
dwc3_decode_set_sel
dwc3_decode_set_isoch_delay
dwc3_decode_ctrl
These functions are used also in inroduced cdns3 driver.
All functions prefixes were changed from dwc3 to usb.
Also, function's parameters has been extended according to the name
of fields in standard SETUP packet.
Additionally, patch adds usb_decode_ctrl function to
include/linux/usb/ch9.h file.
Signed-off-by: Pawel Laszczak <pawell@cadence.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
dt-bindings: add binding for USBSS-DRD controller.
This patch aim at documenting USB related dt-bindings for the
Cadence USBSS-DRD controller.
Signed-off-by: Pawel Laszczak <pawell@cadence.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This patch aim at documenting USB related dt-bindings for the
Cadence USBSS-DRD controller.
Signed-off-by: Pawel Laszczak <pawell@cadence.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
usb: dwc3: debug: purge usage of strcat
commit 1381a5113caf764f090b912b478663275e7b999e upstream.
Now that buffer size is always passed around, we don't need to rely on
strcat anymore.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
commit 1381a5113caf764f090b912b478663275e7b999e upstream.
Now that buffer size is always passed around, we don't need to rely on
strcat anymore.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
usb: dwc3: trace: pass trace buffer size to decoding functions
commit 7790b3556fccc555ae422f1576e97bf34c8ab8b6 upstream.
Instead of assuming that our buffer is big enough, let's pass the
buffer size around so printing functions can make sure they won't
overflow the buffer.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
commit 7790b3556fccc555ae422f1576e97bf34c8ab8b6 upstream.
Instead of assuming that our buffer is big enough, let's pass the
buffer size around so printing functions can make sure they won't
overflow the buffer.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
usb: dwc3: trace: log ep commands in hex
commit 1517265228b4ea6b89379fa8e134e62f75ea1dfe upstream.
They are much more useful in hexadecimal than in decimal. Moreover,
generic commands are already logged in hex.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
commit 1517265228b4ea6b89379fa8e134e62f75ea1dfe upstream.
They are much more useful in hexadecimal than in decimal. Moreover,
generic commands are already logged in hex.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
usb: dwc3: debugfs: Properly print/set link state for HS
commit 0d36dede457873404becd7c9cb9d0f2bcfd0dcd9 upstream.
Highspeed device and below has different state names than superspeed and
higher. Add proper checks and printouts of link states for highspeed and
below.
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
commit 0d36dede457873404becd7c9cb9d0f2bcfd0dcd9 upstream.
Highspeed device and below has different state names than superspeed and
higher. Add proper checks and printouts of link states for highspeed and
below.
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Merge branch 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree into ti-linux-4.19.y
TI-Feature: platform_base
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree:
firmware: ti_sci: extend clock identifiers from u8 to u32
clk: keystone: sci-clk: extend clock IDs to 32 bits
clk: keystone: sci-clk: cut down the clock name length
arm64: defconfig: Enable TI's J721E SoC platform
arm64: dts: ti: Add support for J721E Common Processor Board
soc: ti: Add Support for J721E SoC config option
arm64: dts: ti: Add Support for J721E SoC
dt-bindings: serial: 8250_omap: Add compatible for J721E UART controller
dt-bindings: arm: ti: Add bindings for J721E SoC
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: platform_base
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree:
firmware: ti_sci: extend clock identifiers from u8 to u32
clk: keystone: sci-clk: extend clock IDs to 32 bits
clk: keystone: sci-clk: cut down the clock name length
arm64: defconfig: Enable TI's J721E SoC platform
arm64: dts: ti: Add support for J721E Common Processor Board
soc: ti: Add Support for J721E SoC config option
arm64: dts: ti: Add Support for J721E SoC
dt-bindings: serial: 8250_omap: Add compatible for J721E UART controller
dt-bindings: arm: ti: Add bindings for J721E SoC
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
firmware: ti_sci: extend clock identifiers from u8 to u32
Future SoCs are going to have more than 255 device clocks in certain cases,
and thus the API must be extended to support this. The support is done in
backwards compatible extension, in which the new u32 clock identifier
fields are only used if the existing u8 size clock identifier is set as
255. In all the other cases, the existing u8 clock identifier is used. As
the size of the messages sent / received is not verified for existing
devices / old firmware, increasing the size of the messages from the end
is also fine. Due to this reason, depending on ABI version isn't necessary
either.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Future SoCs are going to have more than 255 device clocks in certain cases,
and thus the API must be extended to support this. The support is done in
backwards compatible extension, in which the new u32 clock identifier
fields are only used if the existing u8 size clock identifier is set as
255. In all the other cases, the existing u8 clock identifier is used. As
the size of the messages sent / received is not verified for existing
devices / old firmware, increasing the size of the messages from the end
is also fine. Due to this reason, depending on ABI version isn't necessary
either.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
clk: keystone: sci-clk: extend clock IDs to 32 bits
Currently, the clock identifiers are limited to 255. To support future
SoCs, this muse be extended to 32 bits, which should provide way more
than enough space. Basic support for extending the clock API is going
to be implemented in the firmware driver, but there are some minor
changes that need to be done on the clock driver side first.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Currently, the clock identifiers are limited to 255. To support future
SoCs, this muse be extended to 32 bits, which should provide way more
than enough space. Basic support for extending the clock API is going
to be implemented in the firmware driver, but there are some minor
changes that need to be done on the clock driver side first.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
clk: keystone: sci-clk: cut down the clock name length
There is no need to store the full node name to the individual clocks,
as this will just consome memory and make the clock debug entries
unnecessary long. Just shorten this to "clk" for now.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
There is no need to store the full node name to the individual clocks,
as this will just consome memory and make the clock debug entries
unnecessary long. Just shorten this to "clk" for now.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
arm64: defconfig: Enable TI's J721E SoC platform
Enable J721E SoC support from TI.
Signed-off-by: Nishanth Menon <nm@ti.com>
Enable J721E SoC support from TI.
Signed-off-by: Nishanth Menon <nm@ti.com>
arm64: dts: ti: Add support for J721E Common Processor Board
Add Support for J721E Common Processor board support.
The EVM architecture is as follows:
+------------------------------------------------------+
| +-------------------------------------------+ |
| | | |
| | Add-on Card 1 Options | |
| | | |
| +-------------------------------------------+ |
| |
| |
| +-------------------+ |
| | | |
| | SOM | |
| +--------------+ | | |
| | | | | |
| | Add-on | +-------------------+ |
| | Card 2 | | Power Supply
| | Options | | |
| | | | |
| +--------------+ | <---
+------------------------------------------------------+
Common Processor Board
Common Processor board is the baseboard that has most of the actual
connectors, power supply etc. A SOM (System on Module) is plugged on
to the common processor board and this contains the SoC, PMIC, DDR and
basic high speed components necessary for functionality. Add-n card
options add further functionality (such as additional Audio, Display,
networking options).
Note:
A) The minimum configuration required to boot up the board is System On
Module(SOM) + Common Processor Board.
B) Since there is just a single SOM and Common Processor Board, we are
maintaining common processor board as the base dts and SOM as the dtsi
that we include. In the future as more SOM's appear, we should move
common processor board as a dtsi and include configurations as dts.
C) All daughter cards beyond the basic boards shall be maintained as
overlays.
Signed-off-by: Nishanth Menon <nm@ti.com>
Add Support for J721E Common Processor board support.
The EVM architecture is as follows:
+------------------------------------------------------+
| +-------------------------------------------+ |
| | | |
| | Add-on Card 1 Options | |
| | | |
| +-------------------------------------------+ |
| |
| |
| +-------------------+ |
| | | |
| | SOM | |
| +--------------+ | | |
| | | | | |
| | Add-on | +-------------------+ |
| | Card 2 | | Power Supply
| | Options | | |
| | | | |
| +--------------+ | <---
+------------------------------------------------------+
Common Processor Board
Common Processor board is the baseboard that has most of the actual
connectors, power supply etc. A SOM (System on Module) is plugged on
to the common processor board and this contains the SoC, PMIC, DDR and
basic high speed components necessary for functionality. Add-n card
options add further functionality (such as additional Audio, Display,
networking options).
Note:
A) The minimum configuration required to boot up the board is System On
Module(SOM) + Common Processor Board.
B) Since there is just a single SOM and Common Processor Board, we are
maintaining common processor board as the base dts and SOM as the dtsi
that we include. In the future as more SOM's appear, we should move
common processor board as a dtsi and include configurations as dts.
C) All daughter cards beyond the basic boards shall be maintained as
overlays.
Signed-off-by: Nishanth Menon <nm@ti.com>
soc: ti: Add Support for J721E SoC config option
Add option to build J721E SoC specific components
Signed-off-by: Nishanth Menon <nm@ti.com>
Add option to build J721E SoC specific components
Signed-off-by: Nishanth Menon <nm@ti.com>
arm64: dts: ti: Add Support for J721E SoC
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Signed-off-by: Nishanth Menon <nm@ti.com>
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Signed-off-by: Nishanth Menon <nm@ti.com>
dt-bindings: serial: 8250_omap: Add compatible for J721E UART controller
J721e uses a UART controller that is compatible with AM654 UART.
Introduce a specific compatible to help handle the differences if
necessary.
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
J721e uses a UART controller that is compatible with AM654 UART.
Introduce a specific compatible to help handle the differences if
necessary.
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
dt-bindings: arm: ti: Add bindings for J721E SoC
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Signed-off-by: Nishanth Menon <nm@ti.com>
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Signed-off-by: Nishanth Menon <nm@ti.com>
Merge branch 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel into ti-linux-4.19.y
TI-Feature: connectivity
TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git
TI-Branch: connectivity-ti-linux-4.19.y
* 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel:
net: ethernet: ti: am65-cpsw-nuss: enable gro
net: ethernet: ti: icssg_prueth: fix rx napi add function
net: ethernet: ti: am65-cpsw-nuss: fix rx napi add function
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: connectivity
TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git
TI-Branch: connectivity-ti-linux-4.19.y
* 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel:
net: ethernet: ti: am65-cpsw-nuss: enable gro
net: ethernet: ti: icssg_prueth: fix rx napi add function
net: ethernet: ti: am65-cpsw-nuss: fix rx napi add function
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
net: ethernet: ti: am65-cpsw-nuss: enable gro
Enable Generic Receive Offload (GRO) support by TI AM65x MCU CPSW driver.
For GRO support:
- the netif_receive_skb(skb) is replaced with
napi_gro_receive(&common->napi_rx, skb),
- the napi_complete() is replaced with napi_complete_done().
This change shows significant throughput improvement:
-- gro off
ethtool -K eth0 gro off
iperf -s (client: iperf -c <addr> -d -w128K -t30)
[ ID] Interval Transfer Bandwidth
[ 4] 0.0-30.0 sec 2.53 GBytes 723 Mbits/ses
[ 6] 0.0-30.0 sec 1.36 GBytes 388 Mbits/sec
-- gro on
ethtool -K eth0 gso on gro on
iperf -s
[ ID] Interval Transfer Bandwidth
[ 4] 0.0-30.0 sec 3.27 GBytes 935 Mbits/sec
[ 6] 0.0-30.0 sec 1.75 GBytes 501 Mbits/sec
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Enable Generic Receive Offload (GRO) support by TI AM65x MCU CPSW driver.
For GRO support:
- the netif_receive_skb(skb) is replaced with
napi_gro_receive(&common->napi_rx, skb),
- the napi_complete() is replaced with napi_complete_done().
This change shows significant throughput improvement:
-- gro off
ethtool -K eth0 gro off
iperf -s (client: iperf -c <addr> -d -w128K -t30)
[ ID] Interval Transfer Bandwidth
[ 4] 0.0-30.0 sec 2.53 GBytes 723 Mbits/ses
[ 6] 0.0-30.0 sec 1.36 GBytes 388 Mbits/sec
-- gro on
ethtool -K eth0 gso on gro on
iperf -s
[ ID] Interval Transfer Bandwidth
[ 4] 0.0-30.0 sec 3.27 GBytes 935 Mbits/sec
[ 6] 0.0-30.0 sec 1.75 GBytes 501 Mbits/sec
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
net: ethernet: ti: icssg_prueth: fix rx napi add function
Use correct RX NAPI registration function instead of netif_tx_napi_add(),
which was used due to copy-past error.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Use correct RX NAPI registration function instead of netif_tx_napi_add(),
which was used due to copy-past error.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
net: ethernet: ti: am65-cpsw-nuss: fix rx napi add function
Use correct RX NAPI registration function instead of netif_tx_napi_add(),
which was used due to copy-past error.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Use correct RX NAPI registration function instead of netif_tx_napi_add(),
which was used due to copy-past error.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Merge branch 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel into ti-linux-4.19.y
TI-Feature: connectivity
TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git
TI-Branch: connectivity-ti-linux-4.19.y
* 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel:
arm64: dts: ti: add mii-rt phandle in icssg prueth DT nodes
net: ti: icssg_prueth: update TX IPG based on link speed
dt-bindings: net: ti, icssg-prueth: bindings to update TX IPG value
net: ti: icssg_prueth: update ICSSG RGMII cfg based on PHY link parameters
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: connectivity
TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git
TI-Branch: connectivity-ti-linux-4.19.y
* 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel:
arm64: dts: ti: add mii-rt phandle in icssg prueth DT nodes
net: ti: icssg_prueth: update TX IPG based on link speed
dt-bindings: net: ti, icssg-prueth: bindings to update TX IPG value
net: ti: icssg_prueth: update ICSSG RGMII cfg based on PHY link parameters
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
Merge branch 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree into ti-linux-4.19.y
TI-Feature: platform_base
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree:
ARM: OMAP2+: hwmod: Introduce cpu_pm notifiers for context save/restore
arm: mach-omap2: omap_hwmod: Introduce omap_hwmod_rst save/restore
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: platform_base
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree:
ARM: OMAP2+: hwmod: Introduce cpu_pm notifiers for context save/restore
arm: mach-omap2: omap_hwmod: Introduce omap_hwmod_rst save/restore
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
arm64: dts: ti: add mii-rt phandle in icssg prueth DT nodes
To allow configure MII RT interface TX_IPG0/1 values differently
for 100M link vs 1G link, add phandle for mii_rt regmap node
in icssg prueth DT nodes.
Acked-by: Roger Quadros <rogerq@ti.com>
Acked-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
To allow configure MII RT interface TX_IPG0/1 values differently
for 100M link vs 1G link, add phandle for mii_rt regmap node
in icssg prueth DT nodes.
Acked-by: Roger Quadros <rogerq@ti.com>
Acked-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
net: ti: icssg_prueth: update TX IPG based on link speed
Firmware requires that minimum inter packet gap (TX_IPG0/1 field of
ICSSG_TX_IPG0/1 register) is to be set to desired values based on the
PHY link speed. This patch updates the same based on PHY link speed.
Acked-by: Roger Quadros <rogerq@ti.com>
Acked-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Firmware requires that minimum inter packet gap (TX_IPG0/1 field of
ICSSG_TX_IPG0/1 register) is to be set to desired values based on the
PHY link speed. This patch updates the same based on PHY link speed.
Acked-by: Roger Quadros <rogerq@ti.com>
Acked-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
dt-bindings: net: ti, icssg-prueth: bindings to update TX IPG value
ICSSG PRU Ethernet ports should support both 100M/1G operation. This
requires MII RT syscon regmap base address to be available to the
driver to configure the TX IPG values differently for 100M and 1G link
speeds. Thus add the required bindings details to the documentation.
Acked-by: Roger Quadros <rogerq@ti.com>
Acked-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
ICSSG PRU Ethernet ports should support both 100M/1G operation. This
requires MII RT syscon regmap base address to be available to the
driver to configure the TX IPG values differently for 100M and 1G link
speeds. Thus add the required bindings details to the documentation.
Acked-by: Roger Quadros <rogerq@ti.com>
Acked-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
net: ti: icssg_prueth: update ICSSG RGMII cfg based on PHY link parameters
Currently driver doesn't set the speed and full duplex parameters
in RGMII CFG based on PHY auto negotiated parameters. This patch
make updates so that both 100M/1G link speed and full duplex are
configured in RGMII CFG register based on PHY negotiated values.
Acked-by: Roger Quadros <rogerq@ti.com>
Acked-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Currently driver doesn't set the speed and full duplex parameters
in RGMII CFG based on PHY auto negotiated parameters. This patch
make updates so that both 100M/1G link speed and full duplex are
configured in RGMII CFG register based on PHY negotiated values.
Acked-by: Roger Quadros <rogerq@ti.com>
Acked-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
ARM: OMAP2+: hwmod: Introduce cpu_pm notifiers for context save/restore
Introduce cpu_pm notifiers for context save/restore. This is needed
for AM43xx family of SoCs during rtc only mode with ddr in self-refresh.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Introduce cpu_pm notifiers for context save/restore. This is needed
for AM43xx family of SoCs during rtc only mode with ddr in self-refresh.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
arm: mach-omap2: omap_hwmod: Introduce omap_hwmod_rst save/restore
With the introduction of ti,sysc driver we no longer need to
save/restore the actual module context but the rst lines context
needs to be saved/restored. Hence add the omap_hwmod_rst save/restore
functions.
Signed-off-by: Keerthy <j-keerthy@ti.com>
With the introduction of ti,sysc driver we no longer need to
save/restore the actual module context but the rst lines context
needs to be saved/restored. Hence add the omap_hwmod_rst save/restore
functions.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Merge branch 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel into ti-linux-4.19.y
TI-Feature: connectivity
TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git
TI-Branch: connectivity-ti-linux-4.19.y
* 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel:
ARM: dts: dra76x: Update MMC2_HS200_MANUAL1 iodelay values
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: connectivity
TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git
TI-Branch: connectivity-ti-linux-4.19.y
* 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel:
ARM: dts: dra76x: Update MMC2_HS200_MANUAL1 iodelay values
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
ARM: dts: dra76x: Update MMC2_HS200_MANUAL1 iodelay values
Update the MMC2_HS200_MANUAL1 iodelay values to match with the latest
dra76x data manual[1].
Also this particular pinctrl-array is using spaces instead of tabs for
spacing between the values and the comments. Fix this as well.
[1] http://www.ti.com/lit/ds/symlink/dra76p.pdf
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Update the MMC2_HS200_MANUAL1 iodelay values to match with the latest
dra76x data manual[1].
Also this particular pinctrl-array is using spaces instead of tabs for
spacing between the values and the comments. Fix this as well.
[1] http://www.ti.com/lit/ds/symlink/dra76p.pdf
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Merge branch 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel into ti-linux-4.19.y
TI-Feature: connectivity
TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git
TI-Branch: connectivity-ti-linux-4.19.y
* 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel:
net: ti: icssg_prueth: Fix cleanup of RX flows and RX management channel
ARM: dts: am57xx-idk: Remove support for voltage switching for SD card
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: connectivity
TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git
TI-Branch: connectivity-ti-linux-4.19.y
* 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel:
net: ti: icssg_prueth: Fix cleanup of RX flows and RX management channel
ARM: dts: am57xx-idk: Remove support for voltage switching for SD card
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
Merge branch 'linux-4.19.y' of http://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable into ti-linux-4.19.y
* 'linux-4.19.y' of http://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable: (780 commits)
Linux 4.19.38
powerpc/fsl: Add FSL_PPC_BOOK3E as supported arch for nospectre_v2 boot arg
net/tls: don't leak IV and record seq when offload fails
net/tls: avoid potential deadlock in tls_set_device_offload_rx()
net/mlx5e: Fix use-after-free after xdp_return_frame
net/mlx5e: Fix the max MTU check in case of XDP
mlxsw: spectrum: Put MC TCs into DWRR mode
mlxsw: pci: Reincrease PCI reset timeout
net: hns: Fix WARNING when hns modules installed
team: fix possible recursive locking when add slaves
stmmac: pci: Adjust IOT2000 matching
net/tls: fix refcount adjustment in fallback
net: stmmac: move stmmac_check_ether_addr() to driver probe
net/rose: fix unbound loop in rose_loopback_timer()
net: rds: exchange of 8K and 1M pool
net/mlx5e: ethtool, Remove unsupported SFP EEPROM high pages query
mlxsw: spectrum: Fix autoneg status in ethtool
ipv4: set the tcp_min_rtt_wlen range from 0 to one day
ipv4: add sanity checks in ipv4_link_failure()
x86/fpu: Don't export __kernel_fpu_{begin,end}()
...
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
* 'linux-4.19.y' of http://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable: (780 commits)
Linux 4.19.38
powerpc/fsl: Add FSL_PPC_BOOK3E as supported arch for nospectre_v2 boot arg
net/tls: don't leak IV and record seq when offload fails
net/tls: avoid potential deadlock in tls_set_device_offload_rx()
net/mlx5e: Fix use-after-free after xdp_return_frame
net/mlx5e: Fix the max MTU check in case of XDP
mlxsw: spectrum: Put MC TCs into DWRR mode
mlxsw: pci: Reincrease PCI reset timeout
net: hns: Fix WARNING when hns modules installed
team: fix possible recursive locking when add slaves
stmmac: pci: Adjust IOT2000 matching
net/tls: fix refcount adjustment in fallback
net: stmmac: move stmmac_check_ether_addr() to driver probe
net/rose: fix unbound loop in rose_loopback_timer()
net: rds: exchange of 8K and 1M pool
net/mlx5e: ethtool, Remove unsupported SFP EEPROM high pages query
mlxsw: spectrum: Fix autoneg status in ethtool
ipv4: set the tcp_min_rtt_wlen range from 0 to one day
ipv4: add sanity checks in ipv4_link_failure()
x86/fpu: Don't export __kernel_fpu_{begin,end}()
...
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
Linux 4.19.38
powerpc/fsl: Add FSL_PPC_BOOK3E as supported arch for nospectre_v2 boot arg
commit e59f5bd759b7dee57593c5b6c0441609bda5d530 upstream.
Signed-off-by: Diana Craciun <diana.craciun@nxp.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit e59f5bd759b7dee57593c5b6c0441609bda5d530 upstream.
Signed-off-by: Diana Craciun <diana.craciun@nxp.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
net/tls: don't leak IV and record seq when offload fails
[ Upstream commit 12c7686111326148b4b5db189130522a4ad1be4a ]
When device refuses the offload in tls_set_device_offload_rx()
it calls tls_sw_free_resources_rx() to clean up software context
state.
Unfortunately, tls_sw_free_resources_rx() does not free all
the state tls_set_sw_offload() allocated - it leaks IV and
sequence number buffers. All other code paths which lead to
tls_sw_release_resources_rx() (which tls_sw_free_resources_rx()
calls) free those right before the call.
Avoid the leak by moving freeing of iv and rec_seq into
tls_sw_release_resources_rx().
Fixes: 4799ac81e52a ("tls: Add rx inline crypto offload")
Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Reviewed-by: Dirk van der Merwe <dirk.vandermerwe@netronome.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[ Upstream commit 12c7686111326148b4b5db189130522a4ad1be4a ]
When device refuses the offload in tls_set_device_offload_rx()
it calls tls_sw_free_resources_rx() to clean up software context
state.
Unfortunately, tls_sw_free_resources_rx() does not free all
the state tls_set_sw_offload() allocated - it leaks IV and
sequence number buffers. All other code paths which lead to
tls_sw_release_resources_rx() (which tls_sw_free_resources_rx()
calls) free those right before the call.
Avoid the leak by moving freeing of iv and rec_seq into
tls_sw_release_resources_rx().
Fixes: 4799ac81e52a ("tls: Add rx inline crypto offload")
Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Reviewed-by: Dirk van der Merwe <dirk.vandermerwe@netronome.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
net/tls: avoid potential deadlock in tls_set_device_offload_rx()
[ Upstream commit 62ef81d5632634d5e310ed25b9b940b2b6612b46 ]
If device supports offload, but offload fails tls_set_device_offload_rx()
will call tls_sw_free_resources_rx() which (unhelpfully) releases
and reacquires the socket lock.
For a small fix release and reacquire the device_offload_lock.
Fixes: 4799ac81e52a ("tls: Add rx inline crypto offload")
Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Reviewed-by: Dirk van der Merwe <dirk.vandermerwe@netronome.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[ Upstream commit 62ef81d5632634d5e310ed25b9b940b2b6612b46 ]
If device supports offload, but offload fails tls_set_device_offload_rx()
will call tls_sw_free_resources_rx() which (unhelpfully) releases
and reacquires the socket lock.
For a small fix release and reacquire the device_offload_lock.
Fixes: 4799ac81e52a ("tls: Add rx inline crypto offload")
Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Reviewed-by: Dirk van der Merwe <dirk.vandermerwe@netronome.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
net/mlx5e: Fix use-after-free after xdp_return_frame
[ Upstream commit 12fc512f5741443a03adde2ead20724da8ad550a ]
xdp_return_frame releases the frame. It leads to releasing the page, so
it's not allowed to access xdpi.xdpf->len after that, because xdpi.xdpf
is at xdp->data_hard_start after convert_to_xdp_frame. This patch moves
the memory access to precede the return of the frame.
Fixes: 58b99ee3e3ebe ("net/mlx5e: Add support for XDP_REDIRECT in device-out side")
Signed-off-by: Maxim Mikityanskiy <maximmi@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[ Upstream commit 12fc512f5741443a03adde2ead20724da8ad550a ]
xdp_return_frame releases the frame. It leads to releasing the page, so
it's not allowed to access xdpi.xdpf->len after that, because xdpi.xdpf
is at xdp->data_hard_start after convert_to_xdp_frame. This patch moves
the memory access to precede the return of the frame.
Fixes: 58b99ee3e3ebe ("net/mlx5e: Add support for XDP_REDIRECT in device-out side")
Signed-off-by: Maxim Mikityanskiy <maximmi@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
net/mlx5e: Fix the max MTU check in case of XDP
[ Upstream commit d460c2718906252a2a69bc6f89b537071f792e6e ]
MLX5E_XDP_MAX_MTU was calculated incorrectly. It didn't account for
NET_IP_ALIGN and MLX5E_HW2SW_MTU, and it also misused MLX5_SKB_FRAG_SZ.
This commit fixes the calculations and adds a brief explanation for the
formula used.
Fixes: a26a5bdf3ee2d ("net/mlx5e: Restrict the combination of large MTU and XDP")
Signed-off-by: Maxim Mikityanskiy <maximmi@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[ Upstream commit d460c2718906252a2a69bc6f89b537071f792e6e ]
MLX5E_XDP_MAX_MTU was calculated incorrectly. It didn't account for
NET_IP_ALIGN and MLX5E_HW2SW_MTU, and it also misused MLX5_SKB_FRAG_SZ.
This commit fixes the calculations and adds a brief explanation for the
formula used.
Fixes: a26a5bdf3ee2d ("net/mlx5e: Restrict the combination of large MTU and XDP")
Signed-off-by: Maxim Mikityanskiy <maximmi@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
mlxsw: spectrum: Put MC TCs into DWRR mode
[ Upstream commit f476b3f809fa02f47af6333ed63715058c3fc348 ]
Both Spectrum-1 and Spectrum-2 chips are currently configured such that
pairs of TC n (which is used for UC traffic) and TC n+8 (which is used
for MC traffic) are feeding into the same subgroup. Strict
prioritization is configured between the two TCs, and by enabling
MC-aware mode on the switch, the lower-numbered (UC) TCs are favored
over the higher-numbered (MC) TCs.
On Spectrum-2 however, there is an issue in configuration of the
MC-aware mode. As a result, MC traffic is prioritized over UC traffic.
To work around the issue, configure the MC TCs with DWRR mode (while
keeping the UC TCs in strict mode).
With this patch, the multicast-unicast arbitration results in the same
behavior on both Spectrum-1 and Spectrum-2 chips.
Fixes: 7b8195306694 ("mlxsw: spectrum: Configure MC-aware mode on mlxsw ports")
Signed-off-by: Petr Machata <petrm@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[ Upstream commit f476b3f809fa02f47af6333ed63715058c3fc348 ]
Both Spectrum-1 and Spectrum-2 chips are currently configured such that
pairs of TC n (which is used for UC traffic) and TC n+8 (which is used
for MC traffic) are feeding into the same subgroup. Strict
prioritization is configured between the two TCs, and by enabling
MC-aware mode on the switch, the lower-numbered (UC) TCs are favored
over the higher-numbered (MC) TCs.
On Spectrum-2 however, there is an issue in configuration of the
MC-aware mode. As a result, MC traffic is prioritized over UC traffic.
To work around the issue, configure the MC TCs with DWRR mode (while
keeping the UC TCs in strict mode).
With this patch, the multicast-unicast arbitration results in the same
behavior on both Spectrum-1 and Spectrum-2 chips.
Fixes: 7b8195306694 ("mlxsw: spectrum: Configure MC-aware mode on mlxsw ports")
Signed-off-by: Petr Machata <petrm@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
mlxsw: pci: Reincrease PCI reset timeout
[ Upstream commit 1ab3030193d25878b3b1409060e1e0a879800c95 ]
During driver initialization the driver sends a reset to the device and
waits for the firmware to signal that it is ready to continue.
Commit d2f372ba0914 ("mlxsw: pci: Increase PCI SW reset timeout")
increased the timeout to 13 seconds due to longer PHY calibration in
Spectrum-2 compared to Spectrum-1.
Recently it became apparent that this timeout is too short and therefore
this patch increases it again to a safer limit that will be reduced in
the future.
Fixes: c3ab435466d5 ("mlxsw: spectrum: Extend to support Spectrum-2 ASIC")
Fixes: d2f372ba0914 ("mlxsw: pci: Increase PCI SW reset timeout")
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Acked-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[ Upstream commit 1ab3030193d25878b3b1409060e1e0a879800c95 ]
During driver initialization the driver sends a reset to the device and
waits for the firmware to signal that it is ready to continue.
Commit d2f372ba0914 ("mlxsw: pci: Increase PCI SW reset timeout")
increased the timeout to 13 seconds due to longer PHY calibration in
Spectrum-2 compared to Spectrum-1.
Recently it became apparent that this timeout is too short and therefore
this patch increases it again to a safer limit that will be reduced in
the future.
Fixes: c3ab435466d5 ("mlxsw: spectrum: Extend to support Spectrum-2 ASIC")
Fixes: d2f372ba0914 ("mlxsw: pci: Increase PCI SW reset timeout")
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Acked-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>