4 years agoMerge branch 'ti-linux-4.19.y-for-next' of git://git.ti.com/linux-phy/kishons-ti... ti-linux-4.19.y-next-20190615
Merge branch 'ti-linux-4.19.y-for-next' of git://git.ti.com/linux-phy/kishons-ti-linux-kernel into ti-linux-4.19.y-next
TI-Feature: kishon_next
TI-Tree: git://git.ti.com/linux-phy/kishons-ti-linux-kernel.git
TI-Branch: ti-linux-4.19.y-for-next
* 'ti-linux-4.19.y-for-next' of git://git.ti.com/linux-phy/kishons-ti-linux-kernel:
ARM: dts: k2e-evm: enable PCIe on port 1
ARM: dts: keystone-k2e: Use the updated binding to describe PCIe in k2e
ARM: keystone: dts: add PCI serdes driver bindings
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: kishon_next
TI-Tree: git://git.ti.com/linux-phy/kishons-ti-linux-kernel.git
TI-Branch: ti-linux-4.19.y-for-next
* 'ti-linux-4.19.y-for-next' of git://git.ti.com/linux-phy/kishons-ti-linux-kernel:
ARM: dts: k2e-evm: enable PCIe on port 1
ARM: dts: keystone-k2e: Use the updated binding to describe PCIe in k2e
ARM: keystone: dts: add PCI serdes driver bindings
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
Merge branch 'rpmsg-ti-linux-4.19.y-next' of git://git.ti.com/rpmsg/rpmsg into ti-linux-4.19.y-next
TI-Feature: rpmsg_next
TI-Tree: git://git.ti.com/rpmsg/rpmsg.git
TI-Branch: rpmsg-ti-linux-4.19.y-next
* 'rpmsg-ti-linux-4.19.y-next' of git://git.ti.com/rpmsg/rpmsg: (27 commits)
remoteproc/k3-dsp: add support for IPC-only mode for all K3 DSPs
ti_config_fragments: v8_rpmsg: Enable K3 DSP remoteproc support
arm64: dts: ti: k3-j721e: Add an alias for C71x rproc node
arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C71x DSP
arm64: dts: ti: k3-j721e-main: Add C71x DSP node
remoteproc/k3-dsp: add support for C71x DSPs
remoteproc: add support for a new 64-bit trace version
remoteproc: introduce version element into resource type field
remoteproc: add 64-bit ELF loader support code
dt-bindings: remoteproc: k3-dsp: Update bindings for C71x DSPs
arm64: dts: ti: k3-j721e: Add aliases for C66x rproc nodes
arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C66 DSPs
arm64: dts: ti: k3-j721e-main: Add C66x DSP nodes
remoteproc/k3-dsp: add a remoteproc driver of K3 C66x DSPs
dt-bindings: remoteproc: Add bindings for DSP C66x clusters on TI K3 SoCs
remoteproc/k3-r5: add support for IPC-only mode for all R5Fs on J721E SoCs
ti_config_fragments: v8_rpmsg: Enable rpmsg client sample
TEMP: samples/rpmsg: add compatible to support J7ES PDK firmware images
arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS cores
arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for MAIN R5Fs
...
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: rpmsg_next
TI-Tree: git://git.ti.com/rpmsg/rpmsg.git
TI-Branch: rpmsg-ti-linux-4.19.y-next
* 'rpmsg-ti-linux-4.19.y-next' of git://git.ti.com/rpmsg/rpmsg: (27 commits)
remoteproc/k3-dsp: add support for IPC-only mode for all K3 DSPs
ti_config_fragments: v8_rpmsg: Enable K3 DSP remoteproc support
arm64: dts: ti: k3-j721e: Add an alias for C71x rproc node
arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C71x DSP
arm64: dts: ti: k3-j721e-main: Add C71x DSP node
remoteproc/k3-dsp: add support for C71x DSPs
remoteproc: add support for a new 64-bit trace version
remoteproc: introduce version element into resource type field
remoteproc: add 64-bit ELF loader support code
dt-bindings: remoteproc: k3-dsp: Update bindings for C71x DSPs
arm64: dts: ti: k3-j721e: Add aliases for C66x rproc nodes
arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C66 DSPs
arm64: dts: ti: k3-j721e-main: Add C66x DSP nodes
remoteproc/k3-dsp: add a remoteproc driver of K3 C66x DSPs
dt-bindings: remoteproc: Add bindings for DSP C66x clusters on TI K3 SoCs
remoteproc/k3-r5: add support for IPC-only mode for all R5Fs on J721E SoCs
ti_config_fragments: v8_rpmsg: Enable rpmsg client sample
TEMP: samples/rpmsg: add compatible to support J7ES PDK firmware images
arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS cores
arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for MAIN R5Fs
...
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
remoteproc/k3-dsp: add support for IPC-only mode for all K3 DSPs
Add support to the K3 DSP remoteproc driver to configure all the C66x
and C71x cores on J721E SoCs to be either in IPC-only mode or the
traditional remoteproc mode. The IPC-only mode expects that the remote
processors are already booted by the bootloader, and only perform the
minimum steps required to initialize and deinitialize the virtio IPC
transports. The remoteproc mode allows the kernel remoteproc driver to
do the regular load and boot and other device management operations for
a DSP.
The IPC-only mode for a DSP is detected and configured at driver probe
time by querying the System Firmware for the DSP power and reset state
and/or status and making sure that the DSP is indeed started by the
bootloaders, otherwise the device is configured for remoteproc mode.
Support for IPC-only mode is achieved through various flags in both
remoteproc core and the DSP remoteproc driver. The support in remoteproc
core for this is added in commit 20afed1b45bf ("remoteproc: add
infrastructure support to allow pre-loaded remoteprocs"). The support
requires that the firmware still be requested to process the resource
table for retrieving the virtio device and trace resource entries.
NOTE:
- The driver cannot configure a DSP for remoteproc mode by any
means without rebooting the kernel if that DSP has been started
by a bootloader.
- The resource table address retrieval logic can actually be done by
providing the data through device tree (thereby bypassing the need to
request the firmware), with the bootloader adding and/or updating the
necessary DT properties. Another option is to use a design-by-contract
approach of having the resource table located at a specific offset
within one of the memory regions. This will be optimized for in
the future.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add support to the K3 DSP remoteproc driver to configure all the C66x
and C71x cores on J721E SoCs to be either in IPC-only mode or the
traditional remoteproc mode. The IPC-only mode expects that the remote
processors are already booted by the bootloader, and only perform the
minimum steps required to initialize and deinitialize the virtio IPC
transports. The remoteproc mode allows the kernel remoteproc driver to
do the regular load and boot and other device management operations for
a DSP.
The IPC-only mode for a DSP is detected and configured at driver probe
time by querying the System Firmware for the DSP power and reset state
and/or status and making sure that the DSP is indeed started by the
bootloaders, otherwise the device is configured for remoteproc mode.
Support for IPC-only mode is achieved through various flags in both
remoteproc core and the DSP remoteproc driver. The support in remoteproc
core for this is added in commit 20afed1b45bf ("remoteproc: add
infrastructure support to allow pre-loaded remoteprocs"). The support
requires that the firmware still be requested to process the resource
table for retrieving the virtio device and trace resource entries.
NOTE:
- The driver cannot configure a DSP for remoteproc mode by any
means without rebooting the kernel if that DSP has been started
by a bootloader.
- The resource table address retrieval logic can actually be done by
providing the data through device tree (thereby bypassing the need to
request the firmware), with the bootloader adding and/or updating the
necessary DT properties. Another option is to use a design-by-contract
approach of having the resource table located at a specific offset
within one of the memory regions. This will be optimized for in
the future.
Signed-off-by: Suman Anna <s-anna@ti.com>
ti_config_fragments: v8_rpmsg: Enable K3 DSP remoteproc support
Add support to build the K3 DSP remoteproc driver to enable both the
C66x and the single C71x DSP processor subsystems present within the
MAIN domain on J721E SoCs. The other required remoteproc core, OMAP
Mailbox, virtio/rpmsg modules were already enabled. These are the
minimum required modules for enabling remoteproc and rpmsg communication
with the C66x and C71x remote processors on the J721E family of SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add support to build the K3 DSP remoteproc driver to enable both the
C66x and the single C71x DSP processor subsystems present within the
MAIN domain on J721E SoCs. The other required remoteproc core, OMAP
Mailbox, virtio/rpmsg modules were already enabled. These are the
minimum required modules for enabling remoteproc and rpmsg communication
with the C66x and C71x remote processors on the J721E family of SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
arm64: dts: ti: k3-j721e: Add an alias for C71x rproc node
Add the alias for the C71x remoteproc processor core present
within the MAIN domain and common to all the K3 J721E boards.
The alias uses the stem "rproc".
The rproc aliases can be overridden, if needed, in the respective
derivative board dts files.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add the alias for the C71x remoteproc processor core present
within the MAIN domain and common to all the K3 J721E boards.
The alias uses the stem "rproc".
The rproc aliases can be overridden, if needed, in the respective
derivative board dts files.
Signed-off-by: Suman Anna <s-anna@ti.com>
arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C71x DSP
Two carveout reserved memory nodes have been added for the lone C71x DSP
remote processor device present within the MAIN voltage domain for the TI
J721E EVM boards. These nodes are assigned to the respective rproc device
node as well. The first region will be used as the DMA pool for the rproc
device, and the second region will furnish the static carveout regions for
the firmware memory.
The current carveout addresses and sizes are defined statically for each
device. The C71x DSP processor does support a MMU called CMMU, but is not
currently supported and as such requires the exact memory used by the
firmware to be set-aside. The firmware images currently do not need any
RSC_CARVEOUT entries either in their resource tables to allocate the
memory for firmware memory segments.
The reserved memory nodes can be disabled later on if there is no use-case
defined to use the C71x DSP remoteproc processor.
Signed-off-by: Suman Anna <s-anna@ti.com>
Two carveout reserved memory nodes have been added for the lone C71x DSP
remote processor device present within the MAIN voltage domain for the TI
J721E EVM boards. These nodes are assigned to the respective rproc device
node as well. The first region will be used as the DMA pool for the rproc
device, and the second region will furnish the static carveout regions for
the firmware memory.
The current carveout addresses and sizes are defined statically for each
device. The C71x DSP processor does support a MMU called CMMU, but is not
currently supported and as such requires the exact memory used by the
firmware to be set-aside. The firmware images currently do not need any
RSC_CARVEOUT entries either in their resource tables to allocate the
memory for firmware memory segments.
The reserved memory nodes can be disabled later on if there is no use-case
defined to use the C71x DSP remoteproc processor.
Signed-off-by: Suman Anna <s-anna@ti.com>
arm64: dts: ti: k3-j721e-main: Add C71x DSP node
The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN
voltage domain containing the next-generation C711 CPU core. The
subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of
L2 configurable SRAM/Cache. This subsystem has a CMMU but is not
used currently. The inter-processor communication between the main
A72 cores and the C711 processor is achieved through shared memory
and a Mailbox. Add the DT node for this DSP processor sub-system
in the common k3-j721e-main.dtsi file.
NOTE:
The power-domains property is currently commented out until the
local resets integration is sorted out (not represented in SoC
data). Otherwise, the genpd integration tries to enable the DSP
(release from reset) even before the driver is probed.
Signed-off-by: Suman Anna <s-anna@ti.com>
The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN
voltage domain containing the next-generation C711 CPU core. The
subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of
L2 configurable SRAM/Cache. This subsystem has a CMMU but is not
used currently. The inter-processor communication between the main
A72 cores and the C711 processor is achieved through shared memory
and a Mailbox. Add the DT node for this DSP processor sub-system
in the common k3-j721e-main.dtsi file.
NOTE:
The power-domains property is currently commented out until the
local resets integration is sorted out (not represented in SoC
data). Otherwise, the genpd integration tries to enable the DSP
(release from reset) even before the driver is probed.
Signed-off-by: Suman Anna <s-anna@ti.com>
remoteproc/k3-dsp: add support for C71x DSPs
The Texas Instrument's K3 J721E SoCs have a newer next-generation
C71x DSP Subsystems in the MAIN voltage domain in addition to the
previous generation C66x DSP subsystems. The C71x DSP subsystem is
based on the TMS320C71x DSP CorePac module. The C71x CPU is a true
64-bit machine including 64-bit memory addressing and single-cycle
64-bit base arithmetic operations and supports vector signal processing
providing a significant lift in DSP processing power over C66x DSPs.
J721E SoCs use a C711 (a one-core 512-bit vector width CPU core) DSP
that is cache coherent with the A72 Arm cores.
Each subsystem has one or more Fixed/Floating-Point DSP CPUs, with 32 KB
of L1P Cache, 48 KB of L1D SRAM that can be configured and partitioned as
either RAM and/or Cache, and 512 KB of L2 SRAM configurable as either RAM
and/or Cache. The CorePac also includes a Matrix Multiplication Accelerator
(MMA), a Stream Engine (SE) and a C71x Memory Management Unit (CMMU), an
Interrupt Controller (INTC) and a Powerdown Management Unit (PMU) modules.
Update the existing K3 DSP remoteproc driver to add support for this C71x
DSP subsystem. The firmware loading support is provided by using the newly
added 64-bit ELF loader functions, and is limited to images using only
external DDR memory at the moment. The CMMU is also not supported to begin
with, and the driver is designed to treat the MMU as if it is in bypass
mode.
The driver expects the following firmware name to be used for the lone
C71x DSP core on J721E SoCs:
j7-c71_0-fw
Signed-off-by: Suman Anna <s-anna@ti.com>
The Texas Instrument's K3 J721E SoCs have a newer next-generation
C71x DSP Subsystems in the MAIN voltage domain in addition to the
previous generation C66x DSP subsystems. The C71x DSP subsystem is
based on the TMS320C71x DSP CorePac module. The C71x CPU is a true
64-bit machine including 64-bit memory addressing and single-cycle
64-bit base arithmetic operations and supports vector signal processing
providing a significant lift in DSP processing power over C66x DSPs.
J721E SoCs use a C711 (a one-core 512-bit vector width CPU core) DSP
that is cache coherent with the A72 Arm cores.
Each subsystem has one or more Fixed/Floating-Point DSP CPUs, with 32 KB
of L1P Cache, 48 KB of L1D SRAM that can be configured and partitioned as
either RAM and/or Cache, and 512 KB of L2 SRAM configurable as either RAM
and/or Cache. The CorePac also includes a Matrix Multiplication Accelerator
(MMA), a Stream Engine (SE) and a C71x Memory Management Unit (CMMU), an
Interrupt Controller (INTC) and a Powerdown Management Unit (PMU) modules.
Update the existing K3 DSP remoteproc driver to add support for this C71x
DSP subsystem. The firmware loading support is provided by using the newly
added 64-bit ELF loader functions, and is limited to images using only
external DDR memory at the moment. The CMMU is also not supported to begin
with, and the driver is designed to treat the MMU as if it is in bypass
mode.
The driver expects the following firmware name to be used for the lone
C71x DSP core on J721E SoCs:
j7-c71_0-fw
Signed-off-by: Suman Anna <s-anna@ti.com>
remoteproc: add support for a new 64-bit trace version
Introduce a new trace entry resource structure that accommodates
a 64-bit device address to support 64-bit processors. This is to
be used using an overloaded version value of 1 in the upper 32-bits
of the previous resource type field. The new resource still uses
32-bits for the length field (followed by a 32-bit reserved field,
so can be updated in the future), which is a sufficiently large
trace buffer size. A 32-bit padding field also had to be added
to align the device address on a 64-bit boundary, and match the
usage on the firmware side.
The remoteproc debugfs logic also has been adjusted accordingly.
Signed-off-by: Suman Anna <s-anna@ti.com>
Introduce a new trace entry resource structure that accommodates
a 64-bit device address to support 64-bit processors. This is to
be used using an overloaded version value of 1 in the upper 32-bits
of the previous resource type field. The new resource still uses
32-bits for the length field (followed by a 32-bit reserved field,
so can be updated in the future), which is a sufficiently large
trace buffer size. A 32-bit padding field also had to be added
to align the device address on a 64-bit boundary, and match the
usage on the firmware side.
The remoteproc debugfs logic also has been adjusted accordingly.
Signed-off-by: Suman Anna <s-anna@ti.com>
remoteproc: introduce version element into resource type field
The current remoteproc core has supported only 32-bit remote
processors and as such some of the current resource structures
may not scale well for 64-bit remote processors, and would
require new versions of resource types. Each resource is currently
identified by a 32-bit type field. Introduce the concept of version
for these resource types by overloading this 32-bit type field
into two 16-bit version and type fields with the existing resources
behaving as version 0 thereby providing backward compatibility.
The version field is passed as an additional argument to each of
the handler functions, and all the existing handlers are updated
accordingly. Each specific handler will be updated on a need basis
when a new version of the resource type is added.
An alternate way would be to introduce the new types as completely
new resource types which would require additional customization of
the resource handlers based on the 32-bit or 64-bit mode of a remote
processor, and introduction of an additional mode flag to the rproc
structure.
Signed-off-by: Suman Anna <s-anna@ti.com>
The current remoteproc core has supported only 32-bit remote
processors and as such some of the current resource structures
may not scale well for 64-bit remote processors, and would
require new versions of resource types. Each resource is currently
identified by a 32-bit type field. Introduce the concept of version
for these resource types by overloading this 32-bit type field
into two 16-bit version and type fields with the existing resources
behaving as version 0 thereby providing backward compatibility.
The version field is passed as an additional argument to each of
the handler functions, and all the existing handlers are updated
accordingly. Each specific handler will be updated on a need basis
when a new version of the resource type is added.
An alternate way would be to introduce the new types as completely
new resource types which would require additional customization of
the resource handlers based on the 32-bit or 64-bit mode of a remote
processor, and introduction of an additional mode flag to the rproc
structure.
Signed-off-by: Suman Anna <s-anna@ti.com>
remoteproc: add 64-bit ELF loader support code
The current remoteproc core has supported only 32-bit remote
processors and provides a default 32-bit ELF loader code for
parsing and loading the corresponding firmwares, irrespective
of its native 32-bit or 64-bit Linux OS. Add a new remoteproc
core file that provides equivalent loader functionality to
support 64-bit remote processors using 64-bit ELF firmwares.
The current file is created by using the 32-bit ELF loader
code as a foundation and using the appropriate 64-bit structures.
This is done in a separate file to not disturb the current
32-bit loader code, and without introducing additional changes
into the remoteproc core (Both 32-bit and 64-bit firmwares needs
to be supported irrespective of the 32-bit/64-bit Linux OS, which
requires some runtime flag detection rather than a pre-compiler
detection). The remoteproc platform drivers are expected to
overwrite the required rproc_ops with the 64-bit versions.
NOTE:
The rproc_elf64_get_boot_addr() currently returns a 32-bit entry
point assuming all the higher-bit addresses as zero, to reuse the
rproc ops. This is a temporary solution and needs to be fixed
up in the future.
Signed-off-by: Suman Anna <s-anna@ti.com>
The current remoteproc core has supported only 32-bit remote
processors and provides a default 32-bit ELF loader code for
parsing and loading the corresponding firmwares, irrespective
of its native 32-bit or 64-bit Linux OS. Add a new remoteproc
core file that provides equivalent loader functionality to
support 64-bit remote processors using 64-bit ELF firmwares.
The current file is created by using the 32-bit ELF loader
code as a foundation and using the appropriate 64-bit structures.
This is done in a separate file to not disturb the current
32-bit loader code, and without introducing additional changes
into the remoteproc core (Both 32-bit and 64-bit firmwares needs
to be supported irrespective of the 32-bit/64-bit Linux OS, which
requires some runtime flag detection rather than a pre-compiler
detection). The remoteproc platform drivers are expected to
overwrite the required rproc_ops with the 64-bit versions.
NOTE:
The rproc_elf64_get_boot_addr() currently returns a 32-bit entry
point assuming all the higher-bit addresses as zero, to reuse the
rproc ops. This is a temporary solution and needs to be fixed
up in the future.
Signed-off-by: Suman Anna <s-anna@ti.com>
dt-bindings: remoteproc: k3-dsp: Update bindings for C71x DSPs
Some Texas Instruments K3 family of SoCs have one of more newer
generation TMS320C71x CorePac processor subsystem in addition to
the existing TMS320C66x CorePac processor subsystems. Update the
device tree bindings document for the C71x DSP devices.
The example is also updated to show the single C71 DSP present
on J721E SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
Some Texas Instruments K3 family of SoCs have one of more newer
generation TMS320C71x CorePac processor subsystem in addition to
the existing TMS320C66x CorePac processor subsystems. Update the
device tree bindings document for the C71x DSP devices.
The example is also updated to show the single C71 DSP present
on J721E SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
arm64: dts: ti: k3-j721e: Add aliases for C66x rproc nodes
Add aliases for all the C66x remoteproc processor cores present
within the MAIN domain and common to all the K3 J721E boards.
The aliases uses the stem "rproc".
The aliases can be overridden, if needed, in the respective
derivative board dts files.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add aliases for all the C66x remoteproc processor cores present
within the MAIN domain and common to all the K3 J721E boards.
The aliases uses the stem "rproc".
The aliases can be overridden, if needed, in the respective
derivative board dts files.
Signed-off-by: Suman Anna <s-anna@ti.com>
arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C66 DSPs
Two carveout reserved memory nodes each have been added for each of the
C66x DSP remote processor devices present within the MAIN voltage domain
for the TI J721E EVM boards. These nodes are assigned to the respective
rproc device nodes as well. The first region will be used as the DMA pool
for the rproc devices, and the second region will furnish the static
carveout regions for the firmware memory.
The minimum granularity on the Cache settings on C66x DSP cores is 16 MB,
so the DMA memory regions are chosen such that they are in separate 16 MB
regions for each DSP, while reserving a total of 16 MB for each DSP and
not changing the overall DSP remoteproc carveouts.
The current carveout addresses and sizes are defined statically for each
device. The C66x DSP processors do not have an MMU, and as such require the
exact memory used by the firmwares to be set-aside. The firmware images
do not require any RSC_CARVEOUT entries in their resource tables to
allocate the memory for firmware memory segments.
The reserved memory nodes can be disabled later on if there is no use-case
defined to use the corresponding remote processor.
Signed-off-by: Suman Anna <s-anna@ti.com>
Two carveout reserved memory nodes each have been added for each of the
C66x DSP remote processor devices present within the MAIN voltage domain
for the TI J721E EVM boards. These nodes are assigned to the respective
rproc device nodes as well. The first region will be used as the DMA pool
for the rproc devices, and the second region will furnish the static
carveout regions for the firmware memory.
The minimum granularity on the Cache settings on C66x DSP cores is 16 MB,
so the DMA memory regions are chosen such that they are in separate 16 MB
regions for each DSP, while reserving a total of 16 MB for each DSP and
not changing the overall DSP remoteproc carveouts.
The current carveout addresses and sizes are defined statically for each
device. The C66x DSP processors do not have an MMU, and as such require the
exact memory used by the firmwares to be set-aside. The firmware images
do not require any RSC_CARVEOUT entries in their resource tables to
allocate the memory for firmware memory segments.
The reserved memory nodes can be disabled later on if there is no use-case
defined to use the corresponding remote processor.
Signed-off-by: Suman Anna <s-anna@ti.com>
arm64: dts: ti: k3-j721e-main: Add C66x DSP nodes
The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs)
in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP
Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional
288 KB of L2 configurable SRAM/Cache. These subsystems do not have
an MMU but contain a Region Address Translator (RAT) sub-module for
translating 32-bit processor addresses into larger bus addresses.
The inter-processor communication between the main A72 cores and
these processors is achieved through shared memory and Mailboxes.
Add the DT nodes for these DSP processor sub-systems in the common
k3-j721e-main.dtsi file.
NOTE:
The power-domains property is currently commented out until the local
resets integration is sorted out (not represented in SoC data). Otherwise,
the genpd integration tries to enable the DSP (release from reset) even
before the driver is probed.
Signed-off-by: Suman Anna <s-anna@ti.com>
The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs)
in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP
Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional
288 KB of L2 configurable SRAM/Cache. These subsystems do not have
an MMU but contain a Region Address Translator (RAT) sub-module for
translating 32-bit processor addresses into larger bus addresses.
The inter-processor communication between the main A72 cores and
these processors is achieved through shared memory and Mailboxes.
Add the DT nodes for these DSP processor sub-systems in the common
k3-j721e-main.dtsi file.
NOTE:
The power-domains property is currently commented out until the local
resets integration is sorted out (not represented in SoC data). Otherwise,
the genpd integration tries to enable the DSP (release from reset) even
before the driver is probed.
Signed-off-by: Suman Anna <s-anna@ti.com>
remoteproc/k3-dsp: add a remoteproc driver of K3 C66x DSPs
The Texas Instrument's K3 J721E SoCs have two C66x DSP Subsystems in MAIN
voltage domain that are based on the TI's standard TMS320C66x DSP CorePac
module. Each subsystem has a Fixed/Floating-Point DSP CPU, with 32 KB each
of L1P & L1D SRAMs that can be configured and partitioned as either RAM
and/or Cache, and 288 KB of L2 SRAM with 256 KB of memory configurable as
either RAM and/or Cache. The CorePac also includes an Internal DMA (IDMA),
External Memory Controller (EMC), Extended Memory Controller (XMC) with a
Region Address Translator (RAT) unit for 32-bit to 48-bit address
extension/translations, an Interrupt Controller (INTC) and a Powerdown
Controller (PDC).
A new remoteproc module is added to perform the device management of
these DSP devices. The support is limited to images using only external
DDR memory at the moment, the loading support to internal memories and
any on-chip RAM memories will be added in the future. RAT support is also
left for a future patch, and as such the reserved memory carveout regions
are all expected to be using memory regions within the first 2 GB. Error
Recovery and Power Management features are not currently supported.
The C66x remote processors do not have an MMU, and so require fixed memory
carveout regions matching the firmware image addresses. Support for this
is provided by mandating multiple memory regions to be attached to the
remoteproc device. The first memory region will be used to serve as the
DMA pool for all dynamic allocations like the vrings and vring buffers.
The remaining memory regions are mapped into the kernel at device probe
time, and are used to provide address translations for firmware image
segments without the need for any RSC_CARVEOUT entries. Any firmware
image using memory outside of the supplied reserved memory carveout
regions will be errored out.
The driver uses various TI-SCI interfaces to talk to the System Controller
(DMSC) for managing configuration, power and reset management of these
cores. IPC between the A72 cores and the DSP cores is supported through
the virtio rpmsg stack using shared memory and OMAP Mailboxes.
The driver expects the following firmware names to be used for these C66x
cores:
C66_0: j7-c66_0-fw
C66_1: j7-c66_1-fw
NOTE:
The local reset code is currently commented out, the current DDR support
is not effected by this. This needs to be sorted out before the support
for loading into DSP internal memories can be enabled.
Signed-off-by: Suman Anna <s-anna@ti.com>
The Texas Instrument's K3 J721E SoCs have two C66x DSP Subsystems in MAIN
voltage domain that are based on the TI's standard TMS320C66x DSP CorePac
module. Each subsystem has a Fixed/Floating-Point DSP CPU, with 32 KB each
of L1P & L1D SRAMs that can be configured and partitioned as either RAM
and/or Cache, and 288 KB of L2 SRAM with 256 KB of memory configurable as
either RAM and/or Cache. The CorePac also includes an Internal DMA (IDMA),
External Memory Controller (EMC), Extended Memory Controller (XMC) with a
Region Address Translator (RAT) unit for 32-bit to 48-bit address
extension/translations, an Interrupt Controller (INTC) and a Powerdown
Controller (PDC).
A new remoteproc module is added to perform the device management of
these DSP devices. The support is limited to images using only external
DDR memory at the moment, the loading support to internal memories and
any on-chip RAM memories will be added in the future. RAT support is also
left for a future patch, and as such the reserved memory carveout regions
are all expected to be using memory regions within the first 2 GB. Error
Recovery and Power Management features are not currently supported.
The C66x remote processors do not have an MMU, and so require fixed memory
carveout regions matching the firmware image addresses. Support for this
is provided by mandating multiple memory regions to be attached to the
remoteproc device. The first memory region will be used to serve as the
DMA pool for all dynamic allocations like the vrings and vring buffers.
The remaining memory regions are mapped into the kernel at device probe
time, and are used to provide address translations for firmware image
segments without the need for any RSC_CARVEOUT entries. Any firmware
image using memory outside of the supplied reserved memory carveout
regions will be errored out.
The driver uses various TI-SCI interfaces to talk to the System Controller
(DMSC) for managing configuration, power and reset management of these
cores. IPC between the A72 cores and the DSP cores is supported through
the virtio rpmsg stack using shared memory and OMAP Mailboxes.
The driver expects the following firmware names to be used for these C66x
cores:
C66_0: j7-c66_0-fw
C66_1: j7-c66_1-fw
NOTE:
The local reset code is currently commented out, the current DDR support
is not effected by this. This needs to be sorted out before the support
for loading into DSP internal memories can be enabled.
Signed-off-by: Suman Anna <s-anna@ti.com>
dt-bindings: remoteproc: Add bindings for DSP C66x clusters on TI K3 SoCs
Some Texas Instruments K3 family of SoCs have one of more Digital Signal
Processor (DSP) subsystems that are comprised of either a TMS320C66x
CorePac and/or a next-generation TMS320C71x CorePac processor subsystem.
Add the device tree bindings document for the C66x DSP devices on these
SoCs. The added example illustrates the DT nodes for the first C66x DSP
device present on the K3 J721E family of SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
Some Texas Instruments K3 family of SoCs have one of more Digital Signal
Processor (DSP) subsystems that are comprised of either a TMS320C66x
CorePac and/or a next-generation TMS320C71x CorePac processor subsystem.
Add the device tree bindings document for the C66x DSP devices on these
SoCs. The added example illustrates the DT nodes for the first C66x DSP
device present on the K3 J721E family of SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
remoteproc/k3-r5: add support for IPC-only mode for all R5Fs on J721E SoCs
Add support to the K3 R5F remoteproc driver to configure all the R5F cores
on J721E SoCs to be either in IPC-only mode or the traditional remoteproc
mode. The IPC-only mode expects that the remote processors are already
booted by the bootloader, and only perform the minimum steps required to
initialize and deinitialize the virtio IPC transports. The remoteproc mode
allows the kernel remoteproc driver to do the regular load and boot and
other device management operations for a R5F core.
The IPC-only mode for a R5F core is detected and configured at driver
probe time by querying the System Firmware for the R5F power and reset
state and/or status and making sure that the R5F core is indeed started
by the bootloaders, otherwise the device is configured for remoteproc
mode.
Support for IPC-only mode is achieved through various flags in both
remoteproc core and the K3 R5F remoteproc driver. The support in
remoteproc core for this is added in commit 20afed1b45bf ("remoteproc:
add infrastructure support to allow pre-loaded remoteprocs"). The support
requires that the firmware still be requested to process the resource
table for retrieving the virtio device and trace resource entries.
NOTE:
- The driver cannot configure a R5F core for remoteproc mode by any
means without rebooting the kernel if that R5F core has been started
by a bootloader.
- The IPC-only mode support is currently limited to only J721E SoCs.
Functionality on AM65x SoCs will be added in the future.
- The resource table address retrieval logic can actually be done by
providing the data through device tree (thereby bypassing the need to
request the firmware), with the bootloader adding and/or updating the
necessary DT properties. Another option is to use a design-by-contract
approach of having the resource table located at a specific offset
within one of the memory regions. This will be optimized for in
the future.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add support to the K3 R5F remoteproc driver to configure all the R5F cores
on J721E SoCs to be either in IPC-only mode or the traditional remoteproc
mode. The IPC-only mode expects that the remote processors are already
booted by the bootloader, and only perform the minimum steps required to
initialize and deinitialize the virtio IPC transports. The remoteproc mode
allows the kernel remoteproc driver to do the regular load and boot and
other device management operations for a R5F core.
The IPC-only mode for a R5F core is detected and configured at driver
probe time by querying the System Firmware for the R5F power and reset
state and/or status and making sure that the R5F core is indeed started
by the bootloaders, otherwise the device is configured for remoteproc
mode.
Support for IPC-only mode is achieved through various flags in both
remoteproc core and the K3 R5F remoteproc driver. The support in
remoteproc core for this is added in commit 20afed1b45bf ("remoteproc:
add infrastructure support to allow pre-loaded remoteprocs"). The support
requires that the firmware still be requested to process the resource
table for retrieving the virtio device and trace resource entries.
NOTE:
- The driver cannot configure a R5F core for remoteproc mode by any
means without rebooting the kernel if that R5F core has been started
by a bootloader.
- The IPC-only mode support is currently limited to only J721E SoCs.
Functionality on AM65x SoCs will be added in the future.
- The resource table address retrieval logic can actually be done by
providing the data through device tree (thereby bypassing the need to
request the firmware), with the bootloader adding and/or updating the
necessary DT properties. Another option is to use a design-by-contract
approach of having the resource table located at a specific offset
within one of the memory regions. This will be optimized for in
the future.
Signed-off-by: Suman Anna <s-anna@ti.com>
ti_config_fragments: v8_rpmsg: Enable rpmsg client sample
Enable the in-kernel rpmsg client sample module so that it can be
used as the unit-test for verifying rpmsg communication with the
various remote processors present on J721E SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
Enable the in-kernel rpmsg client sample module so that it can be
used as the unit-test for verifying rpmsg communication with the
various remote processors present on J721E SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
TEMP: samples/rpmsg: add compatible to support J7ES PDK firmware images
Add a specific compatible "ti.ipc4.ping-pong" to the rpmsg client device
list so that the rpmsg client sample device published and used by the J7ES
PDK IPC sample firmware images can properly probe the rpmsg_client_sample
driver and provide a means to unit-test the rpmsg communication with the
various remote processors on J7ES SoCs.
This is needed because the current firmwares do not have support for the
enhanced name service announcement mechanism, and are not using the
standard "rpmsg-client-sample" device.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add a specific compatible "ti.ipc4.ping-pong" to the rpmsg client device
list so that the rpmsg client sample device published and used by the J7ES
PDK IPC sample firmware images can properly probe the rpmsg_client_sample
driver and provide a means to unit-test the rpmsg communication with the
various remote processors on J7ES SoCs.
This is needed because the current firmwares do not have support for the
enhanced name service announcement mechanism, and are not using the
standard "rpmsg-client-sample" device.
Signed-off-by: Suman Anna <s-anna@ti.com>
arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS cores
Add a reserved memory node to reserve a portion of the DDR memory to be
used for performing inter-processor communication between all the remote
processors running RTOS on the TI J721E EVM boards. 28 MB of memory is
reserved for this purpose, and this accounts for all the vrings and vring
buffers between all the possible pairs of remote processors.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add a reserved memory node to reserve a portion of the DDR memory to be
used for performing inter-processor communication between all the remote
processors running RTOS on the TI J721E EVM boards. 28 MB of memory is
reserved for this purpose, and this accounts for all the vrings and vring
buffers between all the possible pairs of remote processors.
Signed-off-by: Suman Anna <s-anna@ti.com>
arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for MAIN R5Fs
Two carveout reserved memory nodes each have been added for each of the
R5F remote processor devices within MAIN domain on the TI J721E EVM
boards. These nodes are assigned to the respective rproc device nodes as
well. The first region will be used as the DMA pool for the rproc devices,
and the second region will furnish the static carveout regions for the
firmware memory.
The current carveout addresses and sizes are defined statically for each
device. The R5F processors do not have an MMU, and as such require the
exact memory used by the firmwares to be set-aside. The firmware images do
not require any RSC_CARVEOUT entries in their resource tables to allocate
the memory for firmware memory segments.
Note that the R5F1 carveouts are needed only if the R5F cluster is running
in Split (non-LockStep) mode. The reserved memory nodes can be disabled
later on if there is no use-case defined to use the corresponding remote
processor.
Signed-off-by: Suman Anna <s-anna@ti.com>
Two carveout reserved memory nodes each have been added for each of the
R5F remote processor devices within MAIN domain on the TI J721E EVM
boards. These nodes are assigned to the respective rproc device nodes as
well. The first region will be used as the DMA pool for the rproc devices,
and the second region will furnish the static carveout regions for the
firmware memory.
The current carveout addresses and sizes are defined statically for each
device. The R5F processors do not have an MMU, and as such require the
exact memory used by the firmwares to be set-aside. The firmware images do
not require any RSC_CARVEOUT entries in their resource tables to allocate
the memory for firmware memory segments.
Note that the R5F1 carveouts are needed only if the R5F cluster is running
in Split (non-LockStep) mode. The reserved memory nodes can be disabled
later on if there is no use-case defined to use the corresponding remote
processor.
Signed-off-by: Suman Anna <s-anna@ti.com>
arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for MCU R5Fs
Two carveout reserved memory nodes each have been added for each of the
R5F remote processor devices within MCU domain on the TI J721E EVM boards.
These nodes are assigned to the respective rproc device nodes as well.
The first region will be used as the DMA pool for the rproc devices,
and the second region will furnish the static carveout regions for the
firmware memory.
The current carveout addresses and sizes are defined statically for each
device. The R5F processors do not have an MMU, and as such require the
exact memory used by the firmwares to be set-aside. The firmware images
do not require any RSC_CARVEOUT entries in their resource tables to
allocate the memory for firmware memory segments.
Note that the R5F1 carveouts are needed only if the R5F cluster is running
in Split (non-LockStep) mode. The reserved memory nodes can be disabled
later on if there is no use-case defined to use the corresponding
remote processor.
Signed-off-by: Suman Anna <s-anna@ti.com>
Two carveout reserved memory nodes each have been added for each of the
R5F remote processor devices within MCU domain on the TI J721E EVM boards.
These nodes are assigned to the respective rproc device nodes as well.
The first region will be used as the DMA pool for the rproc devices,
and the second region will furnish the static carveout regions for the
firmware memory.
The current carveout addresses and sizes are defined statically for each
device. The R5F processors do not have an MMU, and as such require the
exact memory used by the firmwares to be set-aside. The firmware images
do not require any RSC_CARVEOUT entries in their resource tables to
allocate the memory for firmware memory segments.
Note that the R5F1 carveouts are needed only if the R5F cluster is running
in Split (non-LockStep) mode. The reserved memory nodes can be disabled
later on if there is no use-case defined to use the corresponding
remote processor.
Signed-off-by: Suman Anna <s-anna@ti.com>
arm64: dts: ti: k3-j721e: Add aliases for R5F rproc nodes
Add aliases for all the R5F remoteproc processor cores present
within the MCU domain and MAIN domains and common to all the K3
J721E boards. The aliases uses the stem "rproc". Note that each
of the R5F1 cores and their corresponding aliases are uniquely
identified and used only if the corresponding R5F cluster/subsystem
is running in Split (non-LockStep) mode.
The aliases can be overridden, if needed, in the respective
derivative board dts files.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add aliases for all the R5F remoteproc processor cores present
within the MCU domain and MAIN domains and common to all the K3
J721E boards. The aliases uses the stem "rproc". Note that each
of the R5F1 cores and their corresponding aliases are uniquely
identified and used only if the corresponding R5F cluster/subsystem
is running in Split (non-LockStep) mode.
The aliases can be overridden, if needed, in the respective
derivative board dts files.
Signed-off-by: Suman Anna <s-anna@ti.com>
arm64: dts: ti: k3-j721e-main: Configure MAIN R5FSS0 for Split-mode
Switch the MAIN R5FSS0 cluster to be configured for Split-mode as the
default so that two different applications can be run on each of the
R5F cores in performance mode.
Signed-off-by: Suman Anna <s-anna@ti.com>
Switch the MAIN R5FSS0 cluster to be configured for Split-mode as the
default so that two different applications can be run on each of the
R5F cores in performance mode.
Signed-off-by: Suman Anna <s-anna@ti.com>
arm64: dts: ti: k3-j721e-main: Add MAIN domain R5F cluster nodes
The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within
the MCU domain, and the remaining two clusters are present in the
MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be
configured at boot time to be either run in a LockStep mode or in
an Asymmetric Multi Processing (AMP) fashion in Split-mode. These
subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
memories for each core split between two banks - ATCM and BTCM
(further interleaved into two banks). There are some IP integration
differences from standard Arm R5 clusters such as the absence of
an ACP port, presence of an additional TI-specific Region Address
Translater (RAT) module for translating 32-bit CPU addresses into
larger system bus addresses etc.
Add the DT nodes for these two MAIN domain R5F cluster/subsystems,
the two R5F cores are each added as child nodes to the corresponding
main cluster node. Both the clusters are configured to run in LockStep
mode by default, with the ATCMs enabled to allow the R5 cores to execute
code from DDR with boot-strapping code from ATCM. The inter-processor
communication between the main A72 cores and these processors is
achieved through shared memory and Mailboxes.
Signed-off-by: Suman Anna <s-anna@ti.com>
The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within
the MCU domain, and the remaining two clusters are present in the
MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be
configured at boot time to be either run in a LockStep mode or in
an Asymmetric Multi Processing (AMP) fashion in Split-mode. These
subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
memories for each core split between two banks - ATCM and BTCM
(further interleaved into two banks). There are some IP integration
differences from standard Arm R5 clusters such as the absence of
an ACP port, presence of an additional TI-specific Region Address
Translater (RAT) module for translating 32-bit CPU addresses into
larger system bus addresses etc.
Add the DT nodes for these two MAIN domain R5F cluster/subsystems,
the two R5F cores are each added as child nodes to the corresponding
main cluster node. Both the clusters are configured to run in LockStep
mode by default, with the ATCMs enabled to allow the R5 cores to execute
code from DDR with boot-strapping code from ATCM. The inter-processor
communication between the main A72 cores and these processors is
achieved through shared memory and Mailboxes.
Signed-off-by: Suman Anna <s-anna@ti.com>
arm64: dts: ti: k3-j721e-mcu: Add MCU domain R5F cluster node
The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within
the MCU domain, and the remaining two clusters are present in the
MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be
configured at boot time to be either run in a LockStep mode or in
an Asymmetric Multi Processing (AMP) fashion in Split-mode. These
subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
memories for each core split between two banks - ATCM and BTCM
(further interleaved into two banks). There are some IP integration
differences from standard Arm R5 clusters such as the absence of
an ACP port, presence of an additional TI-specific Region Address
Translater (RAT) module for translating 32-bit CPU addresses into
larger system bus addresses etc.
Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in LockStep mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.
Signed-off-by: Suman Anna <s-anna@ti.com>
The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within
the MCU domain, and the remaining two clusters are present in the
MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be
configured at boot time to be either run in a LockStep mode or in
an Asymmetric Multi Processing (AMP) fashion in Split-mode. These
subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
memories for each core split between two banks - ATCM and BTCM
(further interleaved into two banks). There are some IP integration
differences from standard Arm R5 clusters such as the absence of
an ACP port, presence of an additional TI-specific Region Address
Translater (RAT) module for translating 32-bit CPU addresses into
larger system bus addresses etc.
Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in LockStep mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.
Signed-off-by: Suman Anna <s-anna@ti.com>
remoteproc/k3-r5: extend support to R5 clusters on J721E SoCs
The K3 J721E SoCs typically have three dual-core Arm R5F clusters/
subsystems with 2 R5F cores each. One cluster is present within the
MCU voltage domain (MCU_R5FSS0), and the remaining two clusters are
present in the MAIN voltage domain (MAIN_R5FSS0 and MAIN_R5FSS1).
Extend the support to these clusters in the K3 R5F remoteproc driver
using the J721E specific compatibles. The integration of these
clusters on J721E SoC is slightly different from those on AM65x SoCs
in that these IPs do support a local reset. The current code sequence
already supports these.
The default names for the firmware images are fixed for each processor
and are expected to be as follows:
MCU R5FSS0 Core0: j7-mcu-r5f0_0-fw (both in LockStep and Split modes)
MCU R5FSS0 Core1: j7-mcu-r5f0_1-fw (needed only in Split mode)
MAIN R5FSS0 Core0: j7-main-r5f0_0-fw (both in LockStep and Split modes)
MAIN R5FSS0 Core1: j7-main-r5f0_1-fw (needed only in Split mode)
MAIN R5FSS1 Core0: j7-main-r5f1_0-fw (both in LockStep and Split modes)
MAIN R5FSS1 Core1: j7-main-r5f1_1-fw (needed only in Split mode)
Signed-off-by: Suman Anna <s-anna@ti.com>
The K3 J721E SoCs typically have three dual-core Arm R5F clusters/
subsystems with 2 R5F cores each. One cluster is present within the
MCU voltage domain (MCU_R5FSS0), and the remaining two clusters are
present in the MAIN voltage domain (MAIN_R5FSS0 and MAIN_R5FSS1).
Extend the support to these clusters in the K3 R5F remoteproc driver
using the J721E specific compatibles. The integration of these
clusters on J721E SoC is slightly different from those on AM65x SoCs
in that these IPs do support a local reset. The current code sequence
already supports these.
The default names for the firmware images are fixed for each processor
and are expected to be as follows:
MCU R5FSS0 Core0: j7-mcu-r5f0_0-fw (both in LockStep and Split modes)
MCU R5FSS0 Core1: j7-mcu-r5f0_1-fw (needed only in Split mode)
MAIN R5FSS0 Core0: j7-main-r5f0_0-fw (both in LockStep and Split modes)
MAIN R5FSS0 Core1: j7-main-r5f0_1-fw (needed only in Split mode)
MAIN R5FSS1 Core0: j7-main-r5f1_0-fw (both in LockStep and Split modes)
MAIN R5FSS1 Core1: j7-main-r5f1_1-fw (needed only in Split mode)
Signed-off-by: Suman Anna <s-anna@ti.com>
dt-bindings: remoteproc: k3-r5f: Update bindings for J721E SoCs
The K3 J721E SoCs typically have three dual-core Arm R5F clusters/
subsystems with 2 R5F cores each. The clusters are split between
multiple voltage domains as well.
Update the K3 R5F remoteproc bindings with the compatible info
relevant to the above R5F clusters/subsystems on K3 J721E SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
The K3 J721E SoCs typically have three dual-core Arm R5F clusters/
subsystems with 2 R5F cores each. The clusters are split between
multiple voltage domains as well.
Update the K3 R5F remoteproc bindings with the compatible info
relevant to the above R5F clusters/subsystems on K3 J721E SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
Merge branch 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree into ti-linux-4.19.y
TI-Feature: platform_base
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree:
ti_config_fragments: v8_baseport: Enable REGULATOR_FIXED_VOLTAGE config
ti_config_fragments: v8_baseport.cfg: Add TPS65917(PALMAS) Configs
arm64: dts: ti: k3-j721e-som-p0: Add tps65917 PMIC node
Signed-off-by: Dan Murphy <dmurphy@ti.com>
# Conflicts:
# arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
TI-Feature: platform_base
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree:
ti_config_fragments: v8_baseport: Enable REGULATOR_FIXED_VOLTAGE config
ti_config_fragments: v8_baseport.cfg: Add TPS65917(PALMAS) Configs
arm64: dts: ti: k3-j721e-som-p0: Add tps65917 PMIC node
Signed-off-by: Dan Murphy <dmurphy@ti.com>
# Conflicts:
# arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
Merge branch 'audio_display-ti-linux-4.19.y' of git.ti.com:~jyrisarha/ti-linux-kernel/jyrisarhas-audio-video-linux-feature-tree into ti-linux-4.19.y
TI-Feature: audio-display
TI-Tree: git@git.ti.com:~jyrisarha/ti-linux-kernel/jyrisarhas-audio-video-linux-feature-tree.git
TI-Branch: audio_display-ti-linux-4.19.y
* 'audio_display-ti-linux-4.19.y' of git.ti.com:~jyrisarha/ti-linux-kernel/jyrisarhas-audio-video-linux-feature-tree:
arm64: dts: ti: j721e-common-proc-board: Analog audio support
ASoC: ti: davinci-mcasp: Support for auxclk-fs-ratio
bindings: sound: davinci-mcasp: Add support for optional auxclk-fs-ratio
arm64: dts: ti: k3-j721e-main: Add McASP nodes
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: audio-display
TI-Tree: git@git.ti.com:~jyrisarha/ti-linux-kernel/jyrisarhas-audio-video-linux-feature-tree.git
TI-Branch: audio_display-ti-linux-4.19.y
* 'audio_display-ti-linux-4.19.y' of git.ti.com:~jyrisarha/ti-linux-kernel/jyrisarhas-audio-video-linux-feature-tree:
arm64: dts: ti: j721e-common-proc-board: Analog audio support
ASoC: ti: davinci-mcasp: Support for auxclk-fs-ratio
bindings: sound: davinci-mcasp: Add support for optional auxclk-fs-ratio
arm64: dts: ti: k3-j721e-main: Add McASP nodes
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
Merge branch 'connectivity-ti-linux-4.19.y' of git.ti.com:connectivity-integration-tree/connectivity-ti-linux-kernel into platform-ti-linux-4.19.y
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
ti_config_fragments: v8_baseport: Enable REGULATOR_FIXED_VOLTAGE config
Enable REGULATOR_FIXED_VOLTAGE config needed for mmc.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Enable REGULATOR_FIXED_VOLTAGE config needed for mmc.
Signed-off-by: Keerthy <j-keerthy@ti.com>
ti_config_fragments: v8_baseport.cfg: Add TPS65917(PALMAS) Configs
Enable TPS65917(PALMAS) configs.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Enable TPS65917(PALMAS) configs.
Signed-off-by: Keerthy <j-keerthy@ti.com>
arm64: dts: ti: k3-j721e-som-p0: Add tps65917 PMIC node
Add the tps65917 PMIC node and its child/parent nodes. tps65917 is the main
domain voltage supplier. We just add ldo1 & ldo2 which is bare minimum
controls we need. ldo1 feeds to sd and ldo2 feeds to vda_usb.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Add the tps65917 PMIC node and its child/parent nodes. tps65917 is the main
domain voltage supplier. We just add ldo1 & ldo2 which is bare minimum
controls we need. ldo1 feeds to sd and ldo2 feeds to vda_usb.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
arm64: dts: ti: j721e-common-proc-board: Analog audio support
The common processor board has a single pcm3168a codec connected to McASP10
We have 3 stereo headphone jacks and 1 stereo line-out,
2 stereo microphone and 1 stereo line-in jacks on the board.
TDM Channel mapping to output:
Playback
0-1 -> to 1st Stereo Headset jack (Stereo playback)
2-3 -> to 2nd Stereo Headset jack
4-5 -> to 3rd Stereo Headset jack
6-7 -> to Stereo Line-out jack
Capture:
0-1 -> from 1st Stereo Microphone jack (Stereo capture)
2-3 -> from 2st Stereo Microphone jack
4-5 -> from Stereo Line-in jack
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
The common processor board has a single pcm3168a codec connected to McASP10
We have 3 stereo headphone jacks and 1 stereo line-out,
2 stereo microphone and 1 stereo line-in jacks on the board.
TDM Channel mapping to output:
Playback
0-1 -> to 1st Stereo Headset jack (Stereo playback)
2-3 -> to 2nd Stereo Headset jack
4-5 -> to 3rd Stereo Headset jack
6-7 -> to Stereo Line-out jack
Capture:
0-1 -> from 1st Stereo Microphone jack (Stereo capture)
2-3 -> from 2st Stereo Microphone jack
4-5 -> from Stereo Line-in jack
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
ASoC: ti: davinci-mcasp: Support for auxclk-fs-ratio
When McASP is bus master and it's AUXCLK clock is not static, but it is
a multiple of the frame sync the constraint rules should take it account
when validating possible stream formats.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
When McASP is bus master and it's AUXCLK clock is not static, but it is
a multiple of the frame sync the constraint rules should take it account
when validating possible stream formats.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
bindings: sound: davinci-mcasp: Add support for optional auxclk-fs-ratio
When McASP is bus master it's reference clock (AUXCLK) might not be a
static clock, but running at a specific FS ratio.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
When McASP is bus master it's reference clock (AUXCLK) might not be a
static clock, but running at a specific FS ratio.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
arm64: dts: ti: k3-j721e-main: Add McASP nodes
Add the nodes for McASP 0-11 and keep them disabled because several
required properties are not present as they are board specific.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Add the nodes for McASP 0-11 and keep them disabled because several
required properties are not present as they are board specific.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Merge branch 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree into ti-linux-4.19.y
TI-Feature: platform_base
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree:
arm64: dts: am654-base-board: Reserve memory for jailhouse
mm: Re-export ioremap_page_range
arm, arm64: export __hyp_stub_vectors
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: platform_base
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree:
arm64: dts: am654-base-board: Reserve memory for jailhouse
mm: Re-export ioremap_page_range
arm, arm64: export __hyp_stub_vectors
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
Merge branch 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel into ti-linux-4.19.y
TI-Feature: connectivity
TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git
TI-Branch: connectivity-ti-linux-4.19.y
* 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel:
arm: dts: add am335x-boneblack-prusuart.dts
serial: add pru software uart (pru_suart) driver
dt-bindings: serial: add binding documentation for TI PRU software UART
arm64: dts: ti: k3-j721e-common-proc-board: Add QSPI DT node
arm64: dts: ti: k3-j721e-som-p0: Add OSPI flash node
arm64: dts: ti: k3-j721e: Add FSS DT nodes
dt-bindings: cadence-quadspi: Add compatible for J721E SoC
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: connectivity
TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git
TI-Branch: connectivity-ti-linux-4.19.y
* 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel:
arm: dts: add am335x-boneblack-prusuart.dts
serial: add pru software uart (pru_suart) driver
dt-bindings: serial: add binding documentation for TI PRU software UART
arm64: dts: ti: k3-j721e-common-proc-board: Add QSPI DT node
arm64: dts: ti: k3-j721e-som-p0: Add OSPI flash node
arm64: dts: ti: k3-j721e: Add FSS DT nodes
dt-bindings: cadence-quadspi: Add compatible for J721E SoC
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
arm64: dts: am654-base-board: Reserve memory for jailhouse
This has to be in sync with jailhouse cell configurations.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This has to be in sync with jailhouse cell configurations.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
mm: Re-export ioremap_page_range
We need this in Jailhouse to map at specific virtual addresses, at
least for the moment.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
We need this in Jailhouse to map at specific virtual addresses, at
least for the moment.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arm, arm64: export __hyp_stub_vectors
HVC_GET_VECTORS got removed. External hypervisors, like Jailhouse, need
this address when they are deactivated, in order to restore original
state.
Signed-off-by: Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[t-kristo@ti.com: moved the export clauses under arm*ksyms.c to avoid build
failures]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
HVC_GET_VECTORS got removed. External hypervisors, like Jailhouse, need
this address when they are deactivated, in order to restore original
state.
Signed-off-by: Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[t-kristo@ti.com: moved the export clauses under arm*ksyms.c to avoid build
failures]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
arm: dts: add am335x-boneblack-prusuart.dts
This adds dts support for PRU software-based UART on Beaglebone Black.
Cc: Jason Reeder <jreeder@ti.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This adds dts support for PRU software-based UART on Beaglebone Black.
Cc: Jason Reeder <jreeder@ti.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
serial: add pru software uart (pru_suart) driver
This adds a new serial driver that supports the PRU software based UART.
With the current version of the PRU UART firmware (v1.0), up to three UART
ports are supported per PRU core. Each character is two bytes in the FIFO.
Hardware flow control is supported if CTS/RTS pins are defined, but
software flow control is not.
Cc: Jason Reeder <jreeder@ti.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This adds a new serial driver that supports the PRU software based UART.
With the current version of the PRU UART firmware (v1.0), up to three UART
ports are supported per PRU core. Each character is two bytes in the FIFO.
Hardware flow control is supported if CTS/RTS pins are defined, but
software flow control is not.
Cc: Jason Reeder <jreeder@ti.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
dt-bindings: serial: add binding documentation for TI PRU software UART
This adds dt bindings for PRU software based UART on TI SoCs.
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This adds dt bindings for PRU software based UART on TI SoCs.
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
arm64: dts: ti: k3-j721e-common-proc-board: Add QSPI DT node
J721e EVM has a QSPI MT25Q flash connected to OSPI1. Add DT nodes for
the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
J721e EVM has a QSPI MT25Q flash connected to OSPI1. Add DT nodes for
the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
arm64: dts: ti: k3-j721e-som-p0: Add OSPI flash node
J721e SoM board contains MT35x Octal flash similar to AM654 EVM. Add
pinmux and flash DT node for the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
J721e SoM board contains MT35x Octal flash similar to AM654 EVM. Add
pinmux and flash DT node for the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
arm64: dts: ti: k3-j721e: Add FSS DT nodes
J721e SoC has same Flash Subsystem as AM654 with two OSPI flash
controllers. Add DT nodes for the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
J721e SoC has same Flash Subsystem as AM654 with two OSPI flash
controllers. Add DT nodes for the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
dt-bindings: cadence-quadspi: Add compatible for J721E SoC
Add compatible for OSPI on J721E SoC.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add compatible for OSPI on J721E SoC.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Merge branch 'audio_display-ti-linux-4.19.y' of git.ti.com:~jyrisarha/ti-linux-kernel/jyrisarhas-audio-video-linux-feature-tree into ti-linux-4.19.y
TI-Feature: audio-display
TI-Tree: git@git.ti.com:~jyrisarha/ti-linux-kernel/jyrisarhas-audio-video-linux-feature-tree.git
TI-Branch: audio_display-ti-linux-4.19.y
* 'audio_display-ti-linux-4.19.y' of git.ti.com:~jyrisarha/ti-linux-kernel/jyrisarhas-audio-video-linux-feature-tree:
arm64: dts: Add k3-j721e-common-proc-board-infotainment.dtso
arm64: dts: ti: k3-j721e-main.dtsi: Add DSS nodes
drm/tidss: dispc7: Add support for j721e DSS
dt-bindings: display/ti: Add ti,j7-dss binding document
drm/tidss: add 8/10 bit gamma support
drm/tidss: improve clock related prints
drm/tidss: fix handling of no-PM case
drm/bridge: tfp410: fix use of cancel_delayed_work_sync
drm/bridge: tfp410: fix memleak in get_modes()
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: audio-display
TI-Tree: git@git.ti.com:~jyrisarha/ti-linux-kernel/jyrisarhas-audio-video-linux-feature-tree.git
TI-Branch: audio_display-ti-linux-4.19.y
* 'audio_display-ti-linux-4.19.y' of git.ti.com:~jyrisarha/ti-linux-kernel/jyrisarhas-audio-video-linux-feature-tree:
arm64: dts: Add k3-j721e-common-proc-board-infotainment.dtso
arm64: dts: ti: k3-j721e-main.dtsi: Add DSS nodes
drm/tidss: dispc7: Add support for j721e DSS
dt-bindings: display/ti: Add ti,j7-dss binding document
drm/tidss: add 8/10 bit gamma support
drm/tidss: improve clock related prints
drm/tidss: fix handling of no-PM case
drm/bridge: tfp410: fix use of cancel_delayed_work_sync
drm/bridge: tfp410: fix memleak in get_modes()
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
arm64: dts: Add k3-j721e-common-proc-board-infotainment.dtso
Add support for TFP410 HDMI bridge located on the Infotainment Expansion
Board (connected to J46 & J51).
Signed-off-by: Benoit Parrot <bparrot@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Add support for TFP410 HDMI bridge located on the Infotainment Expansion
Board (connected to J46 & J51).
Signed-off-by: Benoit Parrot <bparrot@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
arm64: dts: ti: k3-j721e-main.dtsi: Add DSS nodes
Add nodes for J721E DSS.
The DSS related clock muxes are set via assigned-clocks in a way which
provides us:
VP0 - DisplayPort SST
VP1 - DPI0
VP2 - DSI
VP3 - DPI1
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Benoit Parrot <bparrot@ti.com>
Add nodes for J721E DSS.
The DSS related clock muxes are set via assigned-clocks in a way which
provides us:
VP0 - DisplayPort SST
VP1 - DPI0
VP2 - DSI
VP3 - DPI1
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Benoit Parrot <bparrot@ti.com>
drm/tidss: dispc7: Add support for j721e DSS
This patch adds support for DSS on J721E, which is a SoC in Texas
Instruments Keystone 3 family.
J721E DSS is DSS7, similarly to AM6. However, the J721E DSS7 is an
extended version, and while the basic features are the same, there are
multiple differences. Some of the features/differences are:
- 4 videoports
- 4 planes (2 of the "lite", without scaling)
- Support up to 8k displays
- 2 DPI outputs
- DisplayPort and DSI support (implemented separately as DRM bridge
drivers).
- No OLDI
- Support for DSS videport/plane sharing between different CPU cores
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Benoit Parrot <bparrot@ti.com>
This patch adds support for DSS on J721E, which is a SoC in Texas
Instruments Keystone 3 family.
J721E DSS is DSS7, similarly to AM6. However, the J721E DSS7 is an
extended version, and while the basic features are the same, there are
multiple differences. Some of the features/differences are:
- 4 videoports
- 4 planes (2 of the "lite", without scaling)
- Support up to 8k displays
- 2 DPI outputs
- DisplayPort and DSI support (implemented separately as DRM bridge
drivers).
- No OLDI
- Support for DSS videport/plane sharing between different CPU cores
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Benoit Parrot <bparrot@ti.com>
dt-bindings: display/ti: Add ti,j7-dss binding document
Add j721e DSS binding document.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Benoit Parrot <bparrot@ti.com>
Add j721e DSS binding document.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Benoit Parrot <bparrot@ti.com>
drm/tidss: add 8/10 bit gamma support
J721E DSS has 10 bit gamma support, instead of 8 bit as K2G and AM6
does.
To prepare for J721E DSS, add support for the two different types of
gamma tables.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Benoit Parrot <bparrot@ti.com>
J721E DSS has 10 bit gamma support, instead of 8 bit as K2G and AM6
does.
To prepare for J721E DSS, add support for the two different types of
gamma tables.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Benoit Parrot <bparrot@ti.com>
drm/tidss: improve clock related prints
Add videoport number to some clock related prints.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Benoit Parrot <bparrot@ti.com>
Add videoport number to some clock related prints.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Benoit Parrot <bparrot@ti.com>
drm/tidss: fix handling of no-PM case
If the kernel is configured without PM, runtime PM calls will be no-ops.
However, the tidss driver relies on runtime PM resume and suspend to
function properly.
We have a special case inside #ifdefs to manually call the runtime
resume and suspend so that the driver initializes correctly.
However, the driver is checking against CONFIG_PM_SLEEP, which is not
correct. This patch fixes the check to be against CONFIG_PM.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Benoit Parrot <bparrot@ti.com>
If the kernel is configured without PM, runtime PM calls will be no-ops.
However, the tidss driver relies on runtime PM resume and suspend to
function properly.
We have a special case inside #ifdefs to manually call the runtime
resume and suspend so that the driver initializes correctly.
However, the driver is checking against CONFIG_PM_SLEEP, which is not
correct. This patch fixes the check to be against CONFIG_PM.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Benoit Parrot <bparrot@ti.com>
drm/bridge: tfp410: fix use of cancel_delayed_work_sync
We use delayed_work in HPD handling, and cancel any scheduled work in
tfp410_fini using cancel_delayed_work_sync(). However, we have only
initialized the delayed work if we actually have a HPD interrupt
configured in the DT, but in the tfp410_fini, we always cancel the work,
possibly causing a WARN().
Fix this by doing the cancel only if we actually had the delayed work
set up.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Benoit Parrot <bparrot@ti.com>
We use delayed_work in HPD handling, and cancel any scheduled work in
tfp410_fini using cancel_delayed_work_sync(). However, we have only
initialized the delayed work if we actually have a HPD interrupt
configured in the DT, but in the tfp410_fini, we always cancel the work,
possibly causing a WARN().
Fix this by doing the cancel only if we actually had the delayed work
set up.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Benoit Parrot <bparrot@ti.com>
drm/bridge: tfp410: fix memleak in get_modes()
We don't free the edid blob allocated by the call to drm_get_edid(),
causing a memleak. Fix this by calling kfree(edid) at the end of the
get_modes().
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Benoit Parrot <bparrot@ti.com>
We don't free the edid blob allocated by the call to drm_get_edid(),
causing a memleak. Fix this by calling kfree(edid) at the end of the
get_modes().
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Benoit Parrot <bparrot@ti.com>
Merge branch 'rpmsg-ti-linux-4.19.y-intg' of git://git.ti.com/rpmsg/rpmsg into ti-linux-4.19.y
TI-Feature: rpmsg
TI-Tree: git://git.ti.com/rpmsg/rpmsg.git
TI-Branch: rpmsg-ti-linux-4.19.y-intg
* 'rpmsg-ti-linux-4.19.y-intg' of git://git.ti.com/rpmsg/rpmsg:
soc: ti: pruss: Rename pruss_regmap_read()/update() API
soc: ti: pruss: Drop MII-RT management from PRUSS driver
soc: ti: pruss: Remove stale iep variable
irqchip/irq-pruss-intc: Use bitmap to simplify event configuration
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: rpmsg
TI-Tree: git://git.ti.com/rpmsg/rpmsg.git
TI-Branch: rpmsg-ti-linux-4.19.y-intg
* 'rpmsg-ti-linux-4.19.y-intg' of git://git.ti.com/rpmsg/rpmsg:
soc: ti: pruss: Rename pruss_regmap_read()/update() API
soc: ti: pruss: Drop MII-RT management from PRUSS driver
soc: ti: pruss: Remove stale iep variable
irqchip/irq-pruss-intc: Use bitmap to simplify event configuration
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
Merge branch 'rpmsg-ti-linux-4.19.y' of git://git.ti.com/rpmsg/rpmsg into rpmsg-ti-linux-4.19.y-intg
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Merge branch 'topic/4.19/am65x' of git://git.ti.com/rpmsg/remoteproc into rpmsg-ti-linux-4.19.y
Pull in the dedicated AM65x remoteproc topic branch that drops the
MII-RT management from the PRUSS platform driver and some cleanup
in the PRUSS INTC platform drivers. The pruss_regmap_read() and
pruss_regmap_update() API are also cleaned up and renamed to
pruss_cfg_read() and pruss_cfg_update() respectively.
* 'topic/4.19/am65x' of git://git.ti.com/rpmsg/remoteproc:
soc: ti: pruss: Rename pruss_regmap_read()/update() API
soc: ti: pruss: Drop MII-RT management from PRUSS driver
soc: ti: pruss: Remove stale iep variable
irqchip/irq-pruss-intc: Use bitmap to simplify event configuration
Signed-off-by: Suman Anna <s-anna@ti.com>
Pull in the dedicated AM65x remoteproc topic branch that drops the
MII-RT management from the PRUSS platform driver and some cleanup
in the PRUSS INTC platform drivers. The pruss_regmap_read() and
pruss_regmap_update() API are also cleaned up and renamed to
pruss_cfg_read() and pruss_cfg_update() respectively.
* 'topic/4.19/am65x' of git://git.ti.com/rpmsg/remoteproc:
soc: ti: pruss: Rename pruss_regmap_read()/update() API
soc: ti: pruss: Drop MII-RT management from PRUSS driver
soc: ti: pruss: Remove stale iep variable
irqchip/irq-pruss-intc: Use bitmap to simplify event configuration
Signed-off-by: Suman Anna <s-anna@ti.com>
soc: ti: pruss: Rename pruss_regmap_read()/update() API
The pruss_regmap_read() and pruss_regmap_update() API were designed
to support reading and updating any of the registers within the
CFG, MII-RT or IEP sub-modules. The management of MII-RT and IEP
submodules is dropped from the PRUSS platform driver, so simplify
the functionality of these functions to just deal with the CFG
sub-module. Both the functions have been renamed appropriately to
pruss_cfg_read() and pruss_cfg_update(), and all existing callsites
updated accordingly.
Signed-off-by: Suman Anna <s-anna@ti.com>
The pruss_regmap_read() and pruss_regmap_update() API were designed
to support reading and updating any of the registers within the
CFG, MII-RT or IEP sub-modules. The management of MII-RT and IEP
submodules is dropped from the PRUSS platform driver, so simplify
the functionality of these functions to just deal with the CFG
sub-module. Both the functions have been renamed appropriately to
pruss_cfg_read() and pruss_cfg_update(), and all existing callsites
updated accordingly.
Signed-off-by: Suman Anna <s-anna@ti.com>
soc: ti: pruss: Drop MII-RT management from PRUSS driver
The MII-RT sub-module is represented as a syscon node and is
managed by the PRUSS platform driver at the moment. The usage
of MII-RT is limited to PRU Ethernet drivers, and so makes sense
to manage this sub-module by those drivers directly. So, drop
the code from the PRUSS platform driver that deals with parsing
of the mii-rt DT nodes or providing an API wrapper for accessing
any registers within this sub-module.
Signed-off-by: Suman Anna <s-anna@ti.com>
The MII-RT sub-module is represented as a syscon node and is
managed by the PRUSS platform driver at the moment. The usage
of MII-RT is limited to PRU Ethernet drivers, and so makes sense
to manage this sub-module by those drivers directly. So, drop
the code from the PRUSS platform driver that deals with parsing
of the mii-rt DT nodes or providing an API wrapper for accessing
any registers within this sub-module.
Signed-off-by: Suman Anna <s-anna@ti.com>
soc: ti: pruss: Remove stale iep variable
The commit 7cff1bbab114 ("soc: ti: pruss: Drop IEP management from
PRUSS driver") has removed the management of IEP from PRUSS platform
driver, but missed cleaning up the iep variable. Drop this variable
from the pruss structure.
Signed-off-by: Suman Anna <s-anna@ti.com>
The commit 7cff1bbab114 ("soc: ti: pruss: Drop IEP management from
PRUSS driver") has removed the management of IEP from PRUSS platform
driver, but missed cleaning up the iep variable. Drop this variable
from the pruss structure.
Signed-off-by: Suman Anna <s-anna@ti.com>
irqchip/irq-pruss-intc: Use bitmap to simplify event configuration
Simplify the PRUSS System Event management code to use the bitmap API in
the pruss_intc_configure() and pruss_intc_unconfigure() functions.
Signed-off-by: Suman Anna <s-anna@ti.com>
Acked-by: Andrew F. Davis <afd@ti.com>
Simplify the PRUSS System Event management code to use the bitmap API in
the pruss_intc_configure() and pruss_intc_unconfigure() functions.
Signed-off-by: Suman Anna <s-anna@ti.com>
Acked-by: Andrew F. Davis <afd@ti.com>
Merge branch 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel into ti-linux-4.19.y
TI-Feature: connectivity
TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git
TI-Branch: connectivity-ti-linux-4.19.y
* 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel:
arm64: dts: j721e-common-proc-board: enable pps support for mcu cpsw cpts
arm64: dts: ti: j721e-main: add timesync_router node
arm64: dts: ti: j721e-main: add main navss cpts node
net: ethernet: ti: am65-cpts: add support for J721E SoC
dt-binding: net: ti: am654-cpts: add new compatible for J721E SoCs
arm64: dts: ti: k3-j721e-common-proc-board: add mcu cpsw nuss pinmux and phy defs
arm64: dts: ti: k3-j721e-mcu: add mcu cpsw nuss node
arm64: dts: ti: k3-j721e-mcu: add scm node
net: ethernet: ti: am65-cpsw-nuss: add support for J721E SoC
dt-binding: net: ti: am654-cpsw: add new compatible for J721E SoCs
net: ethernet: ti: am65-cpsw-nuss: use rnd mac addr if efuse is 0
net: ethernet: ti: am65-cpts: fix boot without cpts_refclk_mux
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: connectivity
TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git
TI-Branch: connectivity-ti-linux-4.19.y
* 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel:
arm64: dts: j721e-common-proc-board: enable pps support for mcu cpsw cpts
arm64: dts: ti: j721e-main: add timesync_router node
arm64: dts: ti: j721e-main: add main navss cpts node
net: ethernet: ti: am65-cpts: add support for J721E SoC
dt-binding: net: ti: am654-cpts: add new compatible for J721E SoCs
arm64: dts: ti: k3-j721e-common-proc-board: add mcu cpsw nuss pinmux and phy defs
arm64: dts: ti: k3-j721e-mcu: add mcu cpsw nuss node
arm64: dts: ti: k3-j721e-mcu: add scm node
net: ethernet: ti: am65-cpsw-nuss: add support for J721E SoC
dt-binding: net: ti: am654-cpsw: add new compatible for J721E SoCs
net: ethernet: ti: am65-cpsw-nuss: use rnd mac addr if efuse is 0
net: ethernet: ti: am65-cpts: fix boot without cpts_refclk_mux
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
Merge branch 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree into ti-linux-4.19.y
TI-Feature: platform_base
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree:
soc: ti: ti_sci_pm_domains: switch to use multiple genpds instead of one
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: platform_base
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree:
soc: ti: ti_sci_pm_domains: switch to use multiple genpds instead of one
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
arm64: dts: j721e-common-proc-board: enable pps support for mcu cpsw cpts
Enable pps support for MCU CPSW CPTS by routing GenF1 output to
MCU_CPTS_HW4_PUSH input.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Enable pps support for MCU CPSW CPTS by routing GenF1 output to
MCU_CPTS_HW4_PUSH input.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
arm64: dts: ti: j721e-main: add timesync_router node
The Time Sync Event Router (TIMESYNC_INTRTR0) implements a set of
multiplexers to provide selection of active CPTS time sync events for
routing to CPTS capable modules.
The TIMESYNC_INTRTR0 module has the following configuration:
• Number of input events: 55
• Number of output events: 40
• Event input type: Pulse
This patch adds DT node TIMESYNC_INTRTR0 using "pinctrl-single" bindings.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The Time Sync Event Router (TIMESYNC_INTRTR0) implements a set of
multiplexers to provide selection of active CPTS time sync events for
routing to CPTS capable modules.
The TIMESYNC_INTRTR0 module has the following configuration:
• Number of input events: 55
• Number of output events: 40
• Event input type: Pulse
This patch adds DT node TIMESYNC_INTRTR0 using "pinctrl-single" bindings.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
arm64: dts: ti: j721e-main: add main navss cpts node
Add DT node for Main NAVSS CPTS module.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add DT node for Main NAVSS CPTS module.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
net: ethernet: ti: am65-cpts: add support for J721E SoC
The J721E SoC has the same Common platform time sync (CPTS) modules as TI
AM654 SoC. Hence, add support for J721E SoC.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The J721E SoC has the same Common platform time sync (CPTS) modules as TI
AM654 SoC. Hence, add support for J721E SoC.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
dt-binding: net: ti: am654-cpts: add new compatible for J721E SoCs
The J721E SoC has the same Common platform time sync (CPTS) modules as TI
AM654 SoC. Hence, add new compatible for J721E SoCs.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The J721E SoC has the same Common platform time sync (CPTS) modules as TI
AM654 SoC. Hence, add new compatible for J721E SoCs.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
arm64: dts: ti: k3-j721e-common-proc-board: add mcu cpsw nuss pinmux and phy defs
The TI j721e EVM base board has TI DP83867 PHY connected to external CPSW
NUSS Port 1 in rgmii mode.
Hence, add pinmux and Ethernet PHY configuration for TI j721e SoC MCU
Gigabit Ethernet two ports Switch subsystem (CPSW NUSS).
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The TI j721e EVM base board has TI DP83867 PHY connected to external CPSW
NUSS Port 1 in rgmii mode.
Hence, add pinmux and Ethernet PHY configuration for TI j721e SoC MCU
Gigabit Ethernet two ports Switch subsystem (CPSW NUSS).
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
arm64: dts: ti: k3-j721e-mcu: add mcu cpsw nuss node
Add DT node for The TI j721e MCU SoC Gigabit Ethernet two ports Switch
subsystem (MCU CPSW NUSS).
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add DT node for The TI j721e MCU SoC Gigabit Ethernet two ports Switch
subsystem (MCU CPSW NUSS).
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
arm64: dts: ti: k3-j721e-mcu: add scm node
Add DT node for MCU System Control module DT node.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add DT node for MCU System Control module DT node.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
net: ethernet: ti: am65-cpsw-nuss: add support for J721E SoC
The J721E SoC has the same MCU Gigabit Ethernet two ports Switch subsystem
(MCU CPSW NUSS) as TI AM654 SoC in general.
The difference:
- J721E MCU CPSW NUSS has I2027 errata fixed.
Hence, add support for J721E MCU CPSW NUSS and use compatible string and
of_device_id table to define supported features.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The J721E SoC has the same MCU Gigabit Ethernet two ports Switch subsystem
(MCU CPSW NUSS) as TI AM654 SoC in general.
The difference:
- J721E MCU CPSW NUSS has I2027 errata fixed.
Hence, add support for J721E MCU CPSW NUSS and use compatible string and
of_device_id table to define supported features.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
dt-binding: net: ti: am654-cpsw: add new compatible for J721E SoCs
The J721E SoC has the same MCU Gigabit Ethernet two ports Switch subsystem
(MCU CPSW NUSS) as TI AM654 SoC in general.
The difference:
- J721E MCU CPSW NUSS has I2027 errata fixed.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The J721E SoC has the same MCU Gigabit Ethernet two ports Switch subsystem
(MCU CPSW NUSS) as TI AM654 SoC in general.
The difference:
- J721E MCU CPSW NUSS has I2027 errata fixed.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
net: ethernet: ti: am65-cpsw-nuss: use rnd mac addr if efuse is 0
Add additional check for MAC addr read from eFuse and use random
MAC addr if it's invalid.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add additional check for MAC addr read from eFuse and use random
MAC addr if it's invalid.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
net: ethernet: ti: am65-cpts: fix boot without cpts_refclk_mux
The TI J721E SoC has cpts_refclk_mux register moved into MCU
CTRL_MMR IO space and it's under control of TI SCI FW now.
Hence, fix MCU CPTS boot by allowing initialization without cpts_refclk_mux
node defined in DT.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The TI J721E SoC has cpts_refclk_mux register moved into MCU
CTRL_MMR IO space and it's under control of TI SCI FW now.
Hence, fix MCU CPTS boot by allowing initialization without cpts_refclk_mux
node defined in DT.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Merge branch 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel into ti-linux-4.19.y
TI-Feature: connectivity
TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git
TI-Branch: connectivity-ti-linux-4.19.y
* 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel:
arm64: dts: ti: k3-j721e-common-proc-board: Add I2C GPIO expander nodes
arm64: dts: ti: k3-j721e-mcu-wakeup: Add I2C nodes
arm64: dts: ti: k3-j721e-main: Add I2C nodes
dt-bindings: i2c: omap: Add new compatible for J721E SoCs
Signed-off-by: Dan Murphy <dmurphy@ti.com>
# Conflicts:
# arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
TI-Feature: connectivity
TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git
TI-Branch: connectivity-ti-linux-4.19.y
* 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel:
arm64: dts: ti: k3-j721e-common-proc-board: Add I2C GPIO expander nodes
arm64: dts: ti: k3-j721e-mcu-wakeup: Add I2C nodes
arm64: dts: ti: k3-j721e-main: Add I2C nodes
dt-bindings: i2c: omap: Add new compatible for J721E SoCs
Signed-off-by: Dan Murphy <dmurphy@ti.com>
# Conflicts:
# arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
soc: ti: ti_sci_pm_domains: switch to use multiple genpds instead of one
Current implementation of the genpd support over TI SCI uses a single
genpd across the whole SoC, and attaches multiple devices to this. This
solution has its drawbacks, like it is currently impossible to attach
more than one power domain to a device; the core genpd implementation
requires one genpd per power-domain entry in DT for a single device.
Also, some devices like USB apparently require their own genpd during
probe time, the current shared approach in use does not work at all.
Switch the implementation over to use a single genpd per power domain
entry in DT. The domains are registered with the onecell approach, but
we also add our own xlate service due to recent introduction of the
extended flag for TI SCI PM domains; genpd core xlate service requires
a single cell per powerdomain, but we are using two cells.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Current implementation of the genpd support over TI SCI uses a single
genpd across the whole SoC, and attaches multiple devices to this. This
solution has its drawbacks, like it is currently impossible to attach
more than one power domain to a device; the core genpd implementation
requires one genpd per power-domain entry in DT for a single device.
Also, some devices like USB apparently require their own genpd during
probe time, the current shared approach in use does not work at all.
Switch the implementation over to use a single genpd per power domain
entry in DT. The domains are registered with the onecell approach, but
we also add our own xlate service due to recent introduction of the
extended flag for TI SCI PM domains; genpd core xlate service requires
a single cell per powerdomain, but we are using two cells.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Merge branch 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree into ti-linux-4.19.y
TI-Feature: platform_base
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree:
firmware: ti_sci: Parse all resource ranges even if some is not available
arm64: dts: ti: k3-j721e-mcu-wakeup: Add PDMA nodes
arm64: dts: ti: k3-j721e-main: Add PDMA nodes
arm64: dts: ti: k3-j721e-mcu-wakeup: Add mcu NAVSS nodes for DMA support
arm64: dts: ti: k3-j721e-main: Add main NAVSS nodes for DMA support
dmaengine: ti: k3-udma: Add support for j721e
dt-bindings: dma: ti: k3-udma: Update to include j721e UDMA
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: platform_base
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree:
firmware: ti_sci: Parse all resource ranges even if some is not available
arm64: dts: ti: k3-j721e-mcu-wakeup: Add PDMA nodes
arm64: dts: ti: k3-j721e-main: Add PDMA nodes
arm64: dts: ti: k3-j721e-mcu-wakeup: Add mcu NAVSS nodes for DMA support
arm64: dts: ti: k3-j721e-main: Add main NAVSS nodes for DMA support
dmaengine: ti: k3-udma: Add support for j721e
dt-bindings: dma: ti: k3-udma: Update to include j721e UDMA
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
arm64: dts: ti: k3-j721e-common-proc-board: Add I2C GPIO expander nodes
J721e common processor board has 5 I2C GPIO expanders. Add DT nodes for
the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
J721e common processor board has 5 I2C GPIO expanders. Add DT nodes for
the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
arm64: dts: ti: k3-j721e-mcu-wakeup: Add I2C nodes
Add the nodes for MCU_I2C0-1 and WKUP_I2C0.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[vigneshr@ti.com] Fix up WKUP_I2C0 power domain and MCUSS Ranges.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add the nodes for MCU_I2C0-1 and WKUP_I2C0.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[vigneshr@ti.com] Fix up WKUP_I2C0 power domain and MCUSS Ranges.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
arm64: dts: ti: k3-j721e-main: Add I2C nodes
Add the nodes for I2C0-6 of main domin.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add the nodes for I2C0-6 of main domin.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
dt-bindings: i2c: omap: Add new compatible for J721E SoCs
J721E SoCs have same I2C IP as OMAP SoCs. Add new compatible to
handle J721E SoCs.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
J721E SoCs have same I2C IP as OMAP SoCs. Add new compatible to
handle J721E SoCs.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
firmware: ti_sci: Parse all resource ranges even if some is not available
Do not fail if any of the requested subtypes are not availabe, but set the
number of resources to 0 and continue parsing the resource ranges.
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Do not fail if any of the requested subtypes are not availabe, but set the
number of resources to 0 and continue parsing the resource ranges.
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
arm64: dts: ti: k3-j721e-mcu-wakeup: Add PDMA nodes
Add the PDMA nodes needed for USART, SPI.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Add the PDMA nodes needed for USART, SPI.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
arm64: dts: ti: k3-j721e-main: Add PDMA nodes
Add the PDMA nodes needed for USART, SPI and McASP.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Add the PDMA nodes needed for USART, SPI and McASP.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
arm64: dts: ti: k3-j721e-mcu-wakeup: Add mcu NAVSS nodes for DMA support
Enable the UDMA support by adding and populating the mcu NAVSS.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Enable the UDMA support by adding and populating the mcu NAVSS.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
arm64: dts: ti: k3-j721e-main: Add main NAVSS nodes for DMA support
Enable the UDMA support by adding and populating the main NAVSS.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Enable the UDMA support by adding and populating the main NAVSS.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
dmaengine: ti: k3-udma: Add support for j721e
The changes needed to support the UDMAP/PDMA on J721e:
- We have 3 performance levels for channels compared to 2 in am6
- The output event offset (oes) is changed in sysfw for rchans
- PDMA's staticTR Z is now larger
- PDMA have new fields: acc32 and burst.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
The changes needed to support the UDMAP/PDMA on J721e:
- We have 3 performance levels for channels compared to 2 in am6
- The output event offset (oes) is changed in sysfw for rchans
- PDMA's staticTR Z is now larger
- PDMA have new fields: acc32 and burst.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
dt-bindings: dma: ti: k3-udma: Update to include j721e UDMA
Update the binding document for UDMAs found in j721e.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Update the binding document for UDMAs found in j721e.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Merge branch 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree into ti-linux-4.19.y
TI-Feature: platform_base
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree:
ti_config_fragments: v8_baseport: Enable ION driver
ti_config_fragments: baseport: Enable ION driver
staging: android: ion: Add ION driver for TI platforms
dt-bindings: staging: android: ion: Add ti,ion binding doc
staging: android: ion: Declare helpers for carveout and chunk heaps
staging: android: ion: Allow heap name to be null
staging: android: ion: Do not sync CPU cache on map/unmap
dmaengine: ti: k3-navss-udma: reset tx/rx rt regs upon channel request
arm64: dts: ti: k3-j721e: Add the MCU SRAM node
arm64: dts: ti: k3-j721e-common-proc-board: Disable unused gpio modules
arm64: dts: ti: k3-j721e: Add gpio nodes in wakeup domain
arm64: dts: ti: k3-j721e: Add gpio nodes in main domain
dt-bindings: gpio: davinci: Add new compatible for J721E SoCs
arm64: dts: ti: k3-j721e: Add interrupt controllers in wakeup domain
arm64: dts: ti: k3-j721e: Add interrupt controllers in main domain
arm64: dts: ti: Update power-domain cells for uart 8
Signed-off-by: Dan Murphy <dmurphy@ti.com>
# Conflicts:
# arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
TI-Feature: platform_base
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree:
ti_config_fragments: v8_baseport: Enable ION driver
ti_config_fragments: baseport: Enable ION driver
staging: android: ion: Add ION driver for TI platforms
dt-bindings: staging: android: ion: Add ti,ion binding doc
staging: android: ion: Declare helpers for carveout and chunk heaps
staging: android: ion: Allow heap name to be null
staging: android: ion: Do not sync CPU cache on map/unmap
dmaengine: ti: k3-navss-udma: reset tx/rx rt regs upon channel request
arm64: dts: ti: k3-j721e: Add the MCU SRAM node
arm64: dts: ti: k3-j721e-common-proc-board: Disable unused gpio modules
arm64: dts: ti: k3-j721e: Add gpio nodes in wakeup domain
arm64: dts: ti: k3-j721e: Add gpio nodes in main domain
dt-bindings: gpio: davinci: Add new compatible for J721E SoCs
arm64: dts: ti: k3-j721e: Add interrupt controllers in wakeup domain
arm64: dts: ti: k3-j721e: Add interrupt controllers in main domain
arm64: dts: ti: Update power-domain cells for uart 8
Signed-off-by: Dan Murphy <dmurphy@ti.com>
# Conflicts:
# arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
Merge branch 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel into ti-linux-4.19.y
TI-Feature: connectivity
TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git
TI-Branch: connectivity-ti-linux-4.19.y
* 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel: (23 commits)
mmc: sdhci_am654: Fix DLL trim and driver strength configuration
mmc: sdhci_am654: Fix SLOTTYPE write
mmc: sdhci_am654: Print error message if the DLL fails to lock
mmc: sdhci_am654: Improve line wrapping with regmap_*() calls
ti_config_fragments: connectivity.cfg: Enable Cadence USB3 drivers
usb: cdns3: Implement Idle state for Type-C
usb: cdns3: make dynamic role switching work
usb: cdns3: use phy power on/off
usb: cdns3: Add TI specific wrapper driver
dt-bindings: usb: Add binding for the TI wrapper for Cadence USB3 controller
usb: cdns3: drd: print error on xhci/dev ready timeout
usb: cdns3: drd: don't call drd_update_mode in drd_init()
usb: cdns3: support separate IRQs for otg/xhci/dev
usb:cdns3 Fix for stuck packets in on-chip OUT buffer.
usb:cdns3 Add Cadence USB3 DRD Driver
usb:common Simplify usb_decode_get_set_descriptor function.
usb:common Patch simplify usb_decode_set_clear_feature function.
usb:common Separated decoding functions from dwc3 driver.
dt-bindings: add binding for USBSS-DRD controller.
usb: dwc3: debug: purge usage of strcat
...
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: connectivity
TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git
TI-Branch: connectivity-ti-linux-4.19.y
* 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel: (23 commits)
mmc: sdhci_am654: Fix DLL trim and driver strength configuration
mmc: sdhci_am654: Fix SLOTTYPE write
mmc: sdhci_am654: Print error message if the DLL fails to lock
mmc: sdhci_am654: Improve line wrapping with regmap_*() calls
ti_config_fragments: connectivity.cfg: Enable Cadence USB3 drivers
usb: cdns3: Implement Idle state for Type-C
usb: cdns3: make dynamic role switching work
usb: cdns3: use phy power on/off
usb: cdns3: Add TI specific wrapper driver
dt-bindings: usb: Add binding for the TI wrapper for Cadence USB3 controller
usb: cdns3: drd: print error on xhci/dev ready timeout
usb: cdns3: drd: don't call drd_update_mode in drd_init()
usb: cdns3: support separate IRQs for otg/xhci/dev
usb:cdns3 Fix for stuck packets in on-chip OUT buffer.
usb:cdns3 Add Cadence USB3 DRD Driver
usb:common Simplify usb_decode_get_set_descriptor function.
usb:common Patch simplify usb_decode_set_clear_feature function.
usb:common Separated decoding functions from dwc3 driver.
dt-bindings: add binding for USBSS-DRD controller.
usb: dwc3: debug: purge usage of strcat
...
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
ti_config_fragments: v8_baseport: Enable ION driver
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
ti_config_fragments: baseport: Enable ION driver
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>