5 years agoMerge branch 'ti-linux-4.19.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel into... ti-rt-linux-4.14.y-next-20181129 ti-rt-linux-4.14.y-next-20181130 ti-rt-linux-4.19.y-next-20181129 ti-rt-linux-4.19.y-next-20181130
Merge branch 'ti-linux-4.19.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel into ti-rt-linux-4.19.y
TI-Feature: ti_linux_base_rt
TI-Tree: git@git.ti.com:ti-linux-kernel/ti-linux-kernel.git
TI-Branch: ti-linux-4.19.y
* 'ti-linux-4.19.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel:
arm64: dts: ti: k3-am6: Add NAVSS and PDMA nodes
dmaengine: ti: k3-udma: Add glue layer for non DMAengine users
dmaengine: ti: New driver for K3 UDMA
dmaengine: ti: Add cppi5 header for UDMA
dt-bindings: dma: ti: Add document for K3 UDMA
dmaengine: Add function to request slave channel from a dma_device
dmaengine: Add support for reporting DMA cached data amount
dmaengine: Add metadata_ops for dma_async_tx_descriptor
dmaengine: doc: Add sections for per descriptor metadata support
soc: ti: k3: add navss ringacc driver
bindings: soc: ti: add documentation for k3 ringacc
firmware: ti_sci: Add resource management APIs for ringacc, psi-l and udma
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: ti_linux_base_rt
TI-Tree: git@git.ti.com:ti-linux-kernel/ti-linux-kernel.git
TI-Branch: ti-linux-4.19.y
* 'ti-linux-4.19.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel:
arm64: dts: ti: k3-am6: Add NAVSS and PDMA nodes
dmaengine: ti: k3-udma: Add glue layer for non DMAengine users
dmaengine: ti: New driver for K3 UDMA
dmaengine: ti: Add cppi5 header for UDMA
dt-bindings: dma: ti: Add document for K3 UDMA
dmaengine: Add function to request slave channel from a dma_device
dmaengine: Add support for reporting DMA cached data amount
dmaengine: Add metadata_ops for dma_async_tx_descriptor
dmaengine: doc: Add sections for per descriptor metadata support
soc: ti: k3: add navss ringacc driver
bindings: soc: ti: add documentation for k3 ringacc
firmware: ti_sci: Add resource management APIs for ringacc, psi-l and udma
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
Merge branch 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree into ti-linux-4.19.y
TI-Feature: platform_base
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree:
arm64: dts: ti: k3-am6: Add NAVSS and PDMA nodes
dmaengine: ti: k3-udma: Add glue layer for non DMAengine users
dmaengine: ti: New driver for K3 UDMA
dmaengine: ti: Add cppi5 header for UDMA
dt-bindings: dma: ti: Add document for K3 UDMA
dmaengine: Add function to request slave channel from a dma_device
dmaengine: Add support for reporting DMA cached data amount
dmaengine: Add metadata_ops for dma_async_tx_descriptor
dmaengine: doc: Add sections for per descriptor metadata support
soc: ti: k3: add navss ringacc driver
bindings: soc: ti: add documentation for k3 ringacc
firmware: ti_sci: Add resource management APIs for ringacc, psi-l and udma
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: platform_base
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree:
arm64: dts: ti: k3-am6: Add NAVSS and PDMA nodes
dmaengine: ti: k3-udma: Add glue layer for non DMAengine users
dmaengine: ti: New driver for K3 UDMA
dmaengine: ti: Add cppi5 header for UDMA
dt-bindings: dma: ti: Add document for K3 UDMA
dmaengine: Add function to request slave channel from a dma_device
dmaengine: Add support for reporting DMA cached data amount
dmaengine: Add metadata_ops for dma_async_tx_descriptor
dmaengine: doc: Add sections for per descriptor metadata support
soc: ti: k3: add navss ringacc driver
bindings: soc: ti: add documentation for k3 ringacc
firmware: ti_sci: Add resource management APIs for ringacc, psi-l and udma
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
arm64: dts: ti: k3-am6: Add NAVSS and PDMA nodes
Add nodes and sub nodes for both NAVSS (main and mcu) and add the PDMA
nodes as well.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Add nodes and sub nodes for both NAVSS (main and mcu) and add the PDMA
nodes as well.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
dmaengine: ti: k3-udma: Add glue layer for non DMAengine users
Certain users can not use right now the DMAengine API due to missing
features in the core. Prime example is Networking.
These users can use the glue layer interface to avoid misuse of DMAengine
API and when the core gains the needed features they can be converted to
use generic API.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Certain users can not use right now the DMAengine API due to missing
features in the core. Prime example is Networking.
These users can use the glue layer interface to avoid misuse of DMAengine
API and when the core gains the needed features they can be converted to
use generic API.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
dmaengine: ti: New driver for K3 UDMA
DMA driver for
Texas Instruments K3 NAVSS Unified DMA – Peripheral Root Complex (UDMA-P)
The UDMA-P is intended to perform similar (but significantly upgraded) functions
as the packet-oriented DMA used on previous SoC devices. The UDMA-P module
supports the transmission and reception of various packet types. The UDMA-P is
architected to facilitate the segmentation and reassembly of SoC DMA data
structure compliant packets to/from smaller data blocks that are natively
compatible with the specific requirements of each connected peripheral. Multiple
Tx and Rx channels are provided within the DMA which allow multiple segmentation
or reassembly operations to be ongoing. The DMA controller maintains state
information for each of the channels which allows packet segmentation and
reassembly operations to be time division multiplexed between channels in order
to share the underlying DMA hardware. An external DMA scheduler is used to
control the ordering and rate at which this multiplexing occurs for Transmit
operations. The ordering and rate of Receive operations is indirectly controlled
by the order in which blocks are pushed into the DMA on the Rx PSI-L interface.
The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
channels. Channels in the UDMA-P can be configured to be either Packet-Based or
Third-Party channels on a channel by channel basis.
The initial driver supports:
- MEM_TO_MEM (TR mode)
- DEV_TO_MEM (Packet / TR mode)
- MEM_TO_DEV (Packet / TR mode)
- Cyclic (Packet / TR mode)
- Metadata for descriptors
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
DMA driver for
Texas Instruments K3 NAVSS Unified DMA – Peripheral Root Complex (UDMA-P)
The UDMA-P is intended to perform similar (but significantly upgraded) functions
as the packet-oriented DMA used on previous SoC devices. The UDMA-P module
supports the transmission and reception of various packet types. The UDMA-P is
architected to facilitate the segmentation and reassembly of SoC DMA data
structure compliant packets to/from smaller data blocks that are natively
compatible with the specific requirements of each connected peripheral. Multiple
Tx and Rx channels are provided within the DMA which allow multiple segmentation
or reassembly operations to be ongoing. The DMA controller maintains state
information for each of the channels which allows packet segmentation and
reassembly operations to be time division multiplexed between channels in order
to share the underlying DMA hardware. An external DMA scheduler is used to
control the ordering and rate at which this multiplexing occurs for Transmit
operations. The ordering and rate of Receive operations is indirectly controlled
by the order in which blocks are pushed into the DMA on the Rx PSI-L interface.
The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
channels. Channels in the UDMA-P can be configured to be either Packet-Based or
Third-Party channels on a channel by channel basis.
The initial driver supports:
- MEM_TO_MEM (TR mode)
- DEV_TO_MEM (Packet / TR mode)
- MEM_TO_DEV (Packet / TR mode)
- Cyclic (Packet / TR mode)
- Metadata for descriptors
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
dmaengine: ti: Add cppi5 header for UDMA
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
dt-bindings: dma: ti: Add document for K3 UDMA
New binding document for
Texas Instruments K3 NAVSS Unified DMA – Peripheral Root Complex (UDMA-P).
UDMA-P is introduced as part of the K3 architecture and can be found on
AM65x SoC.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
New binding document for
Texas Instruments K3 NAVSS Unified DMA – Peripheral Root Complex (UDMA-P).
UDMA-P is introduced as part of the K3 architecture and can be found on
AM65x SoC.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
dmaengine: Add function to request slave channel from a dma_device
dma_get_any_slave_channel() would skip using the filter function, which
in some cases needed to be executed before the alloc_chan_resources
callback to make sure that all parameters are provided for the slave
channel.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
dma_get_any_slave_channel() would skip using the filter function, which
in some cases needed to be executed before the alloc_chan_resources
callback to make sure that all parameters are provided for the slave
channel.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
dmaengine: Add support for reporting DMA cached data amount
A DMA hardware can have big cache or FIFO and the amount of data sitting in
the DMA fabric can be an interest for the clients.
For example in audio we want to know the delay in the data flow and in case
the DMA have significantly large FIFO/cache, it can affect the latenc/delay
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
A DMA hardware can have big cache or FIFO and the amount of data sitting in
the DMA fabric can be an interest for the clients.
For example in audio we want to know the delay in the data flow and in case
the DMA have significantly large FIFO/cache, it can affect the latenc/delay
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
dmaengine: Add metadata_ops for dma_async_tx_descriptor
The metadata is best described as side band data or parameters traveling
alongside the data DMAd by the DMA engine. It is data
which is understood by the peripheral and the peripheral driver only, the
DMA engine see it only as data block and it is not interpreting it in any
way.
The metadata can be different per descriptor as it is a parameter for the
data being transferred.
If the DMA supports per descriptor metadata it can implement the attach,
get_ptr/set_len callbacks.
Client drivers must only use either attach or get_ptr/set_len to avoid
misconfiguration.
Client driver can check if a given metadata mode is supported by the
channel during probe time with
dmaengine_is_metadata_mode_supported(chan, DESC_METADATA_CLIENT);
dmaengine_is_metadata_mode_supported(chan, DESC_METADATA_ENGINE);
and based on this information can use either mode.
Wrappers are also added for the metadata_ops.
To be used in DESC_METADATA_CLIENT mode:
dmaengine_desc_attach_metadata()
To be used in DESC_METADATA_ENGINE mode:
dmaengine_desc_get_metadata_ptr()
dmaengine_desc_set_metadata_len()
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
The metadata is best described as side band data or parameters traveling
alongside the data DMAd by the DMA engine. It is data
which is understood by the peripheral and the peripheral driver only, the
DMA engine see it only as data block and it is not interpreting it in any
way.
The metadata can be different per descriptor as it is a parameter for the
data being transferred.
If the DMA supports per descriptor metadata it can implement the attach,
get_ptr/set_len callbacks.
Client drivers must only use either attach or get_ptr/set_len to avoid
misconfiguration.
Client driver can check if a given metadata mode is supported by the
channel during probe time with
dmaengine_is_metadata_mode_supported(chan, DESC_METADATA_CLIENT);
dmaengine_is_metadata_mode_supported(chan, DESC_METADATA_ENGINE);
and based on this information can use either mode.
Wrappers are also added for the metadata_ops.
To be used in DESC_METADATA_CLIENT mode:
dmaengine_desc_attach_metadata()
To be used in DESC_METADATA_ENGINE mode:
dmaengine_desc_get_metadata_ptr()
dmaengine_desc_set_metadata_len()
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
dmaengine: doc: Add sections for per descriptor metadata support
Update the provider and client documentation with details about the
metadata support.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Update the provider and client documentation with details about the
metadata support.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
soc: ti: k3: add navss ringacc driver
The Ring Accelerator (RINGACC or RA) provides hardware acceleration to
enable straightforward passing of work between a producer and a consumer.
There is one RINGACC module per NAVSS on TI AM65x SoCs.
The RINGACC converts constant-address read and write accesses to equivalent
read or write accesses to a circular data structure in memory. The RINGACC
eliminates the need for each DMA controller which needs to access ring
elements from having to know the current state of the ring (base address,
current offset). The DMA controller performs a read or write access to a
specific address range (which maps to the source interface on the RINGACC)
and the RINGACC replaces the address for the transaction with a new address
which corresponds to the head or tail element of the ring (head for reads,
tail for writes). Since the RINGACC maintains the state, multiple DMA
controllers or channels are allowed to coherently share the same rings as
applicable. The RINGACC is able to place data which is destined towards
software into cached memory directly.
Supported ring modes:
- Ring Mode
- Messaging Mode
- Credentials Mode
- Queue Manager Mode
TI-SCI integration:
Texas Instrument's System Control Interface (TI-SCI) Message Protocol now
has control over Ringacc module resources management (RM) and Rings
configuration.
The corresponding support of TI-SCI Ringacc module RM protocol
introduced as option through DT parameters:
- ti,sci: phandle on TI-SCI firmware controller DT node
- ti,sci-dev-id: TI-SCI device identifier as per TI-SCI firmware spec
if both parameters present - Ringacc driver will configure/free/reset Rings
using TI-SCI Message Ringacc RM Protocol.
The Ringacc driver manages Rings allocation by itself now and requests
TI-SCI firmware to allocate and configure specific Rings only. It's done
this way because, Linux driver implements two stage Rings allocation and
configuration (allocate ring and configure ring) while I-SCI Message
Protocol supports only one combined operation (allocate+configure).
Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
The Ring Accelerator (RINGACC or RA) provides hardware acceleration to
enable straightforward passing of work between a producer and a consumer.
There is one RINGACC module per NAVSS on TI AM65x SoCs.
The RINGACC converts constant-address read and write accesses to equivalent
read or write accesses to a circular data structure in memory. The RINGACC
eliminates the need for each DMA controller which needs to access ring
elements from having to know the current state of the ring (base address,
current offset). The DMA controller performs a read or write access to a
specific address range (which maps to the source interface on the RINGACC)
and the RINGACC replaces the address for the transaction with a new address
which corresponds to the head or tail element of the ring (head for reads,
tail for writes). Since the RINGACC maintains the state, multiple DMA
controllers or channels are allowed to coherently share the same rings as
applicable. The RINGACC is able to place data which is destined towards
software into cached memory directly.
Supported ring modes:
- Ring Mode
- Messaging Mode
- Credentials Mode
- Queue Manager Mode
TI-SCI integration:
Texas Instrument's System Control Interface (TI-SCI) Message Protocol now
has control over Ringacc module resources management (RM) and Rings
configuration.
The corresponding support of TI-SCI Ringacc module RM protocol
introduced as option through DT parameters:
- ti,sci: phandle on TI-SCI firmware controller DT node
- ti,sci-dev-id: TI-SCI device identifier as per TI-SCI firmware spec
if both parameters present - Ringacc driver will configure/free/reset Rings
using TI-SCI Message Ringacc RM Protocol.
The Ringacc driver manages Rings allocation by itself now and requests
TI-SCI firmware to allocate and configure specific Rings only. It's done
this way because, Linux driver implements two stage Rings allocation and
configuration (allocate ring and configure ring) while I-SCI Message
Protocol supports only one combined operation (allocate+configure).
Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
bindings: soc: ti: add documentation for k3 ringacc
The Ring Accelerator (RINGACC or RA) provides hardware acceleration to
enable straightforward passing of work between a producer and a consumer.
There is one RINGACC module per NAVSS on TI AM65x SoCs.
This patch introduces RINGACC device tree bindings.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
The Ring Accelerator (RINGACC or RA) provides hardware acceleration to
enable straightforward passing of work between a producer and a consumer.
There is one RINGACC module per NAVSS on TI AM65x SoCs.
This patch introduces RINGACC device tree bindings.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
firmware: ti_sci: Add resource management APIs for ringacc, psi-l and udma
TISCI abstracts the management of NAVSS resources, like UDMA channels,
flows, rings.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
TISCI abstracts the management of NAVSS resources, like UDMA channels,
flows, rings.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
5 years agoMerge branch 'ti-linux-4.19.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel into... ti-rt-linux-4.14.y-next-20181128 ti-rt-linux-4.19.y-next-20181128
Merge branch 'ti-linux-4.19.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel into ti-rt-linux-4.19.y
TI-Feature: ti_linux_base_rt
TI-Tree: git@git.ti.com:ti-linux-kernel/ti-linux-kernel.git
TI-Branch: ti-linux-4.19.y
* 'ti-linux-4.19.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel: (36 commits)
ti_config_fragments: v8_baseport: enable K3 thermal
arm64: dts: ti: am6: Add VTM node
arm64: dts: ti: am654: Add thermal zones
thermal: k3: Add support for bandgap sensors
dt-bindings: thermal: k3: Add VTM bindings documentation
arm64: dts: ti: am654-base-board: Add gpio_keys node
arm64: configs: Enable GPIO_DAVINCI
arm64: dts: ti: am6: Add gpio nodes
gpio: Davinci: Add K3 Specific dependencies
gpio: davinci: Fix the compiler warning with ARM64 config enabled
arm64: dts: ti: k3-am654-base-board: Add I2C nodes
arm64: dts: ti: am654-base-board: Add pinmux for main uart0
arm64: dts: ti: k3-am65: Add pinctrl regions
dt-bindings: pinctrl: k3: Introduce pinmux definitions
arm64: dts: ti: am654: Add interrupt controller nodes
arm64: dts: ti: am654: Update compatible for dmsc
soc: ti: am6: Enable interrupt controller drivers
irqchip: ti-sci-inta: Add support for Interrupt Aggregator driver
dt-bindings: irqchip: Introduce TISCI Interrupt Aggregator bindings
irqchip: ti-sci-intr: Add support for Interrupt Router driver
...
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: ti_linux_base_rt
TI-Tree: git@git.ti.com:ti-linux-kernel/ti-linux-kernel.git
TI-Branch: ti-linux-4.19.y
* 'ti-linux-4.19.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel: (36 commits)
ti_config_fragments: v8_baseport: enable K3 thermal
arm64: dts: ti: am6: Add VTM node
arm64: dts: ti: am654: Add thermal zones
thermal: k3: Add support for bandgap sensors
dt-bindings: thermal: k3: Add VTM bindings documentation
arm64: dts: ti: am654-base-board: Add gpio_keys node
arm64: configs: Enable GPIO_DAVINCI
arm64: dts: ti: am6: Add gpio nodes
gpio: Davinci: Add K3 Specific dependencies
gpio: davinci: Fix the compiler warning with ARM64 config enabled
arm64: dts: ti: k3-am654-base-board: Add I2C nodes
arm64: dts: ti: am654-base-board: Add pinmux for main uart0
arm64: dts: ti: k3-am65: Add pinctrl regions
dt-bindings: pinctrl: k3: Introduce pinmux definitions
arm64: dts: ti: am654: Add interrupt controller nodes
arm64: dts: ti: am654: Update compatible for dmsc
soc: ti: am6: Enable interrupt controller drivers
irqchip: ti-sci-inta: Add support for Interrupt Aggregator driver
dt-bindings: irqchip: Introduce TISCI Interrupt Aggregator bindings
irqchip: ti-sci-intr: Add support for Interrupt Router driver
...
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
Merge branch 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree into ti-linux-4.19.y
TI-Feature: platform_base
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree: (36 commits)
ti_config_fragments: v8_baseport: enable K3 thermal
arm64: dts: ti: am6: Add VTM node
arm64: dts: ti: am654: Add thermal zones
thermal: k3: Add support for bandgap sensors
dt-bindings: thermal: k3: Add VTM bindings documentation
arm64: dts: ti: am654-base-board: Add gpio_keys node
arm64: configs: Enable GPIO_DAVINCI
arm64: dts: ti: am6: Add gpio nodes
gpio: Davinci: Add K3 Specific dependencies
gpio: davinci: Fix the compiler warning with ARM64 config enabled
arm64: dts: ti: k3-am654-base-board: Add I2C nodes
arm64: dts: ti: am654-base-board: Add pinmux for main uart0
arm64: dts: ti: k3-am65: Add pinctrl regions
dt-bindings: pinctrl: k3: Introduce pinmux definitions
arm64: dts: ti: am654: Add interrupt controller nodes
arm64: dts: ti: am654: Update compatible for dmsc
soc: ti: am6: Enable interrupt controller drivers
irqchip: ti-sci-inta: Add support for Interrupt Aggregator driver
dt-bindings: irqchip: Introduce TISCI Interrupt Aggregator bindings
irqchip: ti-sci-intr: Add support for Interrupt Router driver
...
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: platform_base
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree: (36 commits)
ti_config_fragments: v8_baseport: enable K3 thermal
arm64: dts: ti: am6: Add VTM node
arm64: dts: ti: am654: Add thermal zones
thermal: k3: Add support for bandgap sensors
dt-bindings: thermal: k3: Add VTM bindings documentation
arm64: dts: ti: am654-base-board: Add gpio_keys node
arm64: configs: Enable GPIO_DAVINCI
arm64: dts: ti: am6: Add gpio nodes
gpio: Davinci: Add K3 Specific dependencies
gpio: davinci: Fix the compiler warning with ARM64 config enabled
arm64: dts: ti: k3-am654-base-board: Add I2C nodes
arm64: dts: ti: am654-base-board: Add pinmux for main uart0
arm64: dts: ti: k3-am65: Add pinctrl regions
dt-bindings: pinctrl: k3: Introduce pinmux definitions
arm64: dts: ti: am654: Add interrupt controller nodes
arm64: dts: ti: am654: Update compatible for dmsc
soc: ti: am6: Enable interrupt controller drivers
irqchip: ti-sci-inta: Add support for Interrupt Aggregator driver
dt-bindings: irqchip: Introduce TISCI Interrupt Aggregator bindings
irqchip: ti-sci-intr: Add support for Interrupt Router driver
...
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
ti_config_fragments: v8_baseport: enable K3 thermal
K3 thermal driver is disabled by default, so enable it.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
K3 thermal driver is disabled by default, so enable it.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
arm64: dts: ti: am6: Add VTM node
VTM stands for voltage and thermal management. Add the vtm node and
the associated thermal zones on the SoC.
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
VTM stands for voltage and thermal management. Add the vtm node and
the associated thermal zones on the SoC.
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
arm64: dts: ti: am654: Add thermal zones
The am654 SoC has three thermal zones namely MPU0, MPU1 and MCU
zones
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
The am654 SoC has three thermal zones namely MPU0, MPU1 and MCU
zones
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
thermal: k3: Add support for bandgap sensors
Add support for bandgap sensors. Currently reading temperatures
and trend computing is supported.
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Add support for bandgap sensors. Currently reading temperatures
and trend computing is supported.
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
dt-bindings: thermal: k3: Add VTM bindings documentation
Add VTM bindings documentation. In the Voltage Thermal
Management Module(VTM), K3 AM654 supplies a voltage
reference and a temperature sensor feature that are gathered in the band
gap voltage and temperature sensor (VBGAPTS) module. The band
gap provides current and voltage reference for its internal
circuits and other analog IP blocks. The analog-to-digital
converter (ADC) produces an output value that is proportional
to the silicon temperature.
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Add VTM bindings documentation. In the Voltage Thermal
Management Module(VTM), K3 AM654 supplies a voltage
reference and a temperature sensor feature that are gathered in the band
gap voltage and temperature sensor (VBGAPTS) module. The band
gap provides current and voltage reference for its internal
circuits and other analog IP blocks. The analog-to-digital
converter (ADC) produces an output value that is proportional
to the silicon temperature.
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
arm64: dts: ti: am654-base-board: Add gpio_keys node
There are 2 push buttons: SW5 and SW6 that are basically connected to
WKUP_GPIO0_24 and WKUP_GPIO0_27 respectively. Add the respective
nodes and the pinctrl data to set the mode to GPIO and Input.
Signed-off-by: Keerthy <j-keerthy@ti.com>
There are 2 push buttons: SW5 and SW6 that are basically connected to
WKUP_GPIO0_24 and WKUP_GPIO0_27 respectively. Add the respective
nodes and the pinctrl data to set the mode to GPIO and Input.
Signed-off-by: Keerthy <j-keerthy@ti.com>
arm64: configs: Enable GPIO_DAVINCI
Enable GPIO_DAVINCI for K3 platforms.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Enable GPIO_DAVINCI for K3 platforms.
Signed-off-by: Keerthy <j-keerthy@ti.com>
arm64: dts: ti: am6: Add gpio nodes
Add gpio0 and gpio1 nodes under MAIN domain and gpio0
under WAKEUP domain.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add gpio0 and gpio1 nodes under MAIN domain and gpio0
under WAKEUP domain.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
gpio: Davinci: Add K3 Specific dependencies
Add K3 Specific dependencies
Signed-off-by: Keerthy <j-keerthy@ti.com>
Add K3 Specific dependencies
Signed-off-by: Keerthy <j-keerthy@ti.com>
gpio: davinci: Fix the compiler warning with ARM64 config enabled
Fix the compiler warning with ARM64 config enabled
Signed-off-by: Keerthy <j-keerthy@ti.com>
Fix the compiler warning with ARM64 config enabled
Signed-off-by: Keerthy <j-keerthy@ti.com>
arm64: dts: ti: k3-am654-base-board: Add I2C nodes
commit e5f4b4ba3d223426cdab582f5a67a841f2b01081 upstream
Add DT entries for I2C instances present in AM654 SoC.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
commit e5f4b4ba3d223426cdab582f5a67a841f2b01081 upstream
Add DT entries for I2C instances present in AM654 SoC.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
arm64: dts: ti: am654-base-board: Add pinmux for main uart0
commit 27e0e5f65dd05167283cf707ae89e19630b0289d upstream
Add pinmux for main uart0 that is serves as console on AM654 EVM
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
commit 27e0e5f65dd05167283cf707ae89e19630b0289d upstream
Add pinmux for main uart0 that is serves as console on AM654 EVM
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
arm64: dts: ti: k3-am65: Add pinctrl regions
commit ffff31e50509eaeea12df0ea2513fc648359b6bd upstream
Add pinctrl regions for the main and wkup mmr.
The range for main pinctrl region contains a gap
at offset 0x2e4, and because of this, the pinctrl
range is split into two sections.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
commit ffff31e50509eaeea12df0ea2513fc648359b6bd upstream
Add pinctrl regions for the main and wkup mmr.
The range for main pinctrl region contains a gap
at offset 0x2e4, and because of this, the pinctrl
range is split into two sections.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
dt-bindings: pinctrl: k3: Introduce pinmux definitions
commit 4d82c9ec96fd25cb4c126df2e14862df434ee185 upstream
The dt-bindings header for TI K3 AM6 SoCs define a set of macros for
defining pinmux configs in human readable form, instead of raw-coded
hex values.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
commit 4d82c9ec96fd25cb4c126df2e14862df434ee185 upstream
The dt-bindings header for TI K3 AM6 SoCs define a set of macros for
defining pinmux configs in human readable form, instead of raw-coded
hex values.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
arm64: dts: ti: am654: Add interrupt controller nodes
Add DT nodes for the interrupt routers and aggregators in the AM65x SoC.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Add DT nodes for the interrupt routers and aggregators in the AM65x SoC.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
arm64: dts: ti: am654: Update compatible for dmsc
Use the am654 specific compatible for dmsc. This allows to use
the am654 specific RM mapping table.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Use the am654 specific compatible for dmsc. This allows to use
the am654 specific RM mapping table.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
soc: ti: am6: Enable interrupt controller drivers
Select all the TISCI dependent interrupt controller drivers
for AM6 SoC.
Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Select all the TISCI dependent interrupt controller drivers
for AM6 SoC.
Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
irqchip: ti-sci-inta: Add support for Interrupt Aggregator driver
Texas Instruments' K3 generation SoCs has an IP Interrupt Aggregator
which is an interrupt controller that does the following:
- Converts events to interrupts that can be understood by
an interrupt router.
- Allows for multiplexing of events to interrupts.
- Allows for grouping of multiple events to a single interrupt.
Configuration of the interrupt aggregator registers can only be done by
a system co-processor and the driver needs to send a message to this
co processor over TISCI protocol.
Add support for Interrupt Aggregator driver over TISCI protocol.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Texas Instruments' K3 generation SoCs has an IP Interrupt Aggregator
which is an interrupt controller that does the following:
- Converts events to interrupts that can be understood by
an interrupt router.
- Allows for multiplexing of events to interrupts.
- Allows for grouping of multiple events to a single interrupt.
Configuration of the interrupt aggregator registers can only be done by
a system co-processor and the driver needs to send a message to this
co processor over TISCI protocol.
Add support for Interrupt Aggregator driver over TISCI protocol.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
dt-bindings: irqchip: Introduce TISCI Interrupt Aggregator bindings
Add the DT binding documentation for Interrupt Aggregator driver.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add the DT binding documentation for Interrupt Aggregator driver.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
irqchip: ti-sci-intr: Add support for Interrupt Router driver
Texas Instruments' K3 generation SoCs has an IP Interrupt Router
that does allows for multiplexing of input interrupts to host
interrupt controller. Interrupt Router inputs are either from a
peripheral or from an Interrupt Aggregator which is another
interrupt controller.
Configuration of the interrupt router registers can only be done by
a system co-processor and the driver needs to send a message to this
co processor over TISCI protocol.
Add support for Interrupt Router driver over TISCI protocol.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Texas Instruments' K3 generation SoCs has an IP Interrupt Router
that does allows for multiplexing of input interrupts to host
interrupt controller. Interrupt Router inputs are either from a
peripheral or from an Interrupt Aggregator which is another
interrupt controller.
Configuration of the interrupt router registers can only be done by
a system co-processor and the driver needs to send a message to this
co processor over TISCI protocol.
Add support for Interrupt Router driver over TISCI protocol.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
dt-bindings: irqchip: Introduce TISCI Interrupt router bindings
Add the DT binding documentation for Interrupt router driver.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add the DT binding documentation for Interrupt router driver.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
firmware: ti_sci: Add helper apis to manage resources
Each resource with in the device can be uniquely identified
by a type and subtype as defined by TISCI. Since this is generic
across the devices, resource allocation also can be made generic
instead of each client driver handling the resource. So add helper
apis to manage the resource.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Each resource with in the device can be uniquely identified
by a type and subtype as defined by TISCI. Since this is generic
across the devices, resource allocation also can be made generic
instead of each client driver handling the resource. So add helper
apis to manage the resource.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
firmware: ti_sci: Add RM mapping table for am654
Add the resource mapping table for AM654 SoC as defined
in http://downloads.ti.com/tisci/esd/latest/5_soc_doc/am6x/resasg_types.html
Introduce a new compatible for AM654 "ti,am654-sci" for using
this resource map table.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add the resource mapping table for AM654 SoC as defined
in http://downloads.ti.com/tisci/esd/latest/5_soc_doc/am6x/resasg_types.html
Introduce a new compatible for AM654 "ti,am654-sci" for using
this resource map table.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
firmware: ti_sci: Add support for IRQ management
TISCI abstracts the handling of IRQ routes where interrupt sources
are not directly connected to interrupt controller. Add support for
the set of TISCI commands for requesting and releasing IRQs.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
TISCI abstracts the handling of IRQ routes where interrupt sources
are not directly connected to interrupt controller. Add support for
the set of TISCI commands for requesting and releasing IRQs.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
firmware: ti_sci: Add support for RM core ops
TISCI provides support for getting the resources(IRQ, RING etc..)
assigned to a specific device. These resources can be handled by
the client and in turn sends TISCI cmd to configure the resources.
It is very important that client should keep track on usage of these
resources.
Add support for TISCI commands to get resource ranges.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
TISCI provides support for getting the resources(IRQ, RING etc..)
assigned to a specific device. These resources can be handled by
the client and in turn sends TISCI cmd to configure the resources.
It is very important that client should keep track on usage of these
resources.
Add support for TISCI commands to get resource ranges.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
firmware: ti_sci: Add support to get TISCI handle using of_phandle
TISCI has been updated to have support for Resource management(likes
interrupts etc..). And there can be multiple device instances of a
resource type in a SoC. So every driver corresponding to a resource type
should get a TISCI handle so that it can make TISCI calls. And each
DT node corresponding to a device should exist under its corresponding
bus node as per the SoC architecture.
But existing apis in TISCI library assumes that all TISCI users are
child nodes of TISCI. Which is not true in the above case. So introduce
(devm_)ti_sci_get_by_phandle() apis that can be used by TISCI users
to get TISCI handle using of phandle property.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
TISCI has been updated to have support for Resource management(likes
interrupts etc..). And there can be multiple device instances of a
resource type in a SoC. So every driver corresponding to a resource type
should get a TISCI handle so that it can make TISCI calls. And each
DT node corresponding to a device should exist under its corresponding
bus node as per the SoC architecture.
But existing apis in TISCI library assumes that all TISCI users are
child nodes of TISCI. Which is not true in the above case. So introduce
(devm_)ti_sci_get_by_phandle() apis that can be used by TISCI users
to get TISCI handle using of phandle property.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arm64: enable dtb overlay merging support based on configs provided
Add dtb-merger tool support to arm64 TI build. The merged configs are
defined by providing proper .its files.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add dtb-merger tool support to arm64 TI build. The merged configs are
defined by providing proper .its files.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
arm64: enable .dtbo file building for TI arm64 SoCs
Add support for building .dtso files into .dtbo binaries. Also change
the base .dtb files to contain symbols for overlay applying purposes.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add support for building .dtso files into .dtbo binaries. Also change
the base .dtb files to contain symbols for overlay applying purposes.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
ARM: dts: dt-overlays: add support for am57xx-evm
Add support for building FIT image for am57xx-evm. This FIT image
includes support for base am57xx-beagle boards (rev A2 and C) and
AM57xx-evm overlay.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add support for building FIT image for am57xx-evm. This FIT image
includes support for base am57xx-beagle boards (rev A2 and C) and
AM57xx-evm overlay.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
scripts/dtb-merge: add tool for merging DTB overlays
Add tool for merging DT overlays into single DTB file. This parses
all the available .its files to find out the configuration needed
for the DTB. Once matching config is found, passes the data
to fdtoverlay tool to merge everything into a single .dtb.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add tool for merging DT overlays into single DTB file. This parses
all the available .its files to find out the configuration needed
for the DTB. Once matching config is found, passes the data
to fdtoverlay tool to merge everything into a single .dtb.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
scripts/dtc: Bring in upstream version of fdtoverlay tool
Bring in upstream version v1.4.5.6-gc1e55a5513e9 of the fdtoverlay tool.
Copied over the fdtoverlay.c source as such, and updated the Makefile
to build the tool.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Bring in upstream version v1.4.5.6-gc1e55a5513e9 of the fdtoverlay tool.
Copied over the fdtoverlay.c source as such, and updated the Makefile
to build the tool.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
ARM: dts: dt-overlays: Add base support for DT overlay building
Add base support for DT overlay building for TI SoCs. Adds support
for building .dtso files into .dtbo, and building .its files into
.itb for FIT image support. Also, add new kernel build target for
building all available FIT images (make itbs.)
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add base support for DT overlay building for TI SoCs. Adds support
for building .dtso files into .dtbo, and building .its files into
.itb for FIT image support. Also, add new kernel build target for
building all available FIT images (make itbs.)
Signed-off-by: Tero Kristo <t-kristo@ti.com>
ARM: dts: dra76x: add support for OPP_PLUS
Add support for the OPP_PLUS (1.8GHz) for MPU.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add support for the OPP_PLUS (1.8GHz) for MPU.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
cpufreq: ti-cpufreq: Add support for OPP_PLUS
DRA762 SoC introduces OPP_PLUS which runs at 1.8GHz. Add
support for this OPP in ti-cpufreq driver.
Acked-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
DRA762 SoC introduces OPP_PLUS which runs at 1.8GHz. Add
support for this OPP in ti-cpufreq driver.
Acked-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
ti_config_fragments: omap_soc: enable RAS
Enable reliability, availability and serviceability kernel features.
This is needed as a dependency for EDAC.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Enable reliability, availability and serviceability kernel features.
This is needed as a dependency for EDAC.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
ARM: dts: am574x-idk: add support for EMIF1 ECC
EMIF1 has ECC support, so add the DT node with address and interrupt
details to handle this.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
EMIF1 has ECC support, so add the DT node with address and interrupt
details to handle this.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
5 years agoMerge branch 'ti-linux-4.19.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel into... ti-rt-linux-4.14.y-next-20181113 ti-rt-linux-4.14.y-next-20181114 ti-rt-linux-4.14.y-next-20181115 ti-rt-linux-4.14.y-next-20181116 ti-rt-linux-4.14.y-next-20181117 ti-rt-linux-4.14.y-next-20181118 ti-rt-linux-4.14.y-next-20181119 ti-rt-linux-4.14.y-next-20181120 ti-rt-linux-4.14.y-next-20181121 ti-rt-linux-4.14.y-next-20181122 ti-rt-linux-4.14.y-next-20181123 ti-rt-linux-4.14.y-next-20181124 ti-rt-linux-4.14.y-next-20181125 ti-rt-linux-4.14.y-next-20181126 ti-rt-linux-4.14.y-next-20181127 ti-rt-linux-4.19.y-next-20181113 ti-rt-linux-4.19.y-next-20181114 ti-rt-linux-4.19.y-next-20181115 ti-rt-linux-4.19.y-next-20181116 ti-rt-linux-4.19.y-next-20181117 ti-rt-linux-4.19.y-next-20181118 ti-rt-linux-4.19.y-next-20181119 ti-rt-linux-4.19.y-next-20181120 ti-rt-linux-4.19.y-next-20181121 ti-rt-linux-4.19.y-next-20181122 ti-rt-linux-4.19.y-next-20181123 ti-rt-linux-4.19.y-next-20181124 ti-rt-linux-4.19.y-next-20181125 ti-rt-linux-4.19.y-next-20181126 ti-rt-linux-4.19.y-next-20181127
Merge branch 'ti-linux-4.19.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel into ti-rt-linux-4.19.y
TI-Feature: ti_linux_base_rt
TI-Tree: git@git.ti.com:ti-linux-kernel/ti-linux-kernel.git
TI-Branch: ti-linux-4.19.y
* 'ti-linux-4.19.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel: (68 commits)
arm64: defconfig: Enable SERIAL_8250_OMAP
arm64: defconfig: Enable TI_SCI related configs
arm64: dts: ti: k3-am65-wakeup: Fix wakeup_uart reg address
arm64: dts: ti: k3-am6: Add Device Management Security Controller support
arm64: dts: ti: am654: Add secure proxy instance for main domain
arm64: dts: ti: am654: Add uart nodes
arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2
serial: 8250_omap: Make 8250_omap driver driver depend on ARCH_K3
clk: keystone: Enable TISCI clocks if K3_ARCH
drivers: mailbox: Make ti-msgmr driver depend on ARCH_K3
firmware: ti_sci: Provide host-id as an optional dt parameter
Documentation: dt: keystone: ti-sci: Add optional host-id parameter
MAINTAINERS: Drop dt-bindings/genpd/k2g.h
HACK: clocksource: kconfig: allow to select arm global timer manually
arm: dts: dra72-evm: Add interrupt parent for pcf_lcd
ARM: OMAP2+: sleep43xx: Call secure suspend/resume handlers
regulator: palmas: Disable bypass for ldo1 and ldo2
power: opp: ti-opp-supply: Correct the supply in _get_optimal_vdd_voltage call
power: opp: ti-opp-supply: Dynamically update u_volt_min
arm: dts: am57xx-idk-common: Hook smps12 regulator as cpu vdd-supply
...
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: ti_linux_base_rt
TI-Tree: git@git.ti.com:ti-linux-kernel/ti-linux-kernel.git
TI-Branch: ti-linux-4.19.y
* 'ti-linux-4.19.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel: (68 commits)
arm64: defconfig: Enable SERIAL_8250_OMAP
arm64: defconfig: Enable TI_SCI related configs
arm64: dts: ti: k3-am65-wakeup: Fix wakeup_uart reg address
arm64: dts: ti: k3-am6: Add Device Management Security Controller support
arm64: dts: ti: am654: Add secure proxy instance for main domain
arm64: dts: ti: am654: Add uart nodes
arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2
serial: 8250_omap: Make 8250_omap driver driver depend on ARCH_K3
clk: keystone: Enable TISCI clocks if K3_ARCH
drivers: mailbox: Make ti-msgmr driver depend on ARCH_K3
firmware: ti_sci: Provide host-id as an optional dt parameter
Documentation: dt: keystone: ti-sci: Add optional host-id parameter
MAINTAINERS: Drop dt-bindings/genpd/k2g.h
HACK: clocksource: kconfig: allow to select arm global timer manually
arm: dts: dra72-evm: Add interrupt parent for pcf_lcd
ARM: OMAP2+: sleep43xx: Call secure suspend/resume handlers
regulator: palmas: Disable bypass for ldo1 and ldo2
power: opp: ti-opp-supply: Correct the supply in _get_optimal_vdd_voltage call
power: opp: ti-opp-supply: Dynamically update u_volt_min
arm: dts: am57xx-idk-common: Hook smps12 regulator as cpu vdd-supply
...
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
Merge branch 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree into ti-linux-4.19.y
TI-Feature: platform_base
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree: (68 commits)
arm64: defconfig: Enable SERIAL_8250_OMAP
arm64: defconfig: Enable TI_SCI related configs
arm64: dts: ti: k3-am65-wakeup: Fix wakeup_uart reg address
arm64: dts: ti: k3-am6: Add Device Management Security Controller support
arm64: dts: ti: am654: Add secure proxy instance for main domain
arm64: dts: ti: am654: Add uart nodes
arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2
serial: 8250_omap: Make 8250_omap driver driver depend on ARCH_K3
clk: keystone: Enable TISCI clocks if K3_ARCH
drivers: mailbox: Make ti-msgmr driver depend on ARCH_K3
firmware: ti_sci: Provide host-id as an optional dt parameter
Documentation: dt: keystone: ti-sci: Add optional host-id parameter
MAINTAINERS: Drop dt-bindings/genpd/k2g.h
HACK: clocksource: kconfig: allow to select arm global timer manually
arm: dts: dra72-evm: Add interrupt parent for pcf_lcd
ARM: OMAP2+: sleep43xx: Call secure suspend/resume handlers
regulator: palmas: Disable bypass for ldo1 and ldo2
power: opp: ti-opp-supply: Correct the supply in _get_optimal_vdd_voltage call
power: opp: ti-opp-supply: Dynamically update u_volt_min
arm: dts: am57xx-idk-common: Hook smps12 regulator as cpu vdd-supply
...
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: platform_base
TI-Tree: git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree.git
TI-Branch: platform-ti-linux-4.19.y
* 'platform-ti-linux-4.19.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree: (68 commits)
arm64: defconfig: Enable SERIAL_8250_OMAP
arm64: defconfig: Enable TI_SCI related configs
arm64: dts: ti: k3-am65-wakeup: Fix wakeup_uart reg address
arm64: dts: ti: k3-am6: Add Device Management Security Controller support
arm64: dts: ti: am654: Add secure proxy instance for main domain
arm64: dts: ti: am654: Add uart nodes
arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2
serial: 8250_omap: Make 8250_omap driver driver depend on ARCH_K3
clk: keystone: Enable TISCI clocks if K3_ARCH
drivers: mailbox: Make ti-msgmr driver depend on ARCH_K3
firmware: ti_sci: Provide host-id as an optional dt parameter
Documentation: dt: keystone: ti-sci: Add optional host-id parameter
MAINTAINERS: Drop dt-bindings/genpd/k2g.h
HACK: clocksource: kconfig: allow to select arm global timer manually
arm: dts: dra72-evm: Add interrupt parent for pcf_lcd
ARM: OMAP2+: sleep43xx: Call secure suspend/resume handlers
regulator: palmas: Disable bypass for ldo1 and ldo2
power: opp: ti-opp-supply: Correct the supply in _get_optimal_vdd_voltage call
power: opp: ti-opp-supply: Dynamically update u_volt_min
arm: dts: am57xx-idk-common: Hook smps12 regulator as cpu vdd-supply
...
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
5 years agoMerge branch 'ti-linux-4.19.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel into... ti-rt-linux-4.14.y-next-20181110 ti-rt-linux-4.14.y-next-20181111 ti-rt-linux-4.14.y-next-20181112 ti-rt-linux-4.19.y-next-20181110 ti-rt-linux-4.19.y-next-20181111 ti-rt-linux-4.19.y-next-20181112
Merge branch 'ti-linux-4.19.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel into ti-rt-linux-4.19.y
TI-Feature: ti_linux_base_rt
TI-Tree: git@git.ti.com:ti-linux-kernel/ti-linux-kernel.git
TI-Branch: ti-linux-4.19.y
* 'ti-linux-4.19.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel:
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: ti_linux_base_rt
TI-Tree: git@git.ti.com:ti-linux-kernel/ti-linux-kernel.git
TI-Branch: ti-linux-4.19.y
* 'ti-linux-4.19.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel:
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
5 years agoMerge branch 'linux-4.19.y' of http://git.kernel.org/pub/scm/linux/kernel/git/stable... ti-linux-4.14.y-next-20181110 ti-linux-4.14.y-next-20181111 ti-linux-4.19.y-next-20181110 ti-linux-4.19.y-next-20181111
Merge branch 'linux-4.19.y' of http://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable into ti-linux-4.19.y
* 'linux-4.19.y' of http://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable: (25 commits)
Linux 4.19.1
net: bridge: remove ipv6 zero address check in mcast queries
sparc64: Wire up compat getpeername and getsockname.
sparc64: Make corrupted user stacks more debuggable.
sparc64: Export __node_distance.
sctp: check policy more carefully when getting pr status
Revert "be2net: remove desc field from be_eq_obj"
r8169: fix broken Wake-on-LAN from S5 (poweroff)
net: Properly unlink GRO packets on overflow.
net: drop skb on failure in ip_check_defrag()
mlxsw: core: Fix devlink unregister flow
mlxsw: spectrum_switchdev: Don't ignore deletions of learned MACs
net/smc: fix smc_buf_unuse to use the lgr pointer
net/ipv6: Allow onlink routes to have a device mismatch if it is the default route
openvswitch: Fix push/pop ethernet validation
bonding: fix length of actor system
vhost: Fix Spectre V1 vulnerability
rtnetlink: Disallow FDB configuration for non-Ethernet device
Revert "net: simplify sock_poll_wait"
net: udp: fix handling of CHECKSUM_COMPLETE packets
...
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
* 'linux-4.19.y' of http://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable: (25 commits)
Linux 4.19.1
net: bridge: remove ipv6 zero address check in mcast queries
sparc64: Wire up compat getpeername and getsockname.
sparc64: Make corrupted user stacks more debuggable.
sparc64: Export __node_distance.
sctp: check policy more carefully when getting pr status
Revert "be2net: remove desc field from be_eq_obj"
r8169: fix broken Wake-on-LAN from S5 (poweroff)
net: Properly unlink GRO packets on overflow.
net: drop skb on failure in ip_check_defrag()
mlxsw: core: Fix devlink unregister flow
mlxsw: spectrum_switchdev: Don't ignore deletions of learned MACs
net/smc: fix smc_buf_unuse to use the lgr pointer
net/ipv6: Allow onlink routes to have a device mismatch if it is the default route
openvswitch: Fix push/pop ethernet validation
bonding: fix length of actor system
vhost: Fix Spectre V1 vulnerability
rtnetlink: Disallow FDB configuration for non-Ethernet device
Revert "net: simplify sock_poll_wait"
net: udp: fix handling of CHECKSUM_COMPLETE packets
...
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
Merge branch 'linux-4.19.y-rt' of https://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel into ti-rt-linux-4.19.y
TI-Feature: linux_rt-4-19
TI-Tree: https://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git
TI-Branch: linux-4.19.y-rt
* 'linux-4.19.y-rt' of https://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel: (31 commits)
v4.19.1-rt3
rcu: make RCU_BOOST default on RT without EXPERT
ARM: at91: Update TCB timer patchset to v7
crypto: caam/qi - simplify CGR allocation, freeing
pinctrl: bcm2835: Use raw spinlock for RT compatibility
v4.19.1-rt2
Linux 4.19.1
net: bridge: remove ipv6 zero address check in mcast queries
sparc64: Wire up compat getpeername and getsockname.
sparc64: Make corrupted user stacks more debuggable.
sparc64: Export __node_distance.
sctp: check policy more carefully when getting pr status
Revert "be2net: remove desc field from be_eq_obj"
r8169: fix broken Wake-on-LAN from S5 (poweroff)
net: Properly unlink GRO packets on overflow.
net: drop skb on failure in ip_check_defrag()
mlxsw: core: Fix devlink unregister flow
mlxsw: spectrum_switchdev: Don't ignore deletions of learned MACs
net/smc: fix smc_buf_unuse to use the lgr pointer
net/ipv6: Allow onlink routes to have a device mismatch if it is the default route
...
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: linux_rt-4-19
TI-Tree: https://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git
TI-Branch: linux-4.19.y-rt
* 'linux-4.19.y-rt' of https://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel: (31 commits)
v4.19.1-rt3
rcu: make RCU_BOOST default on RT without EXPERT
ARM: at91: Update TCB timer patchset to v7
crypto: caam/qi - simplify CGR allocation, freeing
pinctrl: bcm2835: Use raw spinlock for RT compatibility
v4.19.1-rt2
Linux 4.19.1
net: bridge: remove ipv6 zero address check in mcast queries
sparc64: Wire up compat getpeername and getsockname.
sparc64: Make corrupted user stacks more debuggable.
sparc64: Export __node_distance.
sctp: check policy more carefully when getting pr status
Revert "be2net: remove desc field from be_eq_obj"
r8169: fix broken Wake-on-LAN from S5 (poweroff)
net: Properly unlink GRO packets on overflow.
net: drop skb on failure in ip_check_defrag()
mlxsw: core: Fix devlink unregister flow
mlxsw: spectrum_switchdev: Don't ignore deletions of learned MACs
net/smc: fix smc_buf_unuse to use the lgr pointer
net/ipv6: Allow onlink routes to have a device mismatch if it is the default route
...
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
v4.19.1-rt3
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
rcu: make RCU_BOOST default on RT without EXPERT
Paul E. McKenney suggested to allow enabling RCU_BOOST on RT without the
need to go through the EXPERT option first.
Suggeted-by: Paul E. McKenney <paulmck@linux.ibm.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Paul E. McKenney suggested to allow enabling RCU_BOOST on RT without the
need to go through the EXPERT option first.
Suggeted-by: Paul E. McKenney <paulmck@linux.ibm.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
ARM: at91: Update TCB timer patchset to v7
This is an update to the v7 of the TCB timer patch set as posted by
Alexandre Belloni on Wed, 18 Apr 2018 12:51:38.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
This is an update to the v7 of the TCB timer patch set as posted by
Alexandre Belloni on Wed, 18 Apr 2018 12:51:38.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
crypto: caam/qi - simplify CGR allocation, freeing
[Upstream commit 29e83c757006fd751966bdc53392bb22d74179c6]
CGRs (Congestion Groups) have to be freed by the same CPU that
initialized them.
This is why currently the driver takes special measures; however, using
set_cpus_allowed_ptr() is incorrect - as reported by Sebastian.
Instead of the generic solution of replacing set_cpus_allowed_ptr() with
work_on_cpu_safe(), we use the qman_delete_cgr_safe() QBMan API instead
of qman_delete_cgr() - which internally takes care of proper CGR
deletion.
Link: https://lkml.kernel.org/r/20181005125443.dfhd2asqktm22ney@linutronix.de
Reported-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
[Upstream commit 29e83c757006fd751966bdc53392bb22d74179c6]
CGRs (Congestion Groups) have to be freed by the same CPU that
initialized them.
This is why currently the driver takes special measures; however, using
set_cpus_allowed_ptr() is incorrect - as reported by Sebastian.
Instead of the generic solution of replacing set_cpus_allowed_ptr() with
work_on_cpu_safe(), we use the qman_delete_cgr_safe() QBMan API instead
of qman_delete_cgr() - which internally takes care of proper CGR
deletion.
Link: https://lkml.kernel.org/r/20181005125443.dfhd2asqktm22ney@linutronix.de
Reported-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
pinctrl: bcm2835: Use raw spinlock for RT compatibility
[Upstream commit 71dfaa749f2f7c1722ebf6716d3f797a04528cba]
The BCM2835 pinctrl driver acquires a spinlock in its ->irq_enable,
->irq_disable and ->irq_set_type callbacks. Spinlocks become sleeping
locks with CONFIG_PREEMPT_RT_FULL=y, therefore invocation of one of the
callbacks in atomic context may cause a hard lockup if at least two GPIO
pins in the same bank are used as interrupts. The issue doesn't occur
with just a single interrupt pin per bank because the lock is never
contended. I'm experiencing such lockups with GPIO 8 and 28 used as
level-triggered interrupts, i.e. with ->irq_disable being invoked on
reception of every IRQ.
The critical section protected by the spinlock is very small (one bitop
and one RMW of an MMIO register), hence converting to a raw spinlock
seems a better trade-off than converting the driver to threaded IRQ
handling (which would increase latency to handle an interrupt).
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Acked-by: Julia Cartwright <julia@ni.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
[Upstream commit 71dfaa749f2f7c1722ebf6716d3f797a04528cba]
The BCM2835 pinctrl driver acquires a spinlock in its ->irq_enable,
->irq_disable and ->irq_set_type callbacks. Spinlocks become sleeping
locks with CONFIG_PREEMPT_RT_FULL=y, therefore invocation of one of the
callbacks in atomic context may cause a hard lockup if at least two GPIO
pins in the same bank are used as interrupts. The issue doesn't occur
with just a single interrupt pin per bank because the lock is never
contended. I'm experiencing such lockups with GPIO 8 and 28 used as
level-triggered interrupts, i.e. with ->irq_disable being invoked on
reception of every IRQ.
The critical section protected by the spinlock is very small (one bitop
and one RMW of an MMIO register), hence converting to a raw spinlock
seems a better trade-off than converting the driver to threaded IRQ
handling (which would increase latency to handle an interrupt).
Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Acked-by: Julia Cartwright <julia@ni.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
arm64: defconfig: Enable SERIAL_8250_OMAP
commit d59c774496a2ee824836aaee1975ed23577edfd1 upstream
Enabling CONFIG_SERIAL_8250_OMAP that is used by TI's
AM6 SoC.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Nishanth Menon <nm@ti.com>
commit d59c774496a2ee824836aaee1975ed23577edfd1 upstream
Enabling CONFIG_SERIAL_8250_OMAP that is used by TI's
AM6 SoC.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Nishanth Menon <nm@ti.com>
arm64: defconfig: Enable TI_SCI related configs
commit 41925a21cdb58d07d6cad4f30539d1cee7a25d7b upstream
Enable TI System Control Interface (TI_SCI) Message Protocol library
and it's relevant power management drivers using this library.
TI's AM6 SoC uses this TI_SCI library to communicate to its system
controller(DMSC). While at it, enable TI_MESSAGE_MANAGER mailbox driver
using which this communication happens.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Nishanth Menon <nm@ti.com>
commit 41925a21cdb58d07d6cad4f30539d1cee7a25d7b upstream
Enable TI System Control Interface (TI_SCI) Message Protocol library
and it's relevant power management drivers using this library.
TI's AM6 SoC uses this TI_SCI library to communicate to its system
controller(DMSC). While at it, enable TI_MESSAGE_MANAGER mailbox driver
using which this communication happens.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Nishanth Menon <nm@ti.com>
arm64: dts: ti: k3-am65-wakeup: Fix wakeup_uart reg address
Upstream post: https://patchwork.kernel.org/patch/10617217/
cbass_wakeup interconnect which is the parent of wakeup_uart node
defines address-cells=1 and size-cells=1, therefore fix up reg property
of wakeup_uart node accordingly. Otherwise, this UART instance fails to
probe if enabled.
Fixes: 4201af2544b3 ("arm64: dts: ti: am654: Add uart nodes")
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Upstream post: https://patchwork.kernel.org/patch/10617217/
cbass_wakeup interconnect which is the parent of wakeup_uart node
defines address-cells=1 and size-cells=1, therefore fix up reg property
of wakeup_uart node accordingly. Otherwise, this UART instance fails to
probe if enabled.
Fixes: 4201af2544b3 ("arm64: dts: ti: am654: Add uart nodes")
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
arm64: dts: ti: k3-am6: Add Device Management Security Controller support
commit 42e54f6467ecc25f464d74c0fcea0c9fab1c2e3b upstream
Add TISCI compatible System controller for AM6 SoCs.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
commit 42e54f6467ecc25f464d74c0fcea0c9fab1c2e3b upstream
Add TISCI compatible System controller for AM6 SoCs.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
arm64: dts: ti: am654: Add secure proxy instance for main domain
commit 77ccbae4f9c8a14d41cb741f1d0a99dee68539fc upstream
Add secure proxy instance for Main domain
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
commit 77ccbae4f9c8a14d41cb741f1d0a99dee68539fc upstream
Add secure proxy instance for Main domain
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
arm64: dts: ti: am654: Add uart nodes
commit 4201af2544b39782d78ca1d4d59908e3b2502333 upstream
Add uart nodes for AM654 device tree components.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
commit 4201af2544b39782d78ca1d4d59908e3b2502333 upstream
Add uart nodes for AM654 device tree components.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2
commit 3bc1572068e3896b60d86f9c0fb56d1cef28201c upstream
AM65 has two PCIe controllers and each PCIe controller has '2' address
spaces one within the 4GB address space of the SoC and the other above
the 4GB address space of the SoC (cbass_main) in addition to the
register space. The size of the address space above the 4GB SoC address
space is 4GB. These address ranges will be used by CPU/DMA to access
the PCIe address space. In order to represent the address space above
the 4GB SoC address space and to represent the size of this address
space as 4GB, change address-cells and size-cells of interconnect to 2.
Since OSPI has similar need in MCU Domain Memory Map, change
address-cells and size-cells of cbass_mcu interconnect also to 2.
Fixes: ea47eed33a3fe3d919 ("arm64: dts: ti: Add Support for AM654 SoC")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Vignesh R <vigneshr@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
commit 3bc1572068e3896b60d86f9c0fb56d1cef28201c upstream
AM65 has two PCIe controllers and each PCIe controller has '2' address
spaces one within the 4GB address space of the SoC and the other above
the 4GB address space of the SoC (cbass_main) in addition to the
register space. The size of the address space above the 4GB SoC address
space is 4GB. These address ranges will be used by CPU/DMA to access
the PCIe address space. In order to represent the address space above
the 4GB SoC address space and to represent the size of this address
space as 4GB, change address-cells and size-cells of interconnect to 2.
Since OSPI has similar need in MCU Domain Memory Map, change
address-cells and size-cells of cbass_mcu interconnect also to 2.
Fixes: ea47eed33a3fe3d919 ("arm64: dts: ti: Add Support for AM654 SoC")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Vignesh R <vigneshr@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
serial: 8250_omap: Make 8250_omap driver driver depend on ARCH_K3
commit c886751465b8e312389d91446b76a00f45a79276 upstream
Allow 8250 omap serial driver to be used for K3 platforms.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit c886751465b8e312389d91446b76a00f45a79276 upstream
Allow 8250 omap serial driver to be used for K3 platforms.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
clk: keystone: Enable TISCI clocks if K3_ARCH
commit 2f149e6e14bcb5e581e49307b54aafcd6f74a74f upstream
K3_ARCH uses TISCI for clocks as well. Enable the same
for the driver support.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
commit 2f149e6e14bcb5e581e49307b54aafcd6f74a74f upstream
K3_ARCH uses TISCI for clocks as well. Enable the same
for the driver support.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers: mailbox: Make ti-msgmr driver depend on ARCH_K3
commit cfc0f7a8ea807bf318a1aa755a6a03d469e02725 upstream
ti-msgmr driver can support K3 platforms as well.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
commit cfc0f7a8ea807bf318a1aa755a6a03d469e02725 upstream
ti-msgmr driver can support K3 platforms as well.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
firmware: ti_sci: Provide host-id as an optional dt parameter
commit e69a35531589a2d3c746b0491d5ad3f77b6a0125 upstream
Texas Instrument's System Control Interface (TISCI) permits the
ability for Operating Systems to running in virtual machines to be
able to independently communicate with the firmware without the need
going through an hypervisor.
The "host-id" in effect is the hardware representation of the
host (example: VMs locked to a core) as identified to the System
Controller.
Provide support as an optional parameter implementation and use the
compatible data as default if one is not provided by device tree.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
commit e69a35531589a2d3c746b0491d5ad3f77b6a0125 upstream
Texas Instrument's System Control Interface (TISCI) permits the
ability for Operating Systems to running in virtual machines to be
able to independently communicate with the firmware without the need
going through an hypervisor.
The "host-id" in effect is the hardware representation of the
host (example: VMs locked to a core) as identified to the System
Controller.
Provide support as an optional parameter implementation and use the
compatible data as default if one is not provided by device tree.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
Documentation: dt: keystone: ti-sci: Add optional host-id parameter
commit 79a79c3a0ec2043711577750d4499abf4155d216 upstream
Texas Instrument's System Control Interface (TISCI) permits
the ability for OSs running in virtual machines to be able to
independently communicate with the firmware without the need going
through an hypervisor.
The "host-id" in effect is the hardware representation of the
host (example: VMs locked to a core) as identified to the System
Controller. Hypervisors can either fill in appropriate host-ids in dt
used for each VM instance OR may use prebuilt blobs where the host-ids
are pre-populated, as appropriate for the OS running in the VMs.
This is introduced as an optional parameter to maintain consistency
with legacy device tree blobs.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
commit 79a79c3a0ec2043711577750d4499abf4155d216 upstream
Texas Instrument's System Control Interface (TISCI) permits
the ability for OSs running in virtual machines to be able to
independently communicate with the firmware without the need going
through an hypervisor.
The "host-id" in effect is the hardware representation of the
host (example: VMs locked to a core) as identified to the System
Controller. Hypervisors can either fill in appropriate host-ids in dt
used for each VM instance OR may use prebuilt blobs where the host-ids
are pre-populated, as appropriate for the OS running in the VMs.
This is introduced as an optional parameter to maintain consistency
with legacy device tree blobs.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
MAINTAINERS: Drop dt-bindings/genpd/k2g.h
commit 8abac18fecbd3e6694583227d9b5f337e397f942 upstream.
Drop include/dt-bindings/genpd/k2g.h which disappeared from kernel tree
some time back, however MAINTAINERS file was missed to be updated.
Fixes: d16645054d2f ("dt-bindings: Drop k2g genpd device ID macros")
Cc: Rob Herring <robh@kernel.org>
Cc: Dave Gerlach <d-gerlach@ti.com>
Cc: Santosh Shilimkar <ssantosh@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Reported-by: Joe Perches <joe@perches.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
commit 8abac18fecbd3e6694583227d9b5f337e397f942 upstream.
Drop include/dt-bindings/genpd/k2g.h which disappeared from kernel tree
some time back, however MAINTAINERS file was missed to be updated.
Fixes: d16645054d2f ("dt-bindings: Drop k2g genpd device ID macros")
Cc: Rob Herring <robh@kernel.org>
Cc: Dave Gerlach <d-gerlach@ti.com>
Cc: Santosh Shilimkar <ssantosh@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Reported-by: Joe Perches <joe@perches.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
v4.19.1-rt2
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Merge tag 'v4.19.1' into linux-4.19.y-rt
This is the 4.19.1 stable release
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
This is the 4.19.1 stable release
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
HACK: clocksource: kconfig: allow to select arm global timer manually
This patch changes definition of ARM_GLOBAL_TIMER so it can be
enabled manually. This is required because ARM Global timer
has some limitations:
- It is not always-on timer on am437x and it can't be
used as clocksource device if CPU_IDLE=y
- It doesn't support CPUfreq now
which can't be resolved properly by using kconfig dependencies
in case of multiplatform build.
For example, ARM_GLOBAL_TIMER can't be selected by default
for TI AM437x SOC, because it expected to support cpuidle
and cpufreq in multiplatform build from one side. From
another side - will cpuidle and cpufreq really work depends
not only from kconfig options, but also from PM driver
which has to be loaded.
LKML version:
https://patchwork.ozlabs.org/patch/579071/
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
This patch changes definition of ARM_GLOBAL_TIMER so it can be
enabled manually. This is required because ARM Global timer
has some limitations:
- It is not always-on timer on am437x and it can't be
used as clocksource device if CPU_IDLE=y
- It doesn't support CPUfreq now
which can't be resolved properly by using kconfig dependencies
in case of multiplatform build.
For example, ARM_GLOBAL_TIMER can't be selected by default
for TI AM437x SOC, because it expected to support cpuidle
and cpufreq in multiplatform build from one side. From
another side - will cpuidle and cpufreq really work depends
not only from kconfig options, but also from PM driver
which has to be loaded.
LKML version:
https://patchwork.ozlabs.org/patch/579071/
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
arm: dts: dra72-evm: Add interrupt parent for pcf_lcd
On dra72-evm boards, pcf_lcd GPIO expander's interrupt lines
are connected to SoC GPIO as following
GPIO3_30 for dra72-evm
GPIO6_11 for dra72-evm-revc
Add the interrupt-parent property to correctly describe this.
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
On dra72-evm boards, pcf_lcd GPIO expander's interrupt lines
are connected to SoC GPIO as following
GPIO3_30 for dra72-evm
GPIO6_11 for dra72-evm-revc
Add the interrupt-parent property to correctly describe this.
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
ARM: OMAP2+: sleep43xx: Call secure suspend/resume handlers
During suspend CPU context may be lost in both non-secure and secure CPU
states. The kernel can handle saving and restoring the non-secure context
but must call into the secure side to allow it to save any context it may
lose. Add these calls here.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Dave Gerlach <d-gerlach@ti.com>
During suspend CPU context may be lost in both non-secure and secure CPU
states. The kernel can handle saving and restoring the non-secure context
but must call into the secure side to allow it to save any context it may
lose. Add these calls here.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Dave Gerlach <d-gerlach@ti.com>
regulator: palmas: Disable bypass for ldo1 and ldo2
ldo1 and ldo2 have bypass capability. The regulator framework starts
with assuming that bypass is disabled by default. In this particular
case the bypass OTP is 1. So one cannot disable without first enabling
due to the use count going negative. Hence doing a one time disable at
boot.
Any consumer which wants bypass to be enabled/disabled can use the
bypass_enable/bypass_disable functions to turn on or turn off bypass
subsequently.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
ldo1 and ldo2 have bypass capability. The regulator framework starts
with assuming that bypass is disabled by default. In this particular
case the bypass OTP is 1. So one cannot disable without first enabling
due to the use count going negative. Hence doing a one time disable at
boot.
Any consumer which wants bypass to be enabled/disabled can use the
bypass_enable/bypass_disable functions to turn on or turn off bypass
subsequently.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
power: opp: ti-opp-supply: Correct the supply in _get_optimal_vdd_voltage call
_get_optimal_vdd_voltage call provides new_supply_vbb->u_volt
as the reference voltage while it should be really new_supply_vdd->u_volt.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Acked-by: Dave Gerlach <d-gerlach@ti.com>
_get_optimal_vdd_voltage call provides new_supply_vbb->u_volt
as the reference voltage while it should be really new_supply_vdd->u_volt.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Acked-by: Dave Gerlach <d-gerlach@ti.com>
power: opp: ti-opp-supply: Dynamically update u_volt_min
The voltage range (min, max) provided in the device tree is from
the data manual and is pretty big, catering to a wide range of devices.
On a i2c read/write failure the regulator_set_voltage_triplet function
falls back to set voltage between min and max. The min value from Device
Tree can be lesser than the optimal value and in that case that can lead
to a hang or crash. Hence set the u_volt_min dynamically to the optimal
voltage value.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Acked-by: Dave Gerlach <d-gerlach@ti.com>
The voltage range (min, max) provided in the device tree is from
the data manual and is pretty big, catering to a wide range of devices.
On a i2c read/write failure the regulator_set_voltage_triplet function
falls back to set voltage between min and max. The min value from Device
Tree can be lesser than the optimal value and in that case that can lead
to a hang or crash. Hence set the u_volt_min dynamically to the optimal
voltage value.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Acked-by: Dave Gerlach <d-gerlach@ti.com>
arm: dts: am57xx-idk-common: Hook smps12 regulator as cpu vdd-supply
commit 5c8a6b9db5e95ea7702ef8d4bb1438537ef63594 upstream
am574x-idk has no cpu vdd-supply at the moment. Hence hook smps12
regulator as cpu vdd-supply in am57xx-idk-common as the same regulator
feeds on to cpu on am571/2/4-idks. So remove all the individual
instances and place that in common place.
Signed-off-by: Keerthy <j-keerthy@ti.com>
commit 5c8a6b9db5e95ea7702ef8d4bb1438537ef63594 upstream
am574x-idk has no cpu vdd-supply at the moment. Hence hook smps12
regulator as cpu vdd-supply in am57xx-idk-common as the same regulator
feeds on to cpu on am571/2/4-idks. So remove all the individual
instances and place that in common place.
Signed-off-by: Keerthy <j-keerthy@ti.com>
ARM: dts: am437x-gp-evm: Add sleep state for beeper pins
Add sleep state for beeper pins. Without this there was a power
increase during the suspend and standby states on V3_3D domain.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Add sleep state for beeper pins. Without this there was a power
increase during the suspend and standby states on V3_3D domain.
Signed-off-by: Keerthy <j-keerthy@ti.com>
ARM: dts: am335x: Add rtc node as system-power-controller
PMIC_PWR_EN pin of RTC on am335x-evm, bone, and boneblack is connected to
PMIC on board, so flag rtc node as system-power-controller to allow
software to poweroff boards.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
PMIC_PWR_EN pin of RTC on am335x-evm, bone, and boneblack is connected to
PMIC on board, so flag rtc node as system-power-controller to allow
software to poweroff boards.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
HACK: arm: keystone: add outer shareable attribute for pages/sections
On KS2 devices pages/sections to be used for DMA must have "outer
shareable" attribute. In the upstream kernel, ARM v7 supports only
"inner shareable attribute". This means all memory requests for pages
that are marked inner shareable in the page tables and are writeback
cacheable will be coherent in all caches at the inner domain. However
in Keystone, these are to be marked as "outer shareable" as the keystone
dma coherency hardware implementation use this feature to listen to
maintenance snoop messages to make it coherent with DMA masters. For more
details, please refer to the ARM TRM and Keystone device user guides [1].
[1] MSMC user guide, document id spruhj6
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
On KS2 devices pages/sections to be used for DMA must have "outer
shareable" attribute. In the upstream kernel, ARM v7 supports only
"inner shareable attribute". This means all memory requests for pages
that are marked inner shareable in the page tables and are writeback
cacheable will be coherent in all caches at the inner domain. However
in Keystone, these are to be marked as "outer shareable" as the keystone
dma coherency hardware implementation use this feature to listen to
maintenance snoop messages to make it coherent with DMA masters. For more
details, please refer to the ARM TRM and Keystone device user guides [1].
[1] MSMC user guide, document id spruhj6
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
ARM: dts: keystone-k2g: add timer1 as clocksource
Add timer1 node as the clocksource.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add timer1 node as the clocksource.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
clocksource: timer-keystone: Add platform probe support to existing code
This patch fixes the case for k2g where in clocks are not
available at the time of keystone_timer_init function call.
K2HK/K2L/K2E devices are left untouched and the old way of
keystone_timer_init is preserved since it is init order sensitive.
On top of the existing code a platform driver is introduced so that
if clock is not yet ready probe can be deferred. This enables hres
timers for k2g.
Signed-off-by: Keerthy <j-keerthy@ti.com>
This patch fixes the case for k2g where in clocks are not
available at the time of keystone_timer_init function call.
K2HK/K2L/K2E devices are left untouched and the old way of
keystone_timer_init is preserved since it is init order sensitive.
On top of the existing code a platform driver is introduced so that
if clock is not yet ready probe can be deferred. This enables hres
timers for k2g.
Signed-off-by: Keerthy <j-keerthy@ti.com>
HACK: ARM: smccc-call: Use r12 to route secure monitor calls
Our ROM Secure Monitor(SM) uses the value in r12 to determine which
service is being requested by an SMC call. This goes against he ARM
recommended SMC Calling Convention(SMCCC), which partitions the values
in R0 for this task, OP-TEE's SM follows the ARM recommended convention.
We need a way to signal that a call is for our new SM and not for
the ROM SM in a way that is safe for the ROM SM, in case OP-TEE is
not installed. We do this by putting a value of 0x200 in r12 when the
call is for OP-TEE by modifying the SMCCC caller function.
There are four combinations of events:
If the ROM SM is present and we make a legacy style SMC call, as we
do in early boot, the call will not have r12 set to 0x200 as these
calls go through existing mach-omap2/ SMC handlers, so all is well.
If the ROM SM is present and we make an SMCCC style call, r12 will be
set to 0x200 and ROM SM will see this as an invalid service call and
safely return to the normal world. This should not happen.
If OP-TEE is present and we make a legacy style SMC call, r12 will
not be set to 0x200, and OP-TEE will emulate the functionality that
the call is requesting.
If OP-TEE is present and we make an SMCCC style call, r12 is checked
and as it will be 0x200 we can ignore it and treat the rest of the
registers in the standard SMCCC way.
Using a TI specific calling convention was rejected upstream[0], the
suggested solution was to change all legacy calls to perform runtime
switching based on the DT OP-TEE, this is not a reasonable solution
given how many platforms would be affected, so we will have to keep
this non-upstreamable HACK for now.
[0] https://patchwork.kernel.org/patch/9957687/
Signed-off-by: Harinarayan Bhatta <harinarayan@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Our ROM Secure Monitor(SM) uses the value in r12 to determine which
service is being requested by an SMC call. This goes against he ARM
recommended SMC Calling Convention(SMCCC), which partitions the values
in R0 for this task, OP-TEE's SM follows the ARM recommended convention.
We need a way to signal that a call is for our new SM and not for
the ROM SM in a way that is safe for the ROM SM, in case OP-TEE is
not installed. We do this by putting a value of 0x200 in r12 when the
call is for OP-TEE by modifying the SMCCC caller function.
There are four combinations of events:
If the ROM SM is present and we make a legacy style SMC call, as we
do in early boot, the call will not have r12 set to 0x200 as these
calls go through existing mach-omap2/ SMC handlers, so all is well.
If the ROM SM is present and we make an SMCCC style call, r12 will be
set to 0x200 and ROM SM will see this as an invalid service call and
safely return to the normal world. This should not happen.
If OP-TEE is present and we make a legacy style SMC call, r12 will
not be set to 0x200, and OP-TEE will emulate the functionality that
the call is requesting.
If OP-TEE is present and we make an SMCCC style call, r12 is checked
and as it will be 0x200 we can ignore it and treat the rest of the
registers in the standard SMCCC way.
Using a TI specific calling convention was rejected upstream[0], the
suggested solution was to change all legacy calls to perform runtime
switching based on the DT OP-TEE, this is not a reasonable solution
given how many platforms would be affected, so we will have to keep
this non-upstreamable HACK for now.
[0] https://patchwork.kernel.org/patch/9957687/
Signed-off-by: Harinarayan Bhatta <harinarayan@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
ARM: dts: am437x-gp-evm: Add pinmux for gpio0 wake
Add pinctrl settings so that gpio0 wake from suspend will be supported
using buttons SW4 and SW7. Also, add pinctrl configuration for 0x954,
spi0_d0, which is an unused pin brought out to a header on the board
that in it's default state also connects to the gpio used for wakeup,
gpio0_3, which affects the state of the pin and prevents a working
wakeup unless we set the mux to a different state.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Add pinctrl settings so that gpio0 wake from suspend will be supported
using buttons SW4 and SW7. Also, add pinctrl configuration for 0x954,
spi0_d0, which is an unused pin brought out to a header on the board
that in it's default state also connects to the gpio used for wakeup,
gpio0_3, which affects the state of the pin and prevents a working
wakeup unless we set the mux to a different state.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
ARM: dts: am437x-gp-evm: Add uart0 pinctrl default and sleep states
Currently uart0 uses pinctrl config set by bootloader so
create default state that can be restored after a suspend
event.
Also, modify uart0 pinctrl to include RTS and CTS pins as by
default these are not in a mode for optimal power savings.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Currently uart0 uses pinctrl config set by bootloader so
create default state that can be restored after a suspend
event.
Also, modify uart0 pinctrl to include RTS and CTS pins as by
default these are not in a mode for optimal power savings.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
ARM: dts: am437x-gp-evm: Add pinctrl for debugss pins
The pins used by debugss are not configued by default, place pulldowns
on the pins for maximum power savings during sleep.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[t-kristo@ti.com: converted to use AM4372_IOPAD macro]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The pins used by debugss are not configued by default, place pulldowns
on the pins for maximum power savings during sleep.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[t-kristo@ti.com: converted to use AM4372_IOPAD macro]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
ARM: dts: am437x-gp-evm: Add pinctrl for unused_pins
There are several pins on this EVM that are not in use but they can
still draw power if misconfigured. Create a pinctrl entry for these pins
and configure each one for optimal power savings.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[t-kristo@ti.com: converted to use AM4372_IOPAD macro]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
There are several pins on this EVM that are not in use but they can
still draw power if misconfigured. Create a pinctrl entry for these pins
and configure each one for optimal power savings.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[t-kristo@ti.com: converted to use AM4372_IOPAD macro]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
ARM: OMAP2+: am43xx: Add lcdc clockdomain
As described in AM437x TRM, spruhl7f, Revised September 2016, there is
an LCDC clockdomain present in the PER power domain. Although it is
entirely unused on AM437x, it should be defined along with the other
clockdomains so it can be shut off by Linux as there are no users.
Reported-by: Munan Xu <munan@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
As described in AM437x TRM, spruhl7f, Revised September 2016, there is
an LCDC clockdomain present in the PER power domain. Although it is
entirely unused on AM437x, it should be defined along with the other
clockdomains so it can be shut off by Linux as there are no users.
Reported-by: Munan Xu <munan@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
ARM: OMAP2+: timer: Extend pending interrupt ACK for gic
The current implementation for preventing timer interrupts from
breaking suspend fully fixes the issue on am335x but the GIC present on
am437x cannot be directly acked using only the irqchip calls as is done
for am335x but requires an additional step.
Calling irqchip->irq_eoi only writes to the GIC_CPU_EOI register but for
an interrupt to be properly cleared by the GIC, a read from
GIC_CPU_INTACK must come first. The only place the irq-gic driver reads
this is in the actual interrupt handler so we cannot access it from the
driver.
To get around this, let's map the GIC_CPU_BASE and read the
GIC_CPU_INTACK register ourselves before calling irq_eoi to properly ack
late timer interrupts that show up during suspend on am437x.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
The current implementation for preventing timer interrupts from
breaking suspend fully fixes the issue on am335x but the GIC present on
am437x cannot be directly acked using only the irqchip calls as is done
for am335x but requires an additional step.
Calling irqchip->irq_eoi only writes to the GIC_CPU_EOI register but for
an interrupt to be properly cleared by the GIC, a read from
GIC_CPU_INTACK must come first. The only place the irq-gic driver reads
this is in the actual interrupt handler so we cannot access it from the
driver.
To get around this, let's map the GIC_CPU_BASE and read the
GIC_CPU_INTACK register ourselves before calling irq_eoi to properly ack
late timer interrupts that show up during suspend on am437x.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
ARM: OMAP2+: timer: Ack pending interrupt during suspend
It is possible that when suspending the clock event timer it will generate
an interrupt just before their suspend is completed, but after interrupts have
been disabled. In this case any pending interrupts will prevent suspend, so
ACK the timer interrupt to avoid this.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
It is possible that when suspending the clock event timer it will generate
an interrupt just before their suspend is completed, but after interrupts have
been disabled. In this case any pending interrupts will prevent suspend, so
ACK the timer interrupt to avoid this.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
soc: ti: wkup_m3_ipc: Add debug option to halt m3 in suspend
Add a debugfs option to allow configurable halting of the wkup_m3
during suspend at the last possible point before low power mode entry.
This condition can only be resolved through JTAG and advancing beyond
the while loop in a8_lp_ds0_handler. Although this hangs the system it
forces the system to remain active once it has been entirely configured
for low power mode entry, allowing for register inspection through JTAG
to help in debugging transition errors.
Halt mode can be set using the enable_off_mode entry under wkup_m3_ipc
in the debugfs.
Suggested-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Add a debugfs option to allow configurable halting of the wkup_m3
during suspend at the last possible point before low power mode entry.
This condition can only be resolved through JTAG and advancing beyond
the while loop in a8_lp_ds0_handler. Although this hangs the system it
forces the system to remain active once it has been entirely configured
for low power mode entry, allowing for register inspection through JTAG
to help in debugging transition errors.
Halt mode can be set using the enable_off_mode entry under wkup_m3_ipc
in the debugfs.
Suggested-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
soc: ti: wkup_m3_ipc: Fix race condition with rproc_boot
Any user of wkup_m3_ipc calls wkup_m3_ipc_get to get a handle and this
checks the value of the static variable m3_ipc_state to see if the
wkup_m3 is ready. Currently this is populated during probe before
rproc_boot has been called, meaning there is a window of time that
wkup_m3_ipc_get can return a valid handle but the wkup_m3 itself is not
ready, leading to invalid IPC calls to the wkup_m3 and system
instability.
To avoid this, move the population of the m3_ipc_state variable until
after rproc_boot has succeeded to guarantee a valid and usable handle
is always returned.
Reported-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Any user of wkup_m3_ipc calls wkup_m3_ipc_get to get a handle and this
checks the value of the static variable m3_ipc_state to see if the
wkup_m3 is ready. Currently this is populated during probe before
rproc_boot has been called, meaning there is a window of time that
wkup_m3_ipc_get can return a valid handle but the wkup_m3 itself is not
ready, leading to invalid IPC calls to the wkup_m3 and system
instability.
To avoid this, move the population of the m3_ipc_state variable until
after rproc_boot has succeeded to guarantee a valid and usable handle
is always returned.
Reported-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
ARM: dts: am4372: Add idle_states for cpuidle
Add idle_states table for CPU on am437x. Currently just add C1 state
which gates the MPU clock domain.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Add idle_states table for CPU on am437x. Currently just add C1 state
which gates the MPU clock domain.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>