UefiCpuPkg/Include: Add Xeon E7 MSR include file

Add Xeon E7 MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-7.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
new file mode 100644 (file)
index 0000000..b95f963
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
@@ -0,0 +1,254 @@
+/** @file\r
+  MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.\r
+\r
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+  are provided for MSRs that contain one or more bit fields.  If the MSR value\r
+  returned is a single 32-bit or 64-bit value, then a data structure is not\r
+  provided for that MSR.\r
+\r
+  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+  @par Specification Reference:\r
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-7.\r
+\r
+**/\r
+\r
+#ifndef __XEON_E7_MSR_H__\r
+#define __XEON_E7_MSR_H__\r
+\r
+#include <Register/ArchitecturalMsr.h>\r
+\r
+/**\r
+  Package. Reserved Attempt to read/write will cause #UD.\r
+\r
+  @param  ECX  MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);\r
+  AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_XEON_E7_TURBO_RATIO_LIMIT            0x000001AD\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 8 perfmon local box control MSR.\r
+\r
+  @param  ECX  MSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);\r
+  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_XEON_E7_C8_PMON_BOX_CTRL             0x00000F40\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 8 perfmon local box status MSR.\r
+\r
+  @param  ECX  MSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);\r
+  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_XEON_E7_C8_PMON_BOX_STATUS           0x00000F41\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 8 perfmon local box overflow control MSR.\r
+\r
+  @param  ECX  MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);\r
+  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL         0x00000F42\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 8 perfmon event select MSR.\r
+\r
+  @param  ECX  MSR_XEON_E7_C8_PMON_EVNT_SELn\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);\r
+  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);\r
+  @endcode\r
+  @{\r
+**/\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL0            0x00000F50\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL1            0x00000F52\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL2            0x00000F54\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL3            0x00000F56\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL4            0x00000F58\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL5            0x00000F5A\r
+/// @}\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 8 perfmon counter MSR.\r
+\r
+  @param  ECX  MSR_XEON_E7_C8_PMON_CTRn\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);\r
+  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);\r
+  @endcode\r
+  @{\r
+**/\r
+#define MSR_XEON_E7_C8_PMON_CTR0                 0x00000F51\r
+#define MSR_XEON_E7_C8_PMON_CTR1                 0x00000F53\r
+#define MSR_XEON_E7_C8_PMON_CTR2                 0x00000F55\r
+#define MSR_XEON_E7_C8_PMON_CTR3                 0x00000F57\r
+#define MSR_XEON_E7_C8_PMON_CTR4                 0x00000F59\r
+#define MSR_XEON_E7_C8_PMON_CTR5                 0x00000F5B\r
+/// @}\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 9 perfmon local box control MSR.\r
+\r
+  @param  ECX  MSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);\r
+  AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_XEON_E7_C9_PMON_BOX_CTRL             0x00000FC0\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 9 perfmon local box status MSR.\r
+\r
+  @param  ECX  MSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);\r
+  AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_XEON_E7_C9_PMON_BOX_STATUS           0x00000FC1\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 9 perfmon local box overflow control MSR.\r
+\r
+  @param  ECX  MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);\r
+  AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);\r
+  @endcode\r
+**/\r
+#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL         0x00000FC2\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 9 perfmon event select MSR.\r
+\r
+  @param  ECX  MSR_XEON_E7_C9_PMON_EVNT_SELn\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);\r
+  AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);\r
+  @endcode\r
+  @{\r
+**/\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL0            0x00000FD0\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL1            0x00000FD2\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL2            0x00000FD4\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL3            0x00000FD6\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL4            0x00000FD8\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL5            0x00000FDA\r
+/// @}\r
+\r
+\r
+/**\r
+  Package. Uncore C-box 9 perfmon counter MSR.\r
+\r
+  @param  ECX  MSR_XEON_E7_C9_PMON_CTRn\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);\r
+  AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);\r
+  @endcode\r
+  @{\r
+**/\r
+#define MSR_XEON_E7_C9_PMON_CTR0                 0x00000FD1\r
+#define MSR_XEON_E7_C9_PMON_CTR1                 0x00000FD3\r
+#define MSR_XEON_E7_C9_PMON_CTR2                 0x00000FD5\r
+#define MSR_XEON_E7_C9_PMON_CTR3                 0x00000FD7\r
+#define MSR_XEON_E7_C9_PMON_CTR4                 0x00000FD9\r
+#define MSR_XEON_E7_C9_PMON_CTR5                 0x00000FDB\r
+/// @}\r
+\r
+#endif\r