| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | |
| Wed, 17 Feb 2016 14:37:58 +0000 (15:37 +0100) | ||
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | |
| Wed, 24 Feb 2016 08:18:44 +0000 (09:18 +0100) | ||
| commit | f9bbb8d9c3f065faba9f266cf4e731fe2ca70c4d | |
| tree | f6458e36c395a5c20ea2ac8c5f662235ccdf9c80 | tree | snapshot (tar.xz tar.gz zip) |
| parent | 0d4a6c3dfc06d7d5769c19a3d112c5fdeae70525 | commit | diff |
MdeModulePkg: AcpiTableDxe: make 4 GB table allocation limit optional
AARCH64 systems never require compatibility with legacy ACPI OSes, and
may not have any 32-bit addressable system RAM. To support ACPI on these
systems, we need to be able to relax the 4 GB allocation restriction.
So add a PCD PcdAcpiExposedTableVersions containing a bitmask describing
which ACPI versions are targeted, and wire it up it up to the memory
allocation calls in AcpiTableDxe/AcpiTableProtocol.c. I.e., if ACPI v1.0b
is not among the supported versions, the memory allocations are not limited
to 4 GB, and only table types that carry 64-bit addresses are emitted.
Note that this will inhibit the publishing of any tables that carry only
32-bit addresses, i.e., RSDPv1, RSDTv1 and RSDTv3.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
AARCH64 systems never require compatibility with legacy ACPI OSes, and
may not have any 32-bit addressable system RAM. To support ACPI on these
systems, we need to be able to relax the 4 GB allocation restriction.
So add a PCD PcdAcpiExposedTableVersions containing a bitmask describing
which ACPI versions are targeted, and wire it up it up to the memory
allocation calls in AcpiTableDxe/AcpiTableProtocol.c. I.e., if ACPI v1.0b
is not among the supported versions, the memory allocations are not limited
to 4 GB, and only table types that carry 64-bit addresses are emitted.
Note that this will inhibit the publishing of any tables that carry only
32-bit addresses, i.e., RSDPv1, RSDTv1 and RSDTv3.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>