imx6: decrease wilink8 sdio pins drive strength

The original drive strength value of 90 OHM was too strong causing
detection issues of some modules on the sdio bus.
Reducing the io strength to 50 OHM solves this issue.
Add a kernel patch for fixing this issue on the SABRE board and SoloLite
platforms.

Signed-off-by: Eyal Reizer <eyalr@ti.com>

diff --git a/patches/kernel_patches/imx-3.10.53/0009-imx6-decrease-wilink8-sdio-pins-drive-strength.patch b/patches/kernel_patches/imx-3.10.53/0009-imx6-decrease-wilink8-sdio-pins-drive-strength.patch
new file mode 100644 (file)
index 0000000..bd6f280
--- /dev/null
+++ b/patches/kernel_patches/imx-3.10.53/0009-imx6-decrease-wilink8-sdio-pins-drive-strength.patch
@@ -0,0 +1,64 @@
+From 3f1b360d3954c688eb1f2e0e51d59b60006c4163 Mon Sep 17 00:00:00 2001
+From: Eyal Reizer <eyalr@ti.com>
+Date: Thu, 2 Apr 2015 14:47:15 +0300
+Subject: [PATCH] imx6: decrease wilink8 sdio pins drive strength
+
+The original drive strength value of 90 OHM was too strong causing
+detection issues of some modules on the sdio bus.
+Reducing the io strength to 50 OHM solves this issue
+
+Signed-off-by: Eyal Reizer <eyalr@ti.com>
+---
+ arch/arm/boot/dts/imx6qdl.dtsi |   12 ++++++------
+ arch/arm/boot/dts/imx6sl.dtsi  |   12 ++++++------
+ 2 files changed, 12 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
+index 2442393..42482f5 100644
+--- a/arch/arm/boot/dts/imx6qdl.dtsi
++++ b/arch/arm/boot/dts/imx6qdl.dtsi
+@@ -1653,12 +1653,12 @@
+ 
+               pinctrl_usdhc2_2: usdhc2grp-2 {
+                       fsl,pins = <
+-                              MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
+-                              MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
+-                              MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+-                              MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+-                              MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+-                              MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
++                              MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17069
++                              MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10069
++                              MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069
++                              MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069
++                              MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069
++                              MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069
+                       >;
+               };
+       };
+diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
+index 260d431..0010ff4 100644
+--- a/arch/arm/boot/dts/imx6sl.dtsi
++++ b/arch/arm/boot/dts/imx6sl.dtsi
+@@ -1311,12 +1311,12 @@
+       usdhc3 {
+               pinctrl_usdhc3_1: usdhc3grp-1 {
+                       fsl,pins = <
+-                              MX6SL_PAD_SD3_CMD__SD3_CMD    0x17059
+-                              MX6SL_PAD_SD3_CLK__SD3_CLK    0x10059
+-                              MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+-                              MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+-                              MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+-                              MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++                              MX6SL_PAD_SD3_CMD__SD3_CMD    0x17069
++                              MX6SL_PAD_SD3_CLK__SD3_CLK    0x10069
++                              MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17069
++                              MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17069
++                              MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17069
++                              MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17069
+                               MX6SL_PAD_SD1_DAT2__GPIO5_IO13  0x13059   // reserve two pins from sd1 for wl8 gpio, this is pulled low at reset for WL_EN
+                               MX6SL_PAD_SD1_DAT1__GPIO5_IO08  0x13059   // this is for wl_irq which driver will configure as an input with a pull down
+                       >;
+-- 
+1.7.9.5
+